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5.1 Overview of the Status Report/5.2 Status Byte
Overview of Registers and Queues
Name
Function
Status byte
Service request
Masks status byte.
enable register
Standard event
Change in device
register
status
Standard event
Masks standard
enable register
event register
Extended event
Change in device
register
status
Extended event
Masks standard
enable register
event register
Condition
Current instrument status —
register
Transit
Extended event
filter
occurrence conditions
Output queue
Stores response message All executable queues
to a query.
Error queue
Stores error Nos.
and messages.
Registers and Queues which Affect the Status Byte
Registers which affect each bit of the status byte are
shown below.
Standard event register : Sets bit 5 (ESB) of status
Output queue
Extended event register : Sets bit 3 (EES) of status
Error queue
Enable Registers
Registers which mask a bit so that the bit does not
affect the status byte, even if the bit is set to "
shown below.
Status byte
Standard event register : Masks bits using the
Extended event register : Masks bits using the
Writing/Reading from Registers
The
command is used to set bits in the standard
*ESE
event enable register to "
is used to check whether bits in that register are set to
"
1
" or "
0
". For details of these commands, refer to
Chapter 4.
5-2
Writing
Reading
—
Serial poll (RQS),
*STB?(MSS)
*SRE
*SRE?
—
*ESR?
*ESE
*ESE?
—
STATus:EESR?
STATus:EESE
STATus:EESE?
STATus:CONDition?
STATus:FILTer
STATus:FILTer<x>?
<x>
—
STATus:ERRor?
byte to "
1
" or "
0
".
: Sets bit 4 (MAV) of status
byte to "
" or "
".
1
0
byte to "
1
" or "
0
".
: Sets bit 2 (EAV) of status
byte to "
1
" or "
0
".
", are
1
: Masks bits using the service
request enable register.
standard event enable
register.
extended event enable
register.
1
" or "
0
", and the
*ESR?
5.2 Status Byte
Overview of Status Byte
RQS
7
6 ESB MAV EES EAV 1
MSS
Bits 0, 1 and 7
Not used (always "
Bit 2 EAV (Error Available)
Set to "
" when the error queue is not empty, i.e. when
1
an error occurs. For details, refer to page 5-5.
Bit 3 EES (Extended Event Summary Bit)
Sets to "
1
" when the logical "AND" of an Extended
Event Register bit and the corresponding Enable
Register bit is equal to "
takes place in the instrument. Refer to page 5-4.
Bit 4 MAV (Message Available)
Set to "
1
" when the output queue is not empty, i.e.
when there is data which is to be output when an query
is made. Refer to page 5-5.
Bit 5 ESB (Event Summary Bit)
Set to "
" when the logical AND of the standard event
1
register and the corresponding enable register is "
i.e. when an event takes place in the instrument. Refer
to page 5-3.
Bit 6 RQS (Request Status)/MSS (Master Summary
Status)
Sets to "
1
" when the logical "AND" of any one of the
Status Byte bits (other than bit 6) and the
corresponding Service Request Enable Register bit
becomes "
requesting service from the controller.
RQS is set to "
and is cleared when a serial poll is performed or when
MSS changes to "
Bit Masking
To mask a bit in the status byte so that it does not
cause an SRQ, set the corresponding bit of the service
request enable register to "
query
For example, to mask bit 2 (EAV) so that no service
will be requested, even if an error occurs, set bit 2 of
the service request enable register to "
done using the
each bit of the service request enable register is "
"0", use
*SRE?
to Chapter 4.
0
0
")
."—that is, when an event
1
1
"—that is, when the instrument is
" when MSS changes from "
1
0
".
0
".
*SRE
command. To query whether
. For details of the
*SRE
1
",
" to "
",
0
1
0
". This can be
" or
1
command, refer
IM 253710-11E
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