Setting/Resetting Bit Addresses, continued
The RLO is written to the address of the instruction. The instructions can be dependent on the MCR (see page 97).
Instru
Instru
Instru
Address
Address
Address
Ction
Ction
ID
=
Assign RLO
I/Q
a.b
To input/output
M
a.b
To bit memory
L
a.b
To local data bit
DBX
a.b
To data bit
DIX
a.b
To instance data bit
c [d]
Memory-indirect, area-internal ***
c [AR1,m]
Register-indirect, area-internal (AR1) ***
c [AR2,m]
Register-indirect, area-internal (AR2) ***
[AR1,m]
Area-crossing (AR1) ***
[AR2,m]
Area-crossing (AR2) ***
Parameter
Via parameter ***
Status word for:
=
Instruction evaluates:
Instruction affects:
+
Plus time required for loading the address of the instruction (see page 20)
*)
With direct instruction addressing; Address area 0 to 127
)
**
With direct instruction addressing; Address area 0 to 255
***)I, Q, M, L / DB, DI
S7-400 Instruction List
A5E00267845-01
Description
Description
BR
CC1
–
–
–
–
Setting/Resetting Bit Addresses
Execution Time in ms
Execution Time in ms
Length
Length
Length
in
in
CPU 412
CPU 414
Words
1*/2
0.2
0.12
1**/2
0.2
0.12
2
0.2
0.12
2
0.3
0.18
2
0.3
0.18
2
0.2+/0.3+
0.12+/0.18+
2
0.2+/0.3+
0.12+/0.18+
2
0.2+/0.3+
0.12+/0.18+
2
0.2+/0.3+
0.12+/0.18+
2
0.2+/0.3+
0.12+/0.18+
2
0.2+/0.3+
0.12+/0.18+
CC0
OV
OS
–
–
–
–
–
–
CPU 416
CPU 417
0.08
0.06
0.08
0.06
0.08
0.06
0.12
0.12
0.12
0.12
0.08+/0.12+
0.06+/0.12+
0.08+/0.12+
0.06+/0.12+
0.08+/0.12+
0.06+/0.12+
0.08+/0.12+
0.06+/0.12+
0.08+/0.12+
0.06+/0.12+
0.08+/0.12+
0.06+/0.12+
OR
STA
RLO
–
–
Yes
0
Yes
–
/FC
–
0
40