Siemens CPU 412-1 Instruction Manual page 28

Bit Logic Instructions, continued
Instr.
Address
ID
O/ON OR/OR-NOT
I/Q a.b Input/output
M a.b Bit memory
L a.b Local da
DBX a.b Data bit
DIX a.b Instance data bit
c [d] Memory-indirect, area-internal ***
c [AR1,m] Register-ind., area-internal (AR1) ***
c [AR2,m] Register-ind., area-internal (AR2) ***
[AR1,m] Area-crossing (AR1) ***
[AR2,m] Area-crossing (AR2) ***
Parameter Via parameter ***
Statusword for: O, ON
Instruction evaluates:
Instruction affects:
+ Plus time required for loading the address of the instruction (see page 20)
*)
With direct instruction addressing; Address area 0 to 127
)
** With direct instruction addressing; Address area 0 to 255
)
*** I,Q,M,L / DB, DI
S7-400 Instruction List
A5E00267845-01
Length
Description
Words
1**/2
BR CC1
– –
– –
in CPU 412 CPU 414
1*/2 0.1/0.125 0.06/0.075
0.1/0.125 0.06/0.075
2 0.125 0.075
2 0.2
2 0.2
2 0.1+/0.2+ 0.06+/0.12+
2 0.125+/0.2+ 0.075+/0.12+
2 0.125+/0.2+ 0.075+/0.12+
2 0.125+/0.2+ 0.075+/0.12+
2 0.125+/0.2+ 0.075+/0.12+
2 0.125+/0.2+ 0.075+/0.12+
CC0 OV OS
– – –
– – –
Bit Logic Instructions
CPU 416
0.04/0.05
0.04/0.05
0.05
0.12 0.08
0.12 0.08
0.04+/0.08+ 0.03+/0.09+
0.05+/0.08+ 0.042+/0.09+
0.05+/0.08+ 0.042+/0.09+
0.05+/0.08+ 0.042+/0.09+
0.05+/0.08+ 0.042+/0.09+
0.05+/0.08+ 0.042+/0.09+
OR STA RLO
– – Yes
0 Yes Yes
CPU 417
0.03/0.042
0.03/0.042
0.042
0.09
0.09
/FC
Yes
1
26