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Siemens CPU 412-1 Instruction Manual Page 29

S7-400; cpu 412 series; cpu 414 series; cpu 416 series; cpu 417 series;.
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Bit Logic Instructions, continued
Instr.
Instr.
Address-
Address-
ID
X/XN
EXKLUSIV-OR/
EXKLUSIV-OR-NOT
E/A
a.b
Input/output
M
a.b
Bit memory
L
a.b
Local data bit
DBX
a.b
Data bit
DIX
a.b
Instance data bit
c [d]
Memory-indirect, area-internal.
c [AR1,m]
Register-ind., area-internal (AR1)
c [AR2,m]
Register-ind., area-internal (AR2)
[AR1,m]
Area-crossing (AR1)
[AR2,m]
Area-crossing (AR2)
Parameter
Via parameter
Status word for:
X, XN
Instruction evaluates:
Instruction affects:
+Plus time required for loading the address of the instruction (see page 20)
*)
I,Q,M,L / DB, DI
S7-400 Instruction List
A5E00267845-01
Lengt
Lengt
Description
Description
h in
h in
h in
Words
Words
*)
*)
*)
*)
*)
*)
BR
CC1
Execution Time in ms
Execution Time in ms
CPU 412
CPU 414
2
0.125
0.075
2
0.125
0.075
2
0.125
0.075
2
0.2
0.12
2
0.2
0.12
2
0.1+/0.2+
0.06+/0.12+
2
0.125+/0.2+
0.075+/0.12+
2
0.125+/0.2+
0.075+/0.12+
2
0.125+/0.2+
0.075+/0.12+
2
0.125+/0.2+
0.075+/0.12+
2
0.125+/0.2+
0.075+/0.12+
CC0
OV
OS
Bit Logic Instructions
CPU 416
CPU 417
0.05
0.042
0.05
0.042
0.05
0.042
0.08
0.09
0.08
0.09
0.04+/0.08+
0.03+/0.09+
0.05+/0.08+
0.042+/0.09+
0.05+/0.08+
0.042+/0.09+
0.05+/0.08+
0.042+/0.09+
0.05+/0.08+
0.042+/0.09+
0.05+/0.08+
0.042+/0.09+
OR
STA
RLO
Yes
0
Yes
Yes
/FC
Yes
1
27

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