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Bit Logic Instructions - Siemens CPU 412-1 Instruction Manual

S7-400; cpu 412 series; cpu 414 series; cpu 416 series; cpu 417 series;.
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Bit Logic Instructions

All logic instructions generate a result (new RLO). The first instruction in a logic string generates the new RLO from the signal state
scanned. The subsequent logic instructions generate the new RLO from the signal state scanned and the old RLO. The logic string ends
with an instruction which limits the RLO (e.g. a memory instruction); that is, the /FC bit is set to zero.
Instr.
Instr.
Instr.
Address
Address
Address
ID
U/UN
I/Q
a.b
Input/output
M
a.b
Bit memory
L
a.b
Local data bit
DBX
a.b
Data bit
DIX
a.b
Instance data bit
c [d]
Memory-indirect, area-internal***
c [AR1,m]
Register-ind., area-internal (AR1)***
c [AR2,m]
Register-ind., area-internal (AR2)***
[AR1,m]
Area-crossing (AR1)***
[AR2,m]
Area-crossing (AR2)***
Parameter
Via parameter ***
Statusword for:
U/UN
Instruction depends on:
Instruction affects:
+
Plus time required for loading the address of the instruction (see page 20)
*)
With direct instruction addressing;Address area 0 to 127
)
**
With direct instruction addressing;Address area 0 to 255
)
***
I,Q,M,L / DB, DI
S7-400 Instruction List
A5E00267845-01
Length
Length
Length
Description
Description
Words
BIE
A1
Execution Time in ms
Execution Time in ms
in
in
CPU 412
CPU 414
1*/2
0.1/0.125
0.06/0.075
1**/2
0.1/0.125
0.06/0.075
2
0.125
0.075
2
0.2
2
0.2
2
0.1+/0.2+
0.06+/0.12+
2
0.125+/0.2+
0.075+/0.12+
2
0.125+/0.2+
0.075+/0.12+
2
0.125+/0.2+
0.075+/0.12+
2
0.125+/0.2+
0.075+/0.12+
2
0.125+/0.2+
0.075+/0.12+
A0
OV
OS
Bit Logic Instructions
CPU 416
0.04/0.05
0.04/0.05
0.05
0.12
0.08
0.12
0.08
0.04+/0.08+
0.03+/0.09+
0.05+/0.08+
0.042+/0.09+
0.05+/0.08+
0.042+/0.09+
0.05+/0.08+
0.042+/0.09+
0.05+/0.08+
0.042+/0.09+
0.05+/0.08+
0.042+/0.09+
OR
STA
RLO
Yes
Yes
Yes
Yes
Yes
CPU 417
0.03/0.042
0.03/0.042
0.042
0.09
0.09
/FC
Yes
1
25

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