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Edge-triggered Instructions - Siemens CPU 412-1 Instruction Manual

S7-400; cpu 412 series; cpu 414 series; cpu 416 series; cpu 417 series;.
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Edge-Triggered Instructions

The current RLO is compared with the status of the instruction or "edge bit memory". FP detects a change from "0" to "1"; FN detects a
change from "1" to "0".
Instruc-
Instruc-
Instruc-
Address ID
Address ID
tion
tion
FP/FN
I/Q
a.b
M
a.b
)
L
a.b*
DBX
a.b
DIX
a.b
c [d]
c [d]
c [AR1,m] **
c [AR2,m] **
[AR1,m]**
[AR2,m]**
Parameter**
Status word for:
FP, FN
Instruction evaluates:
Instruction affects:
+
Plus time required for loading the address of the instruction (see page 20)
*)
Unnecessary if the bit being monitored is in the process image (local data of a block are only valid while the block is running).
**)
I, Q, M, L /DB, DI
S7-400 Instruction List
A5E00267845-01
Description
Description
The positive/negative edge is
indicated by RLO = 1. The bit
addressed in the instruction is
the auxiliary edge bit memory.
BR
Length
Length
in
in
in
Words
Words
CPU 412
2
0.2
2
0.2
2
0.2
2
0.3
2
0.3
2
2
0.2+/0.3+
0.2+/0.3+
2
0.2+/0.3+
2
0.2+/0.3+
2
0.2+/0.3+
2
0.2+/0.3+
2
0.2+/0.3+
CC1
CC0
OV
Edge-Triggered Instructions
Execution Time in ms
Execution Time in ms
CPU 414
CPU 416
0.12
0.08
0.12
0.08
0.12
0.08
0.18
0.12
0.18
0.12
0.12+/0.18+
0.12+/0.18+
0.08+/0.12+
0.08+/0.12+
0.12+/0.18+
0.08+/0.12+
0.12+/0.18+
0.08+/0.12+
0.12+/0.18+
0.08+/0.12+
0.12+/0.18+
0.08+/0.12+
0.12+/0.18+
0.08+/0.12+
OS
OR
STA
0
Yes
CPU 417
0.06
0.06
0.06
0.12
0.12
0.06+/0.12+
0.06+/0.12+
0.06+/0.12+
0.06+/0.12+
0.06+/0.12+
0.06+/0.12+
0.06+/0.12+
RLO
/FC
Yes
Yes
1
38

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