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Siemens CPU 412-1 Instruction Manual

S7-400; cpu 412 series; cpu 414 series; cpu 416 series; cpu 417 series;.
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S7-400 Instruction List
CPU 412, 414, 416, 417
This Instruction List has the order number:
6ES7498-8AA04-8BN0
Edition 04/2004
A5E00267845-01

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   Summary of Contents for Siemens CPU 412-1

  • Page 1 S7-400 Instruction List CPU 412, 414, 416, 417 This Instruction List has the order number: 6ES7498-8AA04-8BN0 Edition 04/2004 A5E00267845-01...
  • Page 2 Copyright Siemens AG 2004 All rights reserved Disclaimer of Liability The reproduction, transmission or use of this document or its We have checked the contents of this manual for agreement with the contents is not permitted without express written authority.
  • Page 3: Table Of Contents

    Contents Contents Contents ................Applicability .
  • Page 4 Contents ORing of AND Instructions ............Logic Instructions with Timers and Counters .
  • Page 5 Contents Floating-Point Math (32 Bits) ........... . Square Root and Square Instructions (32 Bits) .
  • Page 6 Contents Block End Instructions ............Exchanging Shared Data Block and Instance Data Block .
  • Page 7: Applicability

    Applicability Applicability This list of instructions applies to the CPUs listed below. Name Order number subsequently described as* CPU 412-1 6ES7412-1XF04-0AB0 CPU 412 CPU 412 CPU 412-2 6ES7412-2XG04-0AB0 CPU 414-2 6ES7414-2XG04-0AB0 CPU 414-3 6ES7414-3XJ04-0AB0 CPU 414 CPU 414 CPU 414-4H...
  • Page 8: Address Identifier And Parameter Ranges

    Address Identifier and Parameter Ranges Address Identifier and Parameter Ranges Addr. Parameter Range Description Description CPU 412 CPU 414 CPU 416 CPU 417 0.0 to 127.7 0.0 to 255.7 0.0 to 511.7 0.0 to 1023.7 Output (in PIQ) 0 to 127 0 to 255 0 to 511 0 to 1023...
  • Page 9: Address Identifier And Parameter Ranges, Continued

    Address Identifier and Parameter Ranges Address Identifier and Parameter Ranges, continued Addr. Parameter Range Description Description CPU 412 CPU 414 CPU 416 CPU 417 0.0 to 127.7 0.0 to 255.7 0.0 to 511.7 0.0 to 1023.7 Input bit (in PII) IB** 0 to 127 0 to 255...
  • Page 10: Address Identifier And Parameter Ranges, Continued

    Address Identifier and Parameter Ranges Address Identifier and Parameter Ranges, continued Addr. Parameter Range Description Description CPU 412 CPU 414 CPU 416 CPU 417 0 to 4095 0 to 8191 0 to 16383 0 to 16383 Peripheral output byte (direct I/O access) 0 to 4094 0 to 8190 0 to 16382...
  • Page 11: Constants And Ranges

    Constants and Ranges Constants and Ranges Constant Range Description B(b1,b2) – Constant, 2 or 4 bytes B(b1,b2,b3,b4) D# Date – IEC date constant L# Integer – 32-bit integer constant P# Bit pointer – Pointer constant S5T# Time value – S7 time constant T# TIme value –...
  • Page 12: Abbreviations And Mnemonics

    Abbreviations and Mnemonics Abbreviations and Mnemonics The following abbreviations and mnemonics are used in the Instruction List: Abbrev. Description Example 8-bit constant 0 to 255 16-bit constant 28 131 256 to 32 767 32-bit constant 127 624 32 768 to 999 999 999 8-bit integer -113 -128 to +127...
  • Page 13: Abbreviations And Mnemonics, Continued

    Abbreviations and Mnemonics Abbreviations and Mnemonics, continued Abbrev. Description Example Bit address Address area I, Q, M, L, DBX, DIX Address in: MD, DBD, DID or LD Number in: MW, DBW, DIW or LW Timer/counter No. Address area IB, QB, PIB, PQB, MB, LB, DBB, DIB Address area IW, QW, PIW, PQW, MW,...
  • Page 14: Registers

    Registers Registers ACCU1 to ACCU4 (32 Bits) The accumulators are registers for processing bytes, words or double words. The address identifiers are loaded into the accumulators, where they are logically gated. The result of the logic operation (RLO) is in ACCU1 and can be transferred from there to a memory cell. The accumulators are 32 bits long.
  • Page 15 Registers Address Registers AR1 and AR2 (32 Bits) The address registers contain the area-internal or area-crossing pointers for instructions using indirect addressing. The address registers are 32 bits long. The area-internal and/or area-crossing pointers have the following syntax: • Area-internal pointer 00000000 00000bbb bbbbbbbb bbbbbxxx •...
  • Page 16 Registers Status Word (16 Bits) The status word bits are evaluated or set by the instructions. The status word is 16 bits long. Assignment Description First check bit Result of logic operation Status Or (AND before OR) Stored overflow Overflow CC 0 Condition code 0 CC 1...
  • Page 17: Examples Of Addressing

    Examples of Addressing Examples of Addressing Addressing Examples Description Immediate Addressing L +27 Load 16-bit integer constant “27” into ACCU1 L L#-1 Load 32-bit integer constant “-1” into ACCU1 L 2#1010101010101010 Load binary constant into ACCU1 L DW#16#A0F0BCFD Load hexadecimal constant into ACCU1 L ’ENDE’...
  • Page 18 Examples of Addressing Addressing Examples Description Direct Addressing A I 0.0 ANDing of input bit 0.0 L IB 1 Load input byte 1 into ACCU1 L IW 0 Load input word 0 into ACCU1 L ID 0 Load input double word 0 into ACCU1 Indirect Addressing of Timers/Counters SP T [LW 8] Start timer;...
  • Page 19: Examples Of Addressing, Continued

    Examples of Addressing Examples of Addressing, continued Addressing Examples Area-Internal Register-Indirect Addressing A I [AR1,P#12.2] Area-Crossing Register-Indirect Addressing For area-crossing register-indirect addressing, the address must also contain an area identifier. The address is in the address register. The area identifiers are as follows: Area Coding Area...
  • Page 20: Examples Of How To Calculate The Pointer

    Examples of how to calculate the pointer Examples of how to calculate the pointer • Example for sum of bit addresses x7: LAR1 P#8.2 A I [AR1,P#10.2] Result: Input 18.4 is addressed (by adding the byte and bit addresses) • Example for sum of bit addressesu7: L P#10.5 LAR1 A I [AR1,P#10.7]...
  • Page 21: Execution Times With Indirect Addressing1

    Execution Times with Indirect Addressing1 Execution Times with Indirect Addressing1 When using indirect addresses statement consists of two parts: Part 1: Load the address of the instruction Part 2: Execute the instruction In other words, when working with indirect addresses, you must calculate the execution time of an instruction from these two parts. Calculating the Execution Time The total execution time is calculated as follows: Time required for loading the address...
  • Page 22 Execution Times with Indirect Addressing1 The execution time for loading the address of the instruction from the various areas is shown in the following table. Execution Time in ms Address is in ... CPU 412 CPU 414 CPU 416 CPU 417 Bit memory area M Word 0.12...
  • Page 23: Examples Of Calculations

    Examples of Calculations Examples of Calculations You will find a few examples here for calculating the execution times for the various methods of indirect addressing. Calculating the Execution Times for Area-Internal Memory-Indirect Addressing Example: A I [DBD 12] with CPU 414 Step 1: Load the contents of DBD 12 (time required is listed in the table on page 20) Execution Time in ms...
  • Page 24 Examples of Calculations Execution Time for Area-Crossing Register-Indirect Addressing Example: A [AR1, P#23.1] ... with I 1.0 in AR1 with CPU 416 Step 1: Load the contents of AR1, and increment them by the offset 23.1 (the time required is in the table on page 20) Execution Time in ms Address is in ...
  • Page 25 Examples of Calculations Execution Time for Addressing Via Parameters Example A Parameter ... with I 0.5 in the block parameter list with CPU 414 Step 1: Load input I 0.5 addressed via the parameter (the time required is in the table on page 20) Execution Time in ms Address is in ...
  • Page 26: List Of Instructions

    List of Instructions List of Instructions This chapter contains the complete list of instructions for the S7-400 CPUs. The descriptions have been kept as concise as possible. You will find a detailed functional description in the various STEP 7 reference manuals. Please note that, in the case of indirect addressing (examples see page LEERER MERKER), you must add the time required for loading the address of the particular instruction to the execution times listed (see page 20).
  • Page 27: Bit Logic Instructions

    Bit Logic Instructions Bit Logic Instructions All logic instructions generate a result (new RLO). The first instruction in a logic string generates the new RLO from the signal state scanned. The subsequent logic instructions generate the new RLO from the signal state scanned and the old RLO. The logic string ends with an instruction which limits the RLO (e.g.
  • Page 28 Bit Logic Instructions Bit Logic Instructions, continued Length Instr. Address Description CPU 412 CPU 414 CPU 416 CPU 417 Words O/ON OR/OR-NOT Input/output 1*/2 0.1/0.125 0.06/0.075 0.04/0.05 0.03/0.042 Bit memory 1**/2 0.1/0.125 0.06/0.075 0.04/0.05 0.03/0.042 Local da 0.125 0.075 0.05 0.042 Data bit 0.12...
  • Page 29 Bit Logic Instructions Bit Logic Instructions, continued Instr. Instr. Lengt Lengt Address- Address- Execution Time in ms Execution Time in ms Description Description h in h in h in Words Words CPU 412 CPU 414 CPU 416 CPU 417 X/XN EXKLUSIV-OR/ EXKLUSIV-OR-NOT Input/output...
  • Page 30: Bit Logic Instructions With Parenthetical Expressions

    Bit Logic Instructions with Parenthetical Expressions Bit Logic Instructions with Parenthetical Expressions Saving the RLO and OR bits and the relevant function identifier (A, AN, ...) to the nesting stack. Seven nesting levels are possible per block. After the right parenthesis, the logic operation indicated by the function identifier is performed on the saved RLO and the current RLO;...
  • Page 31: Bit Logic Instructions With Parenthetical Expressions, Continued

    Bit Logic Instructions with Parenthetical Expressions Bit Logic Instructions with Parenthetical Expressions, continued Address Execution Time in ms Length Description struc- struc- tion tion CPU 412 CPU 414 CPU 416 CPU 417 Words Right parenthesis, removing an 0.06 0.04 0.03 entry from the nesting stack.
  • Page 32: Oring Of And Instructions

    ORing of AND Instructions ORing of AND Instructions The ORing of AND instructions is implemented according to the rule: AND before OR. Address Execution Time in ms struc- Description Length tion CPU 412 CPU 414 CPU 416 CPU 417 Words ORing of AND operations 0.06 0.04...
  • Page 33: Logic Instructions With Timers And Counters

    Logic Instructions with Timers and Counters Logic Instructions with Timers and Counters Examining the status of the addressed timer/counter and gating the result with the RLO according to the appropriate logic function. Length Execution Time in ms Execution Time in ms struc- struc- Words...
  • Page 34 Logic Instructions with Timers and Counters Logic Instructions with Timers and Counters, continued Length Execution Time in ms Execution Time in ms struc- struc- Words Words Address ID Description tion CPU 412 CPU 414 CPU 416 CPU 417 O/ON Timer Timer, memory-indirect addr.
  • Page 35: Word Logic Instructions With The Contents Of Accumulator 1

    Word Logic Instructions with the Contents of Accumulator 1 Word Logic Instructions with the Contents of Accumulator 1 Gating the contents of ACCU1 and/or ACCU1-L with a word or double word according to the appropriate function. The word or double word is either specified in the instruction as an address or is in ACCU2.
  • Page 36 Word Logic Instructions with the Contents of Accumulator 1 Word Logic Instructions with the Contents of Accumulator 1, continued Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion tion CPU 412 CPU 414 CPU 416 CPU 417 Words AND ACCU2 0.04...
  • Page 37: Evaluating Conditions Using And, Or And Exclusive Or

    Evaluating Conditions Using AND, OR and EXCLUSIVE OR Evaluating Conditions Using AND, OR and EXCLUSIVE OR All logic instructions generate a result (new RLO). The first instruction in a logic string generates the new RLO from the signal state scanned. The subsequent logic instructions generate the new RL from the signal state scanned and the old RLO. The logic string ends with an instruction which limits the RLO (e.g.
  • Page 38 Evaluating Conditions Using AND, OR and EXCLUSIVE OR Evaluating Conditions Using AND, OR and EXCLUSIVE OR, continued Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words A/AN >=0 Result>=0 0.06...
  • Page 39 Evaluating Conditions Using AND, OR and EXCLUSIVE OR Evaluating Conditions Using AND, OR and EXCLUSIVE OR, continued Length Instruc- Address Execution Time in ms Description tion Words CPU 412 CPU 414 CPU 416 CPU 417 A/AN AND/AND-NOT O/ON OR/OR-NOT X/XN EXCLUSIVE-OR/ EXCLUSIVE-OR-NOT Unordered math instruction...
  • Page 40: Edge-triggered Instructions

    Edge-Triggered Instructions Edge-Triggered Instructions The current RLO is compared with the status of the instruction or “edge bit memory”. FP detects a change from “0” to “1”; FN detects a change from “1” to “0”. Length Length Execution Time in ms Execution Time in ms Instruc- Instruc-...
  • Page 41: Setting/resetting Bit Addresses

    Setting/Resetting Bit Addresses Setting/Resetting Bit Addresses Assigning the value “1” or “0” to the addressed instruction when RLO = 1. The instructions can be dependent on the MCR (see page 97). Execution Time in ms Execution Time in ms Instruc- Instruc- Instruc- Lengt...
  • Page 42 Setting/Resetting Bit Addresses Setting/Resetting Bit Addresses, continued The RLO is written to the address of the instruction. The instructions can be dependent on the MCR (see page 97). Execution Time in ms Execution Time in ms Instru Instru Instru Length Length Length Address...
  • Page 43: Instructions Directly Affecting The Rlo

    Instructions Directly Affecting the RLO Instructions Directly Affecting the RLO The following instructions have a direct effect on the RLO. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Set RLO to “0”...
  • Page 44: Timer Instructions

    Timer Instructions Timer Instructions Starting or resetting a timer. The time value must be in ACCU1-L. The instructions are triggered by an edge transition in the RLO; that is, when the status of the RLO has changed between two calls. Length Length Execution Time in ms...
  • Page 45 Timer Instructions Timer Instructions, continued Length Length Execution Time in ms Execution Time in ms Address Address struc- struc- Description Description CPU 412 CPU 414 CPU 416 CPU 417 tion Words Start timer as retentive ON delay 0.12 0.08 0.06 T [e] on edge change from “0”...
  • Page 46 Timer Instructions Timer Instructions, continued Length Length Execution Time in ms Execution Time in ms Address Address struc- struc- Description Description CPU 412 CPU 414 CPU 416 CPU 417 tion Words Enable timer for restarting on 0.12 0.08 0.06 T [e] edge change from “0”...
  • Page 47: Counter Instructions

    Counter Instructions Counter Instructions The count value must be in ACCU1-L in the form of a BCD number (0 - 999). Length Length Execution Time in ms Execution Time in ms struc- struc- Address ID Address ID Description Description CPU 412 CPU 414 CPU 416 CPU 417...
  • Page 48 Counter Instructions Counter Instructions, continued Length Length Execution Time in ms Execution Time in ms struc- struc- Address ID Address ID Description Description CPU 412 CPU 414 CPU 416 CPU 417 tion Words Decrement counter by 1 on edge 0.12 0.08 0.06 C [e]...
  • Page 49: Load Instructions

    Load Instructions Load Instructions Loading address identifiers into ACCU1. The contents of ACCU1 are first saved to ACCU2. The status word is not affected. Length Length Execution Time in ms Execution Time in ms Address Address struc- struc- Description Description CPU 412 CPU 414 CPU 416...
  • Page 50 Load Instructions Load Instructions, continued If there is a remainder of 3 following an integral division of the used addresses by 4, the execution times for instructions specified on this page are doubled. Length Length Execution Time in ms Execution Time in ms Address Address struc-...
  • Page 51 Load Instructions Load Instructions, continued If the used address is divisible by 4without a remainder, the execution times for instructions specified on this page is doubled. Length Length Execution Time in ms Execution Time in ms Address Address struc- struc- Description Description CPU 412...
  • Page 52 Load Instructions Load Instructions, continued Length Length Execution Time in ms Execution Time in ms Address Address struc- struc- Description Description CPU 412 CPU 414 CPU 416 CPU 417 tion Words Load ... 8-bit constant into ACCU1-LL 0.125 0.075 0.05 0.042 16-bit constant into ACCU1-L 0.125...
  • Page 53 Load Instructions Load Instructions, continued Length Length Execution Time in ms Execution Time in ms struc- struc- Address ID Address ID Description Description CPU 412 CPU 414 CPU 416 CPU 417 tion Words ’x’ Load 1 character 0.125 0.075 0.05 0.042 ’xx’...
  • Page 54 Load Instructions Load Instructions, continued Length Length Execution Time in ms Execution Time in ms struc- struc- Address ID Address ID Description Description CPU 412 CPU 414 CPU 416 CPU 417 tion Words P# bit pointer Load bit pointer 0.185 0.112 0.075 0.062...
  • Page 55: Load Instructions For Timers And Counters

    Load Instructions for Timers and Counters Load Instructions for Timers and Counters Loading a time value or count value into ACCU1. The contents of ACCU1 are first saved to ACCU2. The bits of the status word are not affected. Execution Time in ms Execution Time in ms Length Length...
  • Page 56: Transfer Instructions

    Transfer Instructions Transfer Instructions Transferring the contents of ACCU1 to the addressed operand. Note that some instructions are affected by the MCR (see page LEERER MERKER). The status word is not affected. Length Length Execution Time in ms Execution Time in ms Address Address struc-...
  • Page 57 Transfer Instructions Transfer Instructions, continued If there is a remainder of 3 following an integral division of the used addresses by 4, the execution times for instructions specified on this page are doubled. Instruc- Instruc- Length Length Execution Time in ms Execution Time in ms Address Address...
  • Page 58 Transfer Instructions Transfer Instructions, continued If the used address is divisible by 4without a remainder, the execution times for instructions specified on this page is doubled. Instruc- Instruc- Length Length Execution Time in ms Execution Time in ms Address Address tion tion Description...
  • Page 59: Load And Transfer Instructions For Address Registers

    Load and Transfer Instructions for Address Registers Load and Transfer Instructions for Address Registers Loading a double word from a memory area or register into address register 1 (AR1) or address register 2 (AR2). The status word is not affected. Execution Time in ms Length Length...
  • Page 60 Load and Transfer Instructions for Address Registers Load and Transfer Instructions forAddress Registers, continued Transferring a double word from address register 1 (AR1) or address register 2 (AR2) to a memory area or register. The contents of ACCU1 are first saved to ACCU2. The status word is not affected. Execution Time in ms Length Length...
  • Page 61: Load And Transfer Instructions For The Status Word

    Load and Transfer Instructions for the Status Word Load and Transfer Instructions for the Status Word Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Load status word into ACCU1 0.06 0.04 Status word for:...
  • Page 62: Load Instructions For Db Number And Db Length

    Load Instructions for DB Number and DB Length Load Instructions for DB Number and DB Length Loading the number/length of a data block into ACCU1. The old contents of ACCU1 are saved to ACCU2. The status word is not affected. Execution Time in ms Length Length...
  • Page 63: Integer Math (16 Bits)

    Integer Math (16 Bits) Integer Math (16 Bits) Math instructions on two 16-bit words. The result is written to ACCU1 and/or ACCU1-L. ACCU3 and ACCU4 are then transferred to ACCU2 and ACCU3. Execution Time in ms Length Length Instruc- Instruc- Address Address Description...
  • Page 64 Integer Math (16 Bits) Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Multiply 1 integer by another (16 bits) 0.06 0.04 0.03 (ACCU1)=(ACCU2-L) * (ACCU1-L) Divide 1 integer by another (16 bits) 0.24 0.16 0.12...
  • Page 65: Integer Math (32 Bits)

    Integer Math (32 Bits) Integer Math (32 Bits) Math instructions on two 32-bit words. The result is written to ACCU1. ACCU3 and ACCU4 are then transferred to ACCU2 and ACCU3. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion...
  • Page 66 Integer Math (32 Bits) Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Divide 2 integer by another (32 bits) 0.36 0.24 0.18 (ACCU1)=(ACCU2):(ACCU1) Divide 2 integer by another (32 bits) and 0.36 0.24 0.18...
  • Page 67: Floating-point Math (32 Bits)

    Floating-Point Math (32 Bits) Floating-Point Math (32 Bits) The result of the math instruction is in ACCU1. ACCU3 and ACCU4 are then transferred to ACCU2 and ACCU3. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416...
  • Page 68 Floating-Point Math (32 Bits) Floating-Point Math (32 Bits), continued Execution Time in ms Length Instruc- Instruc- Address Address Description Description tion tion CPU 412 CPU 414 CPU 416 CPU 417 Words NEGR Negate the real number in 0.06 0.04 0.03 ACCU1 Form the absolute value of the real 0.06...
  • Page 69: Square Root And Square Instructions (32 Bits)

    Square Root and Square Instructions (32 Bits) Square Root and Square Instructions (32 Bits) The result of the instruction is in ACCU1. The SQRT instruction can be interrupted. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414...
  • Page 70: Logarithmic Function (32 Bits)

    Logarithmic Function (32 Bits) Logarithmic Function (32 Bits) The result of the logarithmic function is in ACCU1. The instructions can be interrupted. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Form the natural logarithm of a...
  • Page 71: Trigonometrical Functions (32 Bits)

    Trigonometrical Functions (32 Bits) Trigonometrical Functions (32 Bits) The result of the instruction is in ACCU1. The instructions can be interrupted. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Calculate the sine of a real...
  • Page 72: Adding Constants

    Adding Constants Adding Constants Adding integer constants and storing the result in ACCU1. The status word is not affected. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Add an 8-bit integer constant 0.06...
  • Page 73: Adding Using Address Registers

    Adding Using Address Registers Adding Using Address Registers Adding a 16-bit integer to the contents of the address register. The value is either specified as an address in the instruction or is in ACCU1-L. The status word is not affected. Execution Time in ms Length Length...
  • Page 74: Comparison Instructions (16-bit Integers)

    Comparison Instructions (16-Bit Integers) Comparison Instructions (16-Bit Integers) Comparing the 16-bit integers in ACCU1-L and ACCU2-L. RLO = 1 if the condition is satisfied. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words...
  • Page 75: Comparison Instructions (32-bit Integers)

    Comparison Instructions (32-Bit Integers) Comparison Instructions (32-Bit Integers) Comparing the 32-bit integers in ACCU1 and ACCU2. RLO = 1 if the condition is satisfied. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words...
  • Page 76: Comparison Instructions (32-bit Real Numbers)

    Comparison Instructions (32-Bit Real Numbers) Comparison Instructions (32-Bit Real Numbers) Comparing the 32-bit real numbers in ACCU1 and ACCU2. RLO = 1 if the condition is satisfied. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416...
  • Page 77: Shift Instructions

    Shift Instructions Shift Instructions Shifting the contents of ACCU1 and ACCU1-L to the left or right by the specified number of places. If no address identifier is specified, the contents of ACCU2-LL are used as the number of places. The last bit shifted is loaded into condition code bit CC 1. Execution Time in ms Length Length...
  • Page 78 Shift Instructions Shift Instructions, continued Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Shift the contents of ACCU1 to the right. Positions Shift the contents of ACCU1 to the right. Positions 0.06 0.06 0.04...
  • Page 79: Rotate Instructions

    Rotate Instructions Rotate Instructions Rotate the contents of ACCU1 to the left or right by the specified number of places. If no address identifier is specified, the contents of ACCU2-LL are used as the number of places. The last bit shifted is loaded into condition code bit CC1. Execution Time in ms Length Length...
  • Page 80 Rotate Instructions Rotate Instructions, continued Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words RLDA Rotate the contents of ACCU1 one 0.06 0.04 0.03 bit position to the left through condition code bit CC 1 RRDA Rotate the contents of ACCU1 one...
  • Page 81: Accumulator Transfer Instructions, Incrementing And Decrementing

    Accumulator Transfer Instructions, Incrementing and Decrementing Accumulator Transfer Instructions, Incrementing and Decrementing The status word is not affected. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Reverse the order of the bytes in ACCU1-L.
  • Page 82: Accumulator Transfer Instructions, Incrementing And Decrementing, Continued

    Accumulator Transfer Instructions, Incrementing and Decrementing, continued Accumulator Transfer Instructions, Incrementing and Decrementing, continued Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Increment ACCU1-LL 0.06 0.04 0.03 Decrement ACCU1-LL 0.06...
  • Page 83: Program Display And Null Operation Instructions

    Program Display and Null Operation Instructions Program Display and Null Operation Instructions The status word is not affected. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Program display instruction: 0.06 0.04...
  • Page 84: Data Type Conversion Instructions

    Data Type Conversion Instructions Data Type Conversion Instructions The results of the conversion are in ACCU1. Execution Time in ms Length Length Instruc- Instruc- Addr. ID Addr. ID Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Convert contents of ACCU1-L 0.06 0.04...
  • Page 85 Data Type Conversion Instructions Data Type Conversion Instructions, continued Execution Time in ms Length Length Instruc- Instruc- Addr. Addr. Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words Convert contents of ACCU1-L from 0.06 0.04 0.03 integer (16 bits) to BCD from 0 to +/- 999 (Int To BCD) Convert contents of ACCU1 from 0.12...
  • Page 86 Data Type Conversion Instructions Data Type Conversion Instructions, continued The real number to be converted is in ACCU1. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words RND+ Convert a real number into a 0.24...
  • Page 87: Forming The Ones And Twos Complements

    Forming the Ones and Twos Complements Forming the Ones and Twos Complements Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words INVI Form the ones complement of 0.06 0.04 0.03...
  • Page 88: Block Call Instructions

    Block Call Instructions Block Call Instructions The runtimes of the System Functions are specified in the chapter entitled “System Functions” as of page 106. The information on the status word only relates to the block call itself and not to the commands called in this block. Execution Time in ms Length Length...
  • Page 89 Block Call Instructions Block Call Instructions, continued Execution Time in ms Length Length Address Address Description Description struc- struc- CPU 412 CPU 414 CPU 416 CPU 417 tion Words FB q Unconditional call of blocks, 1.32 0.88 0.72 FC q without parameter transfer 1.32 0.88...
  • Page 90 Block Call Instructions Block Call Instructions, continued Instruc- Instruc- Length Length Execution Time in ms Execution Time in ms tion tion tion Address Address Direct Addressing Description Description Words Words CPU 412 CPU 414 CPU 416 CPU 417 Open: 1)2); 1)2) 1)2) 1)2);...
  • Page 91: Block End Instructions

    Block End Instructions Block End Instructions Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words End block 1.62 End block unconditionally 1.62 Status word for: BE, BEU Instruction evaluates: –...
  • Page 92: Exchanging Shared Data Block And Instance Data Block

    Exchanging Shared Data Block and Instance Data Block Exchanging Shared Data Block and Instance Data Block Exchanging the two current data blocks. The current shared data block becomes the current instance data block, and vice versa. The sta- tus word is not affected. Execution Time in ms Length Length...
  • Page 93: Jump Instructions

    Jump Instructions Jump Instructions Jumping as a function of conditions. Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words LABEL Jump unconditionally 0.36 0.24 0.21 Status word for: Instruction evaluates: –...
  • Page 94 Jump Instructions Jump Instructions, continued Execution Time in ms Length Instruc- Instruc- Address Address Description Description tion tion CPU 412 CPU 414 CPU 416 CPU 417 Words LABEL Jump if RLO = “1”. 0.6/0.125 0.36/0.075 0.24/0.05 0.21/0.042 Save the RLO in the BR bit LABEL Jump if RLO = “0”.
  • Page 95 Jump Instructions Jump Instructions, continued Execution Time in ms Length Instruc- Instruc- Address Address Description Description tion tion CPU 412 CPU 414 CPU 416 CPU 417 Words LABEL Jump on stored overflow 0.6; 0.125 0.36; 0.075 0.24; 0.05 0.21; 0.042 (OV = “1”) Status word for: Instruction evaluates:...
  • Page 96 Jump Instructions Jump Instructions, continued Execution Time in ms Length Instruc- Instruc- Address Address Description Description tion tion CPU 412 CPU 414 CPU 416 CPU 417 Words LABEL Jump if “unordered math 0.6/0.125 0.36/0.075 0.24/0.05 0.21/0.042 instruction” (CC1=1 and CC0=1) LABEL Jump if result = 0 0.6;...
  • Page 97 Jump Instructions Execution Time in ms Length Instruc- Instruc- Address Address Description Description tion tion CPU 412 CPU 414 CPU 416 CPU 417 Words Jump if result v 0 (CC1=0 and LABEL 0.6/0.125 0.36/0.075 0.24/0.05 0.21/0.042 CC0=1) or (CC1=0 and CC0=0) Jump if result w 0 (CC1=1 and LABEL 0.6/0.125...
  • Page 98 Jump Instructions Jump Instructions, continued Execution Time in ms Length Instruc- Instruc- Address Address Description Description tion tion CPU 412 CPU 414 CPU 416 CPU 417 Words LABEL Jump distributor 0.42 0.28 0.24 This instruction is followed by a list of jump instructions.
  • Page 99: Instructions For The Master Control Relay (mcr)

    Instructions for the Master Control Relay (MCR) Instructions for the Master Control Relay (MCR) MCR=1³MCR is deactivated MCR=0³MCR is activated; “T” and “=” instructions write zeros to the corresponding address identifiers if RLO = “0”; “S” and ”R” instructions leave the memory contents unchanged. Execution Time in ms Length Length...
  • Page 100 Instructions for the Master Control Relay (MCR) Instructions for the Master Control Relay (MCR), continued Execution Time in ms Length Length Instruc- Instruc- Address Address Description Description tion CPU 412 CPU 414 CPU 416 CPU 417 Words MCRA Activate the MCR 0.06 0.04 0.03...
  • Page 101: Oganization Blocks (ob)

    Oganization Blocks (OB) Oganization Blocks (OB) A user program for the S7-400 is made up of blocks containing the statements, parameters and data for the relevant CPU. The number of blocks you can create or which are provided by the operating system is different for each of the S7-400 CPUs. You will find a detailed description of the OBs and their use in the STEP 7 Programming Manual.
  • Page 102 Oganization Blocks (OB) Oganization Blocks (OB), continued Organization Start Events Blocks 414-4H 417-4H (Hexadecimal Values) Time-delay interrupts OB 20 1121 OB 21 1122 OB 22 1123 OB 23 1124 Timed interrupts OB 30 1131 OB 31 1132 OB 32 1133 OB 33 1134 OB 34...
  • Page 103 Oganization Blocks (OB) Organization Blocks (OB), continued Organization Start Events Blocks 414-4H 417-4H (Hexadecimal Values) Hardware interrupts OB 40 1141, 1142, 1143, 1144, 1145 OB 41 1141, 1142, 1143, 1144, 1145 OB 42 1141, 1142, 1143, 1144, 1145 OB 43 1141, 1142, 1143, 1144, 1145 OB 44 1141, 1142, 1143, 1144, 1145...
  • Page 104 Oganization Blocks (OB) Oganization Blocks (OB), continued Organization Start Events Blocks 414-4H 417-4H (Hexadecimal Values) Multicomputing interrupts OB 60 1161, 1162 Synchronous cycle interrupt: OB 61 1164 OB 62 1165 OB 63 1166 OB 64 1167 Redundancy error interrupts: OB 70 73A2, 73A3, 72A3 OB 72 7301, 7302, 7303, 7320, 7321, 7322, 7323, 7331, 7333, 7334,...
  • Page 105 Oganization Blocks (OB) Organization Start Events Blocks 414-4H 417-4H (Hexadecimal Values) OB 83 3267, 3367, 3861, 3863, 3864, 3865, 3961, 3968 OB 85 35A1, 35A2, 35A3, 38B3, 38B4, 39B1, 39B2, 39B3, 39B4 OB 86 38C1, 38C2, 39C1, 38C6, 38C7, 38C8 38C4 , 38C5 , 39C3...
  • Page 106: Function Blocks (fb)

    Function Blocks (FB) Function Blocks (FB) The following tables list the quantities, numbers and maximum sizes of the function blocks you can create for the various S7-400 CPUs. Function Blocks CPU 412-1 CPU 412-2 CPU 414 CPU 416 CPU 417...
  • Page 107: Functions (fc) And Data Blocks

    Functions (FC) and Data Blocks The following tables list the quantities, numbers and maximum sizes of the functions and data blocks you can create for the various S7-400 CPUs. Functions CPU 412-1 CPU 412-2 CPU 414 CPU 416 CPU 417...
  • Page 108: System Functions

    System Functions System Functions The following tables show the system functions which are provided by the operating system of the S7-400 CPUs and the execution times for the various CPUs. (X: function available, execution times not yet available before printing). Execution Time in ms 414-4H 414-4H...
  • Page 109 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) EN_MSG Enable block-related, symbol-related, and group status messages. First call, REQ = 1 Last call DIS_MSG Disable block-related, symbol-related, and group status messages. First call, REQ = 1 Last call S7-400 Instruction List A5E00267845-01...
  • Page 110 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) DPSYC_FR Synchronize groups of DP Slaves First call, internal DP interface, REQ = 1 Intermediate call, internal DP interface, 40+ n* 4 23+ n* 3 16+ n* 2 13+ n* 2 BUSY = 1...
  • Page 111 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) D_ACT_DP Deactivate and activate DP slaves via integrated DP interface, MODE = 0 D_ACT_DP Deactivate and activate DP slaves via integrated DP interface, MODE = 1 First call Intermediate call Last call...
  • Page 112 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) D_ACT_DP Deactivate and activate DP slaves via external DP interface, MODE = 2 First call Intermediate call Last call DP_NRMDG Read slave diagnostic data First call Intermediate call Last call (28 bytes)
  • Page 113 System Functions Execution Time in ms CPU 412 CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) DPRD_DAT Read consistent user data (n bytes) via integrated DP interface 3 bytes via integrated DP interface 32 bytes via external DP interface 3 bytes via external DP interface 32 bytes Write consistent user data (n bytes) DPWR_DAT...
  • Page 114 System Functions Execution Time in ms CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) ALARM_SC Acknowledgment status of the last ALARM_SQ entering state message. BLKMOV Copy variable 50 + 31 + 21 + 17 + xx + xx + 0.05 0.03...
  • Page 115 System Functions Execution Time in ms CPU 412 CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) UPDAT_PI Update process image input table (run- time entry for 1 DI 32 in the central rack) AI 8* 13Bit UPDAT_PO Update process image output table (run- time entry for 1 DO 32 in the central rack)
  • Page 116 System Functions Execution Time in ms CPU 412 CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) DIS_IRT Discard new events Block all events (MODE = 0) Block all events of a priority class xx-xx xx-xx (MODE = 1) Block one event (MODE = 2) xx-xx xx - xx...
  • Page 117 System Functions Execution Time in ms CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) EN_AIRT Stop delaying interrupt events when canceling the last delay if other delays are present RE_TRIGR Retrigger watchdog monitoring REPL_VAL Transfer substitute value to ACCU1 Force CPU into STOP mode cannot be measured WAIT...
  • Page 118 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) “Module identification” partial list RDSYSST Display one data record (0111) RDSYSST ”Module Identification” partial list Display all data records (0012) Display one data record (0112) xx - xx xx - xx Display header information (0F12)
  • Page 119 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) RDSYSST “System Areas” partial list Display all data records (0014) Display header information (0F14) RDSYSST “Block Types” partial list Display all data records (0015) RDSYSST “Status of Module LEDs”...
  • Page 120 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) RDSYSST “TPA /CPU assignment” partial list Assignment between all process image partitions and OBs (0025) Assignment between a process image partition and the corresponding OB (0125) RDSYSST Assignment between an OB and corresponding process image partitions...
  • Page 121 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) RDSYSST “Modules LEDs” partial list xx - xx xx - xx Status of an LED (0174) RDSYSST “Switched DP slaves in the H system” xx - xx partial list Communication status between the...
  • Page 122 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) RDSYSST “DP master system information” partial list xx - xx xx - xx All known DP master systems of the CPU (0090) A DP master system (0190) xx - xx xx - xx Header information (0F90)
  • Page 123 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) Distributed a module with logical basic address (0C91) RDSYSST “Module status information” partial list of a module (distributed) with logical basic address (4C91) First call “Module status information”...
  • Page 124 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) RDSYSST Central 303 + 178+ 118 + 88 + xx + xx + n* 23 n* 16 n* 10 n * 8 n * yy n * yy all modules in the specified rack (n=number DR) (0D91)
  • Page 125 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) RDSYSST Display activation status of DP master system 1 (via integrated DP interface) (0192) RDSYSST central Display the actual status of rack 0 (0292) distributed Display the actual status of DP system 1 (0292)
  • Page 126 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) RDSYSST Central Display the diagnostic status of the expansion devices (0692) RDSYSST Distributed Display the diagnostic status of the DP system 1 stations (via integrated DP interface) (0692) RDSYSST Diagnostic status of the stations of a DP...
  • Page 127 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) RDSYSST “Diagnostic buffer” partial list 135 - 86 - 188 60 - 125 45 - 111 xx - xx xx - xx Display all deliverable event information in the current operating mode (max.
  • Page 128 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) RDSYSST “Diagnostic data DR 1” partial list Display via physical address (00B2) Display a 16–byte long DR 1 RDSYSST “Diagnostic data DR 1” partial list Display via logical basic address (00B3) Display a 16–byte long DR 1 central...
  • Page 129 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) RDSYSST ”Diagnostic Data DP Slave” partial list Display via configured diagnostic address (00B4) First call Intermediate call, REQ = 0 (00B4) Last call (6 - 240 bytes) (00B4) WR_USMSG Write user entry in diagnostic buffer write with message...
  • Page 130 System Functions Execution Time in ms CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) WR_DPARM Write predefined dynamic parameters AI 8*13 bits local distributed First call AI 8*12 bits (2 - 240 bytes) Intermediate/last call PARM_MOD Assign module parameters local Module/DS number/DS lengths in bytes...
  • Page 131 System Functions Execution Time in ms CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) WR_REC Write parameter data record 279 + 170 + 120 + 107 + xx + xx + local (n = number of bytes) n * 3 n * 2.5 n * 2.3...
  • Page 132 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) RD_REC Read data record 278 + 169 + 119 + 106 + xx + xx + local (n = number of bytes) n * 3.2 n * 2.7 n * 2.4 n * 2.3...
  • Page 133 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) CONTROL Check status of the connection belonging to a local communication-SFB-instance TIME_TCK Display millisecond timer X_SEND Transmit data to external partner First call, establish a connection (1 - 76 bytes) REQ = 1 First call, connection present (1-76 bytes)
  • Page 134 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) X_GET Read data from external partner First call, establish a connection (1-76 bytes) REQ = 1 First call, connection present (1-76 bytes) Intermediate call (1-76 bytes) Last call BUSY = 0 X_PUT...
  • Page 135 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) X_ABORT Abort connection to external partner First call, REQ = 1 Intermediate call Last call, BUSY = 0 I_GET Read data from internal partner First call, establish a connection (1-76 bytes) REQ = 1 First call, connection present (1-76 bytes)
  • Page 136 System Functions Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) I_ABORT Abort connection to internal partner First call, REQ = 1 Intermediate call Last call, without / with connection 62 / 217 48 / 253 37 / 217 BUSY = 0 Set bit array in I/O area...
  • Page 137 System Functions Execution Time in ms CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) SET_CLKS Set time-of-day and clock status MODE = 1 MODE = 2 MODE = 3 DP_TOPOL Detemine bus topology in a DP master system first call, REQ = 1 Intermediate call Last call BUSY = 0...
  • Page 138 System Functions Execution Time in ms CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) READ_SI Read dynamically assigned system 132 - 80 - 988 53 - 45 - xx - xx xx - xx resources MODE = 0 1185 1291 1168...
  • Page 139 System Functions Execution Time in ms CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) DEL_SI Enable dynamically assigned system 198 - 111 - 75 - 65 - xx - xx xx - xx resources MODE = 1 1016 1035 MODE = 2...
  • Page 140 System Functions Execution Time in ms CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) ALARM_D Not acknowledgeable block-related messages create first call, SIG = 0 -> 1 Call (without message) SYNC_PI Update the process image partition of the inputs in a synchronous cycle SYNC_PO Update the process image partition of the...
  • Page 141: System Function Blocks

    System Function Blocks System Function Blocks The following table lists the system function blocks provided with the operating system of the S7-400 CPUs as well as the execution times of the individual CPUs (X: function exists, execution times were not available when manual was printed). Execution Time in ms CPUs CPUs...
  • Page 142 System Function Blocks Execution Time in ms CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) URCV Receive data without coordination (one receive parameter supplied) JOB activated JOB checked JOB finished 280 - 165 - 108 - 92 - 106 xx - xx xx - xx...
  • Page 143 System Function Blocks Execution Time in ms CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) Read data from remote CPU (one area specified) JOB activated JOB checked JOB finished (NDR = 1; 1 - 450 bytes) 282 - 163 - 108 -...
  • Page 144 System Function Blocks Execution Time in ms CPUs CPUs 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) START Start remote device JOB activated, REQ = 1 JOB checked JOB finished, DONE = 1 STOP Stop remote device JOB activated, REQ = 1 JOB checked JOB finished, DONE = 1 RESUME...
  • Page 145 System Function Blocks Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) USTATUS Receive status of remote device without coordination JOB activated, NDR = 1 JOB checked JOB finished NOTIFY_8P Generate block–related message without 543 - 309 - 207 - 178 -...
  • Page 146 System Function Blocks Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) ALARM_8 Generate block-related message without accompanying values for 8 signals JOB activated, SIG = 0–> 1 (1 - 420 bytes) JOB checked JOB finished, DONE = 1 ALARM_8P Generate block-related message with 549 -...
  • Page 147 System Function Blocks Execution Time in ms 414-4H 414-4H SFC Name Function 417-4H 417-4H (solo) (redun- dant) AR_SEND Send archive data JOB activated, REQ = 1 (1 - 3000 bytes) JOB checked JOB finished, DONE = 1 RDREC Read data record from a DP slave via integrated DP interface, First call (2-16 bytes) Intermediate call...
  • Page 148 System Function Blocks Execution Time in ms 414-4H 414-4H SFB Name Function 417-4H 417-4H (solo) (redun- dant) WRREC Write data record in a DP slalve via integrated DP interface, First call (1-10 bytes) Intermediate call Last call WRREC Write data record in a DP slave via external DP interface, First call (2-14 bytes) Intermediate call...
  • Page 149 System Function Blocks Execution Time in ms 414-4H 414-4H SFB Name SFB Name Function Function 417-4H 417-4H (solo) (redun- dant) RALRM Receive interrupt from a DP slave Runtime measurement at external DP interface, MODE = 1, OB 40, OB 83, OB 86 OB 55 to OB 57, OB 82 OB 70 RALRM...
  • Page 150: Sublist Of The System Status List (ssl)

    Sublist of the System Status List (SSL) Sublist of the System Status List (SSL) SSL-ID Information Functions Module Identification 0111 One ident. data record only CPU Characteristics 0012 CPU features, all features 0112 Features of a group 0F12 Only SSL partial list header information User Memory Area 0F12 Only partial list header information...
  • Page 151 Sublist of the System Status List (SSL) Sublist of the System Status List (SSL), continued SSL-ID Information Functions System Areas 0014 System areas, all system areas 0F14 Only partial list header information Block Types 0015 Block types, data records for all block types Status Module LEDs 0019 Status of all module LEDs...
  • Page 152 Sublist of the System Status List (SSL) Sublist of the System Status List (SSL), continued SSL-ID Information Functions Assignment between process image partitions and OBs 0025 Assignment betweeen all process image partitions and OBs within the CPU 0125 Assignment between a process image partition and the corresponding OB 0225 Assignment between an OB and the corresponding process image partitions 0F25...
  • Page 153 Sublist of the System Status List (SSL) Sublist of the System Status List (SSL), continued SSL-ID Information Functions DP Master System Information 0090 Information about all the DP master systems known to the CPU 0190 Information about a DP master system 0F90 Only SSL partial list header information Module Status Information...
  • Page 154 Sublist of the System Status List (SSL) Sublist of the System Status List (SSL), continued SSL-ID Information Functions Rack/Station Status Information 0092 Expected status of the central racks/stations of a DP master system 4092 Expected status of the stations of a DP master system which is connected via an external DP interface module 0192 Activation status of the stations of a DP master system which is connected via an external DP interface module 0292...
  • Page 155 Sublist of the System Status List (SSL) Sublist of the System Status List (SSL), continued SSL-ID Information Functions Diagnostic Buffer (A maximum of 21 data records are supplied) 00A0 All current diagnostic entries available in current operating mode 01A0 Last x entries. X is listed in index 0FA0 Only partial list header information Module Diagnostic Data...
  • Page 156: Alphabetical Index Of Instructions

    Alphabetical Index of Instructions Alphabetical Index of Instructions Instruction Page Instruction Page <=D )MCR <=I <=R +AR1 <D +AR2 <I <R <>D <>I –D >=D –I >=I –R >=R >D >I >R ACOS ASIN ATAN S7-400 Instruction List A5E00267845-01...
  • Page 157 Alphabetical Index of Instructions Instruction Page Instruction Page JBIN CALL 47 48 49 50 51 52 53 59 60 LAR1 LAR2 44 46 INVD INVI S7-400 Instruction List A5E00267845-01...
  • Page 158 Alphabetical Index of Instructions Instruction Page Instruction Page LEAVE RND+ LOOP RND– MCR( MCRA RRDA MCRD SAVE NEGD NEGI NEGR 26 30 32 35 36 37 SQRT 26 32 35 36 37 39 45 PUSH 39 44 45 54 55 56 59 RLDA S7-400 Instruction List A5E00267845-01...
  • Page 159 Alphabetical Index of Instructions Instruction Page Instruction Page TAR1 27 32 35 36 37 TAR2 TRUNC 27 32 35 36 37 25 31 35 36 37 25 31 35 36 37 S7-400 Instruction List A5E00267845-01...
  • Page 160 Alphabetical Index of Instructions S7-400 Instruction List A5E00267845-01...

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