2
eUSCI_B Operation – I
C Mode
Serial Data (SDA)
Serial Clock (SCL)
NOTE:
SDA and SCL levels
The SDA and SCL pins must not be pulled up above the device V
41.3.1 eUSCI_B Initialization and Reset
The eUSCI_B is reset by a PUC or by setting the UCSWRST bit. After a PUC, the UCSWRST bit is
automatically set, keeping the eUSCI_B in a reset condition. To select I
must be set to 11b. After module initialization, it is ready for transmit or receive operation. Clear
UCSWRST to release the eUSCI_B for operation.
To avoid unpredictable behavior, configure or reconfigure the eUSCI_B module only when UCSWRST is
set. Setting UCSWRST in I
2
•
I
C communication stops.
•
SDA and SCL are high impedance.
•
UCBxSTAT, bits 15-8 and 6-4 are cleared.
•
Registers UCBxIE and UCBxIFG are cleared.
•
All other bits and registers remain unchanged.
NOTE:
Initializing or reconfiguring the eUSCI_B module
The recommended eUSCI_B initialization/reconfiguration process is:
1.
Set UCSWRST (BIS.B
2.
Initialize all eUSCI_B registers with UCSWRST = 1 (including UCxCTL1).
3.
Configure ports.
4.
Clear UCSWRST through software (BIC.B
5.
Enable interrupts (optional).
2
41.3.2 I
C Serial Data
One clock pulse is generated by the master device for each data bit transferred. The I
with byte data. Data is transferred MSB first as shown in
The first byte after a START condition consists of a 7-bit slave address and the R/W bit. When R/W = 0,
the master transmits data to a slave. When R/W = 1, the master receives data from a slave. The ACK bit
is sent from the receiver after each byte on the ninth SCL clock.
1082
Enhanced Universal Serial Communication Interface (eUSCI) – I
V
CC
MSP430
2
Figure 41-2. I
C Bus Connection Diagram
2
C mode has the following effects:
#UCSWRST,&UCxCTL1).
#UCSWRST,&UCxCTL1).
2
Copyright © 2008–2018, Texas Instruments Incorporated
Device A
Device B
level.
CC
2
C operation, the UCMODEx bits
Figure
41-3.
SLAU208Q – June 2008 – Revised March 2018
C Mode
www.ti.com
Device C
2
C mode operates
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