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35.2 LCD_C Operation
The LCD controller is configured with user software. The setup and operation of the LCD controller is
discussed in the following sections.
35.2.1 LCD Memory
The LCD memory organization differs slightly depending on the mode.
Each memory bit corresponds to one LCD segment or is not used, depending on the mode. To turn on an
LCD segment, its corresponding memory bit is set.
The memory can also be accessed word-wise using the even addresses starting at LCDM1, LCDM3, ...
Setting the bit LCDCLRM clears all LCD memory registers at the next frame boundary. It is reset
automatically after the registers are cleared.
35.2.1.1 Static and 2-Mux to 4-Mux Mode
For static and 2-mux to 4-mux modes, one byte of the LCD memory contains the information for two
segment lines.
Figure 35-2
Associated
Common Pins
Figure 35-2. LCD Memory for Static and 2-Mux to 4-Mux Mode - Example for 160 Segments
SLAU208Q – June 2008 – Revised March 2018
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shows an example LCD memory map for these modes with 160 segments.
3
2
1
0
Register
7
--
--
--
--
LCDM20
--
--
--
--
LCDM19
--
--
--
--
LCDM18
--
--
--
--
LCDM17
--
--
--
--
LCDM16
--
--
--
--
LCDM15
--
--
--
--
LCDM14
--
--
--
--
LCDM13
--
--
--
--
LCDM12
--
--
--
--
LCDM11
--
--
--
--
LCDM10
--
--
--
--
LCDM9
--
--
--
--
LCDM8
--
--
--
--
LCDM7
--
--
--
--
LCDM6
--
--
--
--
LCDM5
--
--
--
--
LCDM4
--
--
--
--
LCDM3
--
--
--
--
LCDM2
--
--
--
--
LCDM1
Sn+1
Copyright © 2008–2018, Texas Instruments Incorporated
3
2
1
0
Associated
Segment Pins
0
n
--
--
--
--
39, 38
38
--
--
--
--
37, 36
36
--
--
--
--
35, 34
34
--
--
--
--
32
33, 32
--
--
--
--
31, 30
30
--
--
--
--
29, 28
28
--
--
--
--
27, 26
26
--
--
--
--
25, 24
24
--
--
--
--
23, 22
22
--
--
--
--
21, 20
20
--
--
--
--
19, 18
18
--
--
--
--
17, 16
16
--
--
--
--
15, 14
14
--
--
--
--
13, 12
12
--
--
--
--
1, 10
10
--
--
--
--
9, 8
8
--
--
--
--
7, 6
6
--
--
--
--
5, 4
4
--
--
--
--
3, 2
2
--
--
--
--
1, 0
0
Sn
LCD_C Operation
905
LCD_C Controller
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