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Texas Instruments MSMC User Manual

Texas Instruments MSMC User Manual

Keystone architecture multicore shared memory controller
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KeyStone Architecture
Multicore Shared Memory Controller (MSMC)
User Guide
Literature Number: SPRUGW7
November 2010

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Summary of Contents for Texas Instruments MSMC

  • Page 1 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide Literature Number: SPRUGW7 November 2010...

  • Page 2: Release History

    Release History Release Date Chapter/Topic Description/Comments November 2010 Initial Release ø-ii KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    2.1.2.2 System MSMC SRAM Access Slave Interface (SMS) ....... . .
  • Page 4 3.3.3 MSMC SRAM Correctable EDC Extended Error Register (SMCERRXR) ........3-6 3.3.4 MSMC SRAM Non-correctable EDC Error Address Register (SMNCERRAR)......3-6 3.3.5 MSMC SRAM Non-correctable EDC Extended Error Register (SMNCERRXR) .

  • Page 5: List Of Tables

    MSMC SRAM Correctable EDC Error Address Register (SMCERRAR) Field Descriptions ......
  • Page 6 MSMC SRAM Non-correctable EDC Extended Error Register (SMNCERRXR)........

  • Page 7: Ø-Vii

    The Multicore Shared Memory Controller (MSMC) manages traffic among multiple C66x CorePacs, DMA, other mastering peripherals, and the EMIF in a multicore device. MSMC also provides a shared on-chip SRAM that is accessible by all the C66x CorePacs and the mastering peripherals on the device.

  • Page 8: Related Documentation From Texas Instruments

    SPRUGZ3 Trademarks TMS320C66x and C66x are trademarks of Texas Instruments Incorporated. All other brand names and trademarks mentioned in this document are the property of Texas Instruments Incorporated or their respective owners, as applicable. ø-viii KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010...

  • Page 9: Introduction

    Chapter 1 Introduction 1.1 "Overview" on page 1-2 1.2 "Terminology" on page 1-2 1.3 "Features" on page 1-2 SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide Submit Documentation Feedback...

  • Page 10: Overview

    1.3 Features The MSMC module has the following features: • Level 2 or Level 3 shared MSMC SRAM that is accessible by all the C66x CorePacs and the mastering peripherals • Memory protection for accesses to MSMC SRAM and DDR3 memory from system masters •...

  • Page 11: Msmc Architecture

    Control" on page 2-12 "Error Detection and Correction Support" on page 2-14 "MSMC Interrupt Control" on page 2-18 "Reset Considerations" on page 2-19 "Memory Map" on page 2-20 SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide Submit Documentation Feedback...

  • Page 12: Functional Overview

    EMIF – 64-bit DDR3 The MSMC has slave interfaces to connect to the C66x CorePacs (one slave interface per CorePac), two slave interfaces to connect to the system interconnect (SCR), one master port to connect to the EMIF, and one master port to connect to the system interconnect (SCR).

  • Page 13: System Emif Access Slave Interface (Ses)

    The SMS interface handles accesses to MSMC SRAM that originate from a system master that is not a C66x CorePac. Accesses from masters in the system to MSMC configuration registers are also expected to be presented at this interface. Any accesses from the SMS interface that do not address the MSMC SRAM or configuration registers result in an addressing error returned to the requesting master.

  • Page 14: Memory Protection And Address Extension (Mpax)

    ‘‘MPAX Segment Registers’’ on page 3-11. All the MPAX registers in the MSMC are readable by any of the connected C66x CorePacs and also by system masters through the SMS port. Write-access control to these registers can be coordinated with the aid of semaphores external to the MSMC as well as through the locking mechanism for MSMC configuration registers.

  • Page 15: Mpax Segment Register Set Layout

    SMS_MPAXH_F_3 SMS_MPAXL_F_3 MPAX register set for PrivID “0xF” SES_MPAXH_F_3 SES_MPAXL_F_3 SMS_MPAXH_F_4 SMS_MPAXL_F_4 SES_MPAXH_F_4 SES_MPAXL_F_4 SMS_MPAXH_F_5 SMS_MPAXL_F_5 SES_MPAXH_F_5 SES_MPAXL_F_5 SMS_MPAXH_F_6 SMS_MPAXL_F_6 SES_MPAXH_F_6 SES_MPAXL_F_6 SMS_MPAXH_F_7 SMS_MPAXL_F_7 SES_MPAXH_F_7 SES_MPAXL_F_7 SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide Submit Documentation Feedback...

  • Page 16: Mpax Segment Register Reset Values

    At reset, the MPAX segment 0 register-pair has initial values that set up unrestricted access to the full MSMC SRAM address space and 2 GB of the EMIF address space. All other segments come up with the permission bits and size set to 0 (that is, no access map to those segments).
  • Page 17 For 4 GB segments, no BADDR bits are consulted and all addresses match. • If an address does not match any of the programmed MPAXH registers and is not a MSMC configuration register address, the access permissions for the access are considered to be 0; this results in a protection fault. •...

  • Page 18: Memory Protection Fault Reporting

    2.2 Memory Protection and Address Extension (MPAX) Chapter 2—MSMC Architecture www.ti.com 2.2.3.1 Memory Protection Fault Reporting The MSMC memory protection fault reporting registers are listed in Table 2-2 described in ‘‘Memory Protection Fault Reporting Registers’’ on page 3-14. Table 2-2...

  • Page 19: Ses Aliased Access To Msmc Ram

    Using address remapping in the MPAX unit at the SES port, it is possible to map some or all of the MSMC SRAM into external memory space and access it through the SES port. This provides the same ability to alias MSMC memory to external address space for system masters as is available to the C66x CorePacs through the CorePac MPAX unit.

  • Page 20: Msmc Memory

    5 of the address is used to select the subbank in the selected bank. TCI6616 device has MSMC SRAM size of 2 MB, it is made up of four 512 KB banks. TCI6608 device has MSMC SRAM size of 4 MB, it is made up of four 1 MB banks.

  • Page 21: Msmc Bandwidth Management

    SBNDC0-SBNDC3/SBNDC7 for the C66x CorePac slaves, and SBNDM for the SMS port and SBNDE for the SES port. The registers are programmed with a desired starvation bound in MSMC cycles for the requestor’s accesses. MSMC bandwidth management registers are described in ‘‘Bandwidth Management...

  • Page 22: Msmc Register Access Control

    MSMC configuration. While a semaphore-based mutex access control is still expected to be used by software on the cores (and any masters that may program the registers), MSMC features a simple lock mechanism to protect against runaway pointer writes.
  • Page 23 This provides a simple write-protection mechanism that protects Note— against unintentional modification only. It is recommended that the software uses a semaphore to ensure exclusive access when modifying the MSMC lock registers. SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide...

  • Page 24: Error Detection And Correction Support

    2.5 Error Detection and Correction Support The MSMC has error detection and correction hardware to protect the contents of the MSMC memory storage against corruption due to transient (soft) errors. The level of protection provided and the scheme used is the same as that of the C66x CorePacs (that is, one-bit error correction, two-bit error detection, with the parity codes calculated over a 256 bit datum).

  • Page 25: Error Correction Mode

    Figure 4-4. The assumption on the reliability of the data being stored and transferred to/from the MSMC is that any incoming data for MSMC storage is reliable and a parity code generated from it is valid. The EDC hardware consists of the registers listed in...

  • Page 26: Edc Error Reporting

    As parity is tracked at a granularity equal to the width of the banks (32 bytes), writes that are smaller than 32 bytes can invalidate the parity information for a line. MSMC contains a background error correction hardware called the Scrubbing Engine that periodically refreshes the parity bits for the memory.

  • Page 27: Scrubbing Error Logging And Statistics Collection

    2.5.5 Parity RAM Initialization at Reset The MSMC EDC hardware invalidates all the parity RAM entries at reset. During this initialization cycle, accesses are not stalled from the slaves or from the scrubbing engine, but are provided no error correction or detection: •...

  • Page 28: Msmc Interrupt Control

    Chapter 2—MSMC Architecture www.ti.com 2.6 MSMC Interrupt Control The MSMC features a set of interrupt status and enable registers that can control the generation of interrupts at the MSMC module boundary. The MSMC interrupt operation is controlled by the registers listed in...

  • Page 29: Reset Considerations

    2.7 Reset Considerations Chapter 2—MSMC Architecture www.ti.com 2.7 Reset Considerations The MSMC module resets on all device resets. Upon reset, the following sequence is followed: • All MSMC configuration registers are reset to their initial default state. • The parity RAM entries associated with the MSMC SRAM are invalidated as described in ‘‘Parity RAM Initialization at Reset’’...

  • Page 30: Memory Map

    MSMC Config 0x0BC00000 0x0BCFFFFF Table 2-10 MSMC Memory Map for TCI6608 Region Start Address End Address Region Size MSMC SRAM 0x0C000000 0x0C3FFFFF MSMC Config 0x0BC00000 0x0BCFFFFF 2-20 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010 Submit Documentation Feedback...

  • Page 31: Msmc Registers

    Chapter 3 MSMC Registers This chapter describes the memory-mapped registers associated with the MSMC. "MSMC Memory Mapped Registers" on page 3-2 "Peripheral Identification Register (PID)" on page 3-4 "EDC Registers" on page 3-5 "Bandwidth Management Control Registers" on page 3-9 "MPAX Segment...

  • Page 32: Msmc Memory Mapped Registers

    Chapter 3—MSMC Registers www.ti.com 3.1 MSMC Memory Mapped Registers Table 3-1 lists the MSMC memory-mapped registers. See the device-specific data manual for the memory address of these registers. All other register offset addresses not listed in Table 3-1 should be considered as reserved locations and the register contents should not be modified.
  • Page 33 — 0x9F8:0x9FC SES_MPAXL_F_7:SES_MPAXH_F_7 MPAX register pair 7 for SES for PrivID F 3.5.2 3.5.3 1. Registers SBNDC4 to SBNDC7 are applicable only to the TCI6608 device SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide Submit Documentation Feedback...

  • Page 34: Peripheral Identification Register (Pid)

    Legend: R = Read only; W = Write only; -n = value after reset; -x, value is indeterminate — see the device-specific data manual Table 3-2 Peripheral ID Register (PID) Field Descriptions Field Description 31-0 Peripheral identifier uniquely identifies the MSMC and the specific revision of the MSMC. KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010 Submit Documentation Feedback...

  • Page 35: Edc Registers

    Reads return 0 and writes have no effect. REFDEL 0-FFh Controls the number of MSMC clock cycles between each scrub burst. To prevent the bursts from the scrubbing engine from posing a significant performance impact, the value in the REFDEL register is pre-scaled by 1024.

  • Page 36: Msmc Sram Correctable Edc Extended Error Register (Smcerrxr)

    R, +0000 Legend: R = Read only; W = Write only; -n = value after reset; -x, value is indeterminate — see the device-specific data manual Table 3-5 MSMC SRAM Correctable EDC Extended Error Register (SMCERRXR) Field Descriptions Field Value...

  • Page 37: Msmc Sram Non-Correctable Edc Extended Error Register (Smncerrxr)

    R, +0000 Legend: R = Read only; W = Write only; -n = value after reset; -x, value is indeterminate — see the device-specific data manual Table 3-7 MSMC SRAM Non-correctable EDC Extended Error Register (SMNCERRXR) Field Descriptions Field Value...

  • Page 38: Msmc Scrubbing Non-Correctable Address Register (Smncea)

    RW, +0000 0000 0000 0000 Legend: R = Read only; W = Write only; -n = value after reset; -x, value is indeterminate — see the device-specific data manual Table 3-10 MSMC Scrubbing Error Corrected Counter Register (SMSECC) Field Descriptions Field Value...

  • Page 39: Bandwidth Management Control Registers

    Reads return 0 and writes have no effect. SCNTMM 0-FFh Reload value for the starvation counters for SMS requests at the RAM bank arbiters. End of Table 3-12 SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide Submit Documentation Feedback...

  • Page 40: Starvation Bound Register For Ses Port (Sbnde)

    Reads return 0 and writes have no effect. SCNTEM 0-FFh Reload value for the starvation counters for SES requests at the RAM bank arbiters. End of Table 3-13 3-10 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010 Submit Documentation Feedback...

  • Page 41: Mpax Segment Registers

    Indicates a supervisor write request. Supervisor execute access type. Normal operation. Indicates a supervisor execute request. User read access type. Normal operation. Indicates a user read request. SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide 3-11 Submit Documentation Feedback...

  • Page 42: Ses_Mpaxhn

    Reads return 0 and writes have no effect. Supervisor read access type. Normal operation. Indicates a supervisor read request. Supervisor write access type. Normal operation. Indicates a supervisor write request. 3-12 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010 Submit Documentation Feedback...
  • Page 43 User write access type. Normal operation. Indicates a user write request. User execute access type. Normal operation. Indicates a user execute request. End of Table 3-17 SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide 3-13 Submit Documentation Feedback...

  • Page 44: Memory Protection Fault Reporting Registers

    R, +0000 0000 0000 0000 0000 0000 0000 0000 Legend: R = Read only; W = Write only; -n = value after reset; -x, value is indeterminate — see the device-specific data manual Table 3-18 MSMC Memory Protection Fault Address Register (SMPFAR) Field Descriptions Field Value...

  • Page 45: Msmc Memory Protection Fault Control Register (Smpfcr)

    RW, +0 Legend: R = Read only; W = Write only; -n = value after reset; -x, value is indeterminate — see the device-specific data manual Table 3-21 MSMC Memory Protection Fault Control Register (SMPFCR) Field Descriptions Field Value Description...

  • Page 46: Msmc Configuration Write Lock Registers

    Reads return 0 and writes have no effect. Writing 0 has no effect. Writing this bit to 1 along with setting MGCID key = 0x2CD0 disengages the lock. End of Table 3-23 3-16 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010 Submit Documentation Feedback...

  • Page 47: Configuration Lock Status For Non-Mpax Registers (Cfglckstat)

    Writing WLCK[n] bit to 0 has no effect. Writing WLCK[n] bit to 1 along with setting MGCID key = 0x2CD1 engages the lock for PrivID n. End of Table 3-25 SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide 3-17 Submit Documentation Feedback...

  • Page 48: Configuration Unlock Control For Sms Mpax Registers (Sms_Mpax_Ulck)

    0-FFFFh Bit n indicates the lock's current status for PrivID n. 0 - Lock is disengaged. 1 - Lock is engaged. End of Table 3-27 3-18 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010 Submit Documentation Feedback...

  • Page 49: Configuration Lock Control For Ses Mpax Registers (Ses_Mpax_Lck)

    Writing WEN[n] bit to 0 has no effect. Writing WEN[n] bit to 1 along with setting MGCID key = 0x2CD1 disengages the lock for PrivID n. End of Table 3-29 SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide 3-19 Submit Documentation Feedback...

  • Page 50: Configuration Lock Status For Ses Mpax Registers (Ses_Mpax_Lckstat)

    0-FFFFh Bit n indicates the lock's current status for PrivID n. 0 - Lock is disengaged. 1 - Lock is engaged. End of Table 3-30 3-20 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010 Submit Documentation Feedback...

  • Page 51: Msmc Interrupt Control Registers

    No scrubbing error. Correctable scrubbing error interrupt is enabled and pending. NCSES No scrubbing error. Non-correctable scrubbing error interrupt is enabled and pending. End of Table 3-31 SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide 3-21 Submit Documentation Feedback...

  • Page 52: Interrupt Raw Status Register (Smirstat)

    Correctable scrubbing error. Write 1 to set the correctable scrubbing error interrupt status. NCSI No scrubbing error. Non-correctable scrubbing error. Write 1 to set the non-correctable scrubbing error interrupt status. End of Table 3-32 3-22 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010 Submit Documentation Feedback...

  • Page 53: Interrupt Raw Status Clear Register (Smirc)

    Correctable scrubbing error interrupt is disabled. Correctable scrubbing error interrupt is enabled. NCSIE Non-correctable scrubbing error interrupt is disabled. Non-correctable scrubbing error interrupt is enabled. End of Table 3-34 SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide 3-23 Submit Documentation Feedback...

  • Page 54: Interrupt Enable Clear Register (Smiec)

    Clear the non-correctable EDC error interrupt enable. CSEC No effect. Clear the correctable scrubbing error interrupt enable. NCSEC No effect. Clear the non-correctable scrubbing error interrupt enable. End of Table 3-35 3-24 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010 Submit Documentation Feedback...
  • Page 55 SRAM (Static RAM), ø-vii, 1-2, to 2-4, 2-6, to 2-10, 2-14 to 2-15, 2-19 to 2-20, to 3-3, EMIF, ø-vii, 1-2, to 2-4, 2-6, 2-9, 2-11, 3-10 SPRUGW7—November 2010 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide IX-1 Submit Documentation Feedback...

  • Page 56: Index

    Index status register, 2-18, 3-2, 3-21 3-23 IX-2 KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide SPRUGW7—November 2010 Submit Documentation Feedback...
  • Page 57 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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