Texas Instruments TPS65981 Manual

Texas Instruments TPS65981 Manual

Usb type-c and usb pd controller, power switch, and high speed multiplexer
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TPS65981 USB Type-C and USB PD Controller, Power Switch, and High Speed Multiplexer
1 Features
USB Power Delivery (PD) Controller
1
– Mode Configuration for Source (Host), Sink
(Device), or Source-Sink
– Bi-Phase Marked Encoding and Decoding
(BMC)
– Physical Layer (PHY) Protocol
– Policy Engine
– Configurable at Boot and Host-Controlled
USB Type-C Specification Compliant
– Detect USB Cable Plug Attach
– Cable Orientation and Role Detection
– Assign CC and VCONN Pins
– Advertise Default, 1.5 A or 3 A for Type-C
Power
Port-Power Switch
– 5-V, 3-A Switch to VBUS for Type-C Power
– 5-V to 20-V, 3-A Bidirectional Switch to or from
VBUS for USB PD Power
– 5-V, 600-mA Switches for VCONN
– Overcurrent Limiter, Overvoltage Protector
– Slew-Rate Control
– Hard Reset Support
Port Data Multiplexer
– USB 2.0 HS Data and Low Speed Endpoint
– Sideband-Use Data for Alternate Modes
(DisplayPort, for Example)
Power Management
– Gate Control and Current Sense for External
5-V to 20-V, 5-A Bidirectional Switch (Back-to-
Back NFETs)
– Power Supply from 3.3-V or VBUS Source
– 3.3-V LDO Output for Dead Battery Support
QFN Package for Reliable Manufacturing
– 0.5-mm Pitch
– 2-Layer PCB Compatibility
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Product
Buy
Folder
Tools &
Technical
Software
Documents
SLVSDC2B – FEBRUARY 2016 – REVISED AUGUST 2016
2 Applications
After-Market Automotive Infotainment
Industrial Equipment
Medical Equipment
Notebooks, Tablets, and Ultrabooks
Monitors and TVs
USB PD Hosts, Devices, and Dual-Role Ports
3 Description
The TPS65981 device is a stand-alone, USB Type-C,
and power-delivery (PD) controller providing cable-
plug and orientation detection at the USB Type-C
connector. Upon cable detection, the TPS65981
device communicates on the CC wire using the USB
PD protocol. When cable detection and USB PD
negotiation are complete, the TPS65981 device
enables the appropriate power path and configures
alternate mode settings for internal and (optional)
external multiplexers.
The mixed-signal front end on the CC pins provides
default (900 mA), 1.5-A, or 3-A current for Type-C
power sources, detects a plug event, determines the
USB Type-C cable orientation, and autonomously
negotiates USB PD contracts by adhering to the
specified
biphase-marked
physical-layer (PHY) protocol.
Device Information
PART NUMBER
TPS65981
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Diagram
5 to 20 V
External FET Sense and CTRL
5 to 20 V
5 V
3.3 V
Host
Host
Interface
USB2.0 and
Sideband-Use
Data
Alternate Mode Mux Ctrl
TPS65981
Support &
Community
TPS65981
coding
(BMC)
(1)
PACKAGE
BODY SIZE (NOM)
VQFN (56)
8.00 mm × 8.00 mm
5 A
V
3 A
BUS
3 A
Type-
C Cable
CC/V
Detection
and
CC1/2
2
CONN
USB PD Controller
USB_TP/TN
2
High
USB_BP/BN
2
Speed
SBU1/2
2
SBU1/2
Mux
GND
SuperSpeed Mux
Copyright © 2016, Texas Instruments Incorporated
and
USB
Type-C
Connector

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Summary of Contents for Texas Instruments TPS65981

  • Page 1 Community Folder Software Documents TPS65981 SLVSDC2B – FEBRUARY 2016 – REVISED AUGUST 2016 TPS65981 USB Type-C and USB PD Controller, Power Switch, and High Speed Multiplexer 1 Features 2 Applications • USB Power Delivery (PD) Controller • After-Market Automotive Infotainment –...
  • Page 2: Table Of Contents

    NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (April 2016) to Revision B Page • Changed the device status from Product Preview to Production Data ................. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 3: Description (Continued)

    (device), or source-sink. The TPS65981 device is also an upstream-facing port (UFP), downstream-facing port (DFP), or dual-role port for data. The port-data multiplexer passes data to or from the top or bottom D+/D– signal pair at the port for USB 2.0 HS and has a USB 2.0 low-speed endpoint.
  • Page 4: Pin Configuration And Functions

    Analog I/O Hi-Z Port-side top USB D– connection to the port multiplexer. C_USB_TP Type-C Port Analog I/O Hi-Z Port-side top USB D+ connection to the port multiplexer. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 5 GND. Tie pin to GND when unused 5-V supply for C_CC pins. Bypass with capacitance CPP_CABLE PP_CABLE High Current Power to GND when not tied to PP_5V0. Tie pin to PP_5V0 when unused. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 6 Ground. Connect directly to ground plane in accordance with the GND (Thermal Pad) Ground Ground Hi-Z guidelines listed in the Layout Guidelines section to achieve the measured values in the Thermal Information table. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 7: Specifications

    (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 8: Recommended Operating Conditions

    °C/W Junction-to-case (bottom) thermal resistance °C/W θJC(bottom) (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 9: Power Supply Requirements And Characteristics

    Input voltage to power C_CC pins. This input is PP_CABLE 2.95 also available to power core circuitry Bidirection DC bus voltage. Output from the VBUS TPS65981 or input to the TPS65981 5-V supply input to power VBUS. This supply PP_5V0 4.75 does not power the TPS65981 VDDIO Optional supply for I/O cells 3.45...
  • Page 10: Power Supervisor Characteristics

    (4) Active is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, all core functionality active, and the digital core is clocked at 12 MHz. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 11: Cable Detection Characteristics

    Threshold voltage of the pull-down FET in series with RD during VTH_DB I_CC = 80 μA dead battery R_RPD Resistance between RPD_Gn and the gate of the pull-down FET MΩ Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 12: Usb-Pd Baseband Signal Requirements And Characteristics

    TTRANWIN. After waiting TTRANWIN without detecting NCOUNT transitions, the bus is declared idle. (5) Broadband noise ingression is because of coupling in the cable interconnect. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 13: Usb-Pd Tx Driver Voltage Adjustment Parameter

    Configured as sink; EN_HV = 1 IHVEXTSD Shutdown quiescent current from SENSEP pin EN_HV = 0 μA IPP5VACT Active quiescent current from PP_5V0 IPP5VSD Shutdown quiescent current from PP_5V0 μA Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 14 (1) The settings are selected automatically by application code for the current limit required in the application. (2) Specified for a 10-mΩ RSENSE resistor and 10-mΩ RSENSE application code setting. The values scale with a different RSENSE resistance and application code setting. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 15 When reverse blocking is disabled, the values given for accuracy are valid. (4) Limit the resistance from the HV_GATE1/2 pins to the external FET gate pins to < 1Ω to provide adequate response time to short circuit events. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 16: Port Data Multiplexer Switching Characteristics

    (1) All RON specified maximums are the maximum of either of the switches in a pair. All ROND specified maximums are the maximum difference between the two switches in a pair. ROND does not add to RON. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 17: Port Data Multiplexer Clamp Characteristics

    V = VCLMP_IND + 500 mV (1) The TCLMP_PRT time includes the time through the digital synchronizers. When the clock speed is reduced, the signal assertion time may be longer. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 18: Port Data Multiplexer Sbu Detection Requirements

    Total series resistance because of port data VDX_RSRC VDX_SRC = 0.65 V Ω multiplexer VDX_ILIM VDX_SRC current limit μA IDX_SNK Sink current VC_USB_TN/BN ≥ 250 mV μA Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 19: Analog-To-Digital Converter (Adc) Characteristics

    Low-level input voltage LDO_3V3 = 3.3 V SWDCL_THI SWDIOCLK HIGH period 0.05 μs SWDCL_TLO SWDIOCLK LOW period 0.05 μs SWDCL_HYS Input hysteresis voltage LDO_3V3 = 3.3 V Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 20 VDDIO = 1.8 V 0.09 C pulse width suppressed Pin Capacitance SDA AND SCL STANDARD MODE CHARACTERISTICS FSCL C clock frequency THIGH μs C clock high time Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 21: I 2 C Slave Requirements And Characteristics

    = 5 pF to 50 pF, TRSPI SPI_SSZ/CLK/MOSI rise time LDO_3V3 = 3.3 V 90% to 10%, C = 5 pF to 50 pF, TFSPI SPI_SSZ/CLK/MOSI fall time LDO_3V3 = 3.3 V Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 22: Buspowerz Configuration Requirements

    DP SINK SIDE (HPD RX) HPD_HDB_SEL = 0 μs T_HPD_HDB HPD high de-bounce time HPD_HDB_SEL = 1 T_HPD_LDB HPD low de-bounce time μs T_HPD_IRQ HPD IRQ limit time 1.35 1.65 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 23: Oscillator Requirements And Characteristics

    Temperature (qC) D001 D002 Figure 1. PP_5V0 Switch On-Resistance vs Temperature Figure 2. PP_HV Switch On-Resistance vs Temperature Temperature (qC) D003 Figure 3. PP_CABLE Switch On-Resistance vs Temperature Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 24: Parameter Measurement Information

    T_SAMPLEA T_CONVERTA T_INTA ADC Clock ADC Enable ADC Sample ADC Interrupt New Valid Output ADC Output Previous or Invalid Output Figure 5. ADC Enable and Conversion Timing Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 25 HD;STA 9 clock 1 / f 1 clock cycle VD;ACK SU;STA HD;STA SU;STO 70 % 30 % 9 clock 002aac938 Figure 7. I C Slave Interface Timing Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 26 Valid Data t hdmiso Figure 8. SPI Master Timing whigh wlow SWD_CLK dout dout SWD_DATA (Output) Valid Data hdin suin SWD_DATA (Input) Valid Data Figure 9. SWD Timing Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 27: Detailed Description

    1.8-V or 3.3-V rail. The TPS65981 is an I C slave to be...
  • Page 28: Functional Block Diagram

    RPD_G1 Digital Core Cable Power, C_CC2 SPI_MOSI/MISO/SSZ/CLK RPD_G2 USB-PD Phy SWD_DAT/CLK DEBUG_CTL1/2 C_USB_TP/TN AUX_P/N C_USB_BP/BN Port Data Multiplexer USB_RP_P/N C_SBU1/2 DEBUG1 Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 29: Feature Description

    USB-PD transmitter. Figure 12 illustrates the high-level block diagram of the baseband USB-PD receiver. 4b5b Data to PD_TX Encoder Encoder Figure 11. USB-PD Baseband Transmitter Block Diagram Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 30 USB-PD Specifications for more details. 9.3.1.4 USB-PD BMC Transmitter The TPS65981 transmits and receives USB-PD data over one of the C_CCn pins. The C_CCn pin is also used to determine the cable orientation (see the Cable Plug and Orientation Detection section) and maintain cable/device attach detection.
  • Page 31 Digitally Adjustable VREF USB-PD Modem Copyright © 2016, Texas Instruments Incorporated Figure 14. USB-PD BMC TX/Rx Block Diagram Figure 15 shows the transmission of the BMC data on top of the DC bias. Note, The DC bias can be anywhere...
  • Page 32 9.3.1.5 USB-PD BMC Receiver The receiver block of the TPS65981 receives a signal that falls within the allowed Rx masks defined in the USB PD specification. The receive thresholds and hysteresis come from this mask. The values for VRXTR and...
  • Page 33 Mode attached When the TPS65981 is configured as a DFP, a current IH_CC is driven out each C_CCn pin and each pin is monitored for different states. When a UFP is attached to the pin, a pull-down resistance of Rd to GND will exist.
  • Page 34 Figure 19. C_CCn and RPD_Gn pins When C_CC1 is shorted to RPD_G1 and C_CC2 is shorted to RPD_G2 in an application of the TPS65981, booting from dead-battery or no-battery conditions will be supported. In this case, the gate driver for the pull- down FET is Hi-Z at the output.
  • Page 35 Figure 20. Port Power Paths 9.3.3.1 5-V Power Delivery The TPS65981 provides port power to VBUS from PP_5V0 when a low voltage output is needed. The switch path provides 5 V at up to 3 A to from PP_5V0 to VBUS.
  • Page 36 2 Ω. I VBUS VBUS Time (5 Ps/div) D004 Figure 22. PP_5V0 Current Limit with a Hard Short Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 37 9.3.3.5 Internal HV Power Delivery The TPS65981 has an integrated, bi-directional high-voltage switch that is rated for up to 3 Amps of current. The TPS65981 is capable of sourcing or sinking high-voltage power through an internal switch path designed to support USB-PD power up to 20 V at 3 A of current.
  • Page 38 9.3.3.6 Internal HV Power Switch as a Source The TPS65981 provides power from PP_HV to VBUS at the USB Type-C port as an output when operating as a source. When the switch is on as a source, the path behaves resistively until the current reaches the amount...
  • Page 39 USB PD specification: 20 V at 5 A of current. The TPS65981 provides external control and sense to external NMOS power switches for currents greater than 3 A.
  • Page 40 PP_HV to VBUS when the TPS65981 is acting as a power source and the external path may be used to sink current from VBUS to PP_EXT to charge a battery when the TPS65981 is acting as a sink.
  • Page 41 7 μA into the gate capacitance of the switch. The TSSDONE time is independent of the actual final ramp voltage. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 42 When the voltage on BUSPOWERZ is in the VBPZ_DIS range (when BUSPOWERZ is tied to LDO_3V3 as in Figure 31), this indicates that the TPS65981 will not route the 5 V present on VBUS to the entire system. In this case, the TPS65981 will load SPI-connected flash memory and execute this application code. This configuration will disable both the PP_HV and PP_EXT high voltage switches and only use VBUS to power the TPS65981.
  • Page 43 VSRCNEW of the new voltage. During the time TSTABLE, the voltage may fall below the new voltage, but will remain within VSRCNEW of this voltage. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 44 Figure 35. Negative Voltage Transition on VBUS 9.3.3.19 HV Transition to PP_RV0 Pull-down on VBUS The TPS65981 has an integrated active pull-down on VBUS when transitioning from PP_HV to PP_5V0, shown Figure 36. When the PP_HV switch is disabled and VBUS > PP_5V0 + VHVDISPD, amplifier turns on a current source and pulls down on VBUS.
  • Page 45 PP_CABLE, the other is connected to the USB-PD BMC modem. The red line shows the power path and the green line shows the data path. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 46 Active Cable Circuitry VCONN C_CC1 USB-PD Power Digital Core LDO_3V3 C_CC2 USB-PD Data C_CC2 Gate Control Figure 39. Port C_CC1 and C_CC2 Reverse Orientation Power from PP_CABLE Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 47 Figure 40. PP_CABLE to C_CCn Current Limit With a Hard Short I CC2 C_CC2 PP_CABLE Time (500 Ps/div) D010 Figure 41. PP_CABLE to C_CCn Current Limit With a Hard Short (Extended Time Base) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 48 There are two USB output ports that may or may not be passing USB data. When an Alternate Mode is connected, these same ports may also pass that data (for example, DisplayPort). Note, the TPS65981 pin to receptacle mapping is shown in Table 2.
  • Page 49 SBU_INT2 C_SBU2 DEBUG1 AUX_P/N Copyright © 2016, Texas Instruments Incorporated Figure 44. Port Data Multiplexers Table 3 shows the typical signal types through the switch path. All switches are analog pass switches. These switch paths are not limited to the specified signal type. For the signals that interface with the digital core, the maximum data rate is dictated by the clock rate at which the core is running.
  • Page 50 Specification. 9.3.4.4 Signal Monitoring and Pull-up and Pull-down The TPS65981 has comparators that may be enabled to interrupt the core when a switching event occurs on any of the port inputs. The input parameters for the detection are shown in...
  • Page 51 As the pin voltage rises above the VCLMP_IND voltage, the clamping circuit activates, and sinks current to ground, preventing the voltage from rising further. 2nd Stage Mux Input VREF Figure 46. Port Multiplexer Clamp Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 52 The USB low-speed Endpoint is a USB 2.0 low-speed (1.5 Mbps) interface used to support HID class based accesses. The TPS65981 supports control of endpoint EP0. This endpoint enumerates to a USB 2.0 bus to provide USB-Billboard information to a host system as defined in the USB Type-C standard. EP0 is used for advertising the Billboard Class.
  • Page 53 ADC integrated in the TPS65981. To provide complete flexibility, 12 independent switches are connected to allow firmware to force voltage, sink current, and read voltage on any of the C_USB_TP, C_USB_TN, C_USB_BP, and C_USB_BN.
  • Page 54 The other way a supply switch-over will occur is when both supplies are present and VIN_3V3 is removed and falls below 2.85 V. In this case, a hard reset of the TPS65981 occurs prompting a re- boot.
  • Page 55 SLVSDC2B – FEBRUARY 2016 – REVISED AUGUST 2016 9.3.6 Digital Core Figure 50 shows a simplified block diagram of the digital core. This diagram shows the interface between the digital and analog portions of the TPS65981. MRESET RESETZ GPIO0,2-8 BUSPOWERZ...
  • Page 56 Table 5. HPD GPIO Configuration HPD (Binary) Configuration GPIO4 GPIO5 HPD TX Generic GPIO HPD RX Generic GPIO HPD TX HPD RX HPD TX/RX (bidirectional) Generic GPIO Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 57 Debounce State HPD_IRQ Interrupt Timer passes Low_Debounce Timer Passes S4: HPD IRQ IRQ_Limit HPD GPIO goes Detect State high before Timer reaches IRQ_Limit Figure 51. HPD RX Flow Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 58 The output from the ADC is available to be read and used by application firmware. Each supply voltage into the TPS65981 is available to be converted including the port power path inputs and outputs. All GPIO, the C_CCn pins, the charger detection voltages are also available for conversion. To read the port power path current sourced to VBUS, the high-voltage and low-voltage power paths are sensed and converted to voltages to be read by the ADC.
  • Page 59 Voltage IPP_CABLE Current CC2_BY5 Voltage GPIO5 Voltage CC1_BY2 Voltage CC2_BY2 Voltage PP_CABLE Voltage VIN_3V3 Voltage VRSTZ_3V3 Voltage BC_ID Voltage LDO_1V8A Voltage LDO_1V8D Voltage LDO_3V3 Voltage Unused Voltage Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 60 Round-Robin Automatic Readout, the channel averaging must be set to 1 sample. When the TPS65981 is running a Round Robin Readout, it will take approximately 696 μs (11 channels × 63.33 μs conversion) to fully convert all channels. Since the conversion is continuous, when a channel is converted, it will overwrite the previous result.
  • Page 61 GPIOn to VDDIO in this configuration. The pull-up and pull-down output drivers are independently controlled from the input and are enabled or disabled via application code in the digital core. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 62 IOBUF_GPIOLSI2C that is identical to IOBUF_GPIOLS with an extended de-glitch time. LDO_3V3 GPIO_OD_EN GPIO_OE GPIO_DO GPIO_PU_EN GPIO_RPU GPIO_RPD GPIO_PD_EN 50 ns DEBUG_CTL1/2 GPIO_DI Deglitch GPIO_AI_EN To ADC Figure 55. IOBUF_GPIOLSI2C (General GPIO) I/O with I C De-glitch Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 63 I2C_IRQnZ I2C_DO Figure 58. IOBUF_I2C I/O 9.3.17.5 IOBUF_GPIOHSPI Figure 59 shows the I/O buffers for the SPI interface. SPI_x SPIin CMOS SPIout Output SPI_OE Figure 59. IOBUF_GPIOHSSPI Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 64: Device Functional Modes

    9.3.18 Thermal Shutdown The TPS65981 has both a central thermal shutdown to the chip and a local thermal shutdown for the power path block. The central thermal shutdown monitors the temperature of the center of the die and disables all functions except for supervisory circuitry and halts digital core when die temperature goes above a rising temperature of TSD_MAIN.
  • Page 65 SLVSDC2B – FEBRUARY 2016 – REVISED AUGUST 2016 Device Functional Modes (continued) Once initial device configuration is complete the boot code determines if the TPS65981 is booting under dead battery condition (VIN_3V3 invalid, VBUS valid). If the boot code determines the TPS65981 is booting under dead battery condition, the BUSPOWERZ pin is sampled to determine the appropriate path for routing VBUS power to the system.
  • Page 66 VIN_3V3, the dead battery flow is followed to allow for the rest of the system to receive power. The state of the BUSPOWERZ pin is read to determine power path configuration for dead battery operation. After the power path is configured, the TPS65981 will continue through the boot process. Figure 63 depicts the full dead battery process.
  • Page 67 Figure 63. Dead-Battery Condition Flow Diagram 9.4.5 Application Code The TPS65981 application code is stored in an external flash memory. The flash memory used for storing the TPS65981 application code may be shared with other devices in the system. The flash memory organization...
  • Page 68 The TPS65981 first attempts to load application code from the low region of the attached flash memory. If any part of the read process yields invalid data, the TPS65981 will abort the low region read and attempt to read from the high region.
  • Page 69 Figure 65. Flash Read Flow 9.4.7 Invalid Flash Memory If the flash memory read fails because of invalid data, the TPS65981 carries out the memory invalid flow and presents the SWD interface on the USB Type-C SBU pins. Memory Invalid Flow depicts the invalid memory process.
  • Page 70: Programming

    C Port is comprised of the I2C_SDA, I2C_SCL, and I2C_IRQZ pins. This interface provide general status information about the TPS65981, as well as the ability to control the TPS65981 behavior, as well as providing information about connections detected at the USB-C receptacle and supporting communications to and from a connected device and/or cable supporting BMC USB-PD.
  • Page 71 Programming (continued) 9.5.2.1 I C Interface Description The TPS65981 support Standard and Fast mode I C interface. The bi-directional I C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pull-up resistor.
  • Page 72 9.5.2.3 I C Address Setting The boot code sets the hardware configurable unique I C address of the TPS65981 before the port is enabled to respond to I C transactions. The unique I C address is determined by a combination of the digital level on the...
  • Page 73 GPIO and the address decoding is done by firmware in the digital core. To Address Decoder DEBUG_CTL1 Tristate DEBUG_CTL2 Debug Data To Address Decoder Figure 73. I C Address Decode Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 74: Application And Implementation

    Type-C and PD charger that is capable of supporting 5 V at 3 A, 9 V at 3 A, 12 V at 3 A (optional), 15 V at 3 A, and 20 V at 5 A. The 5-V , 9-V, 12-V and 15-V outputs are supported by the TPS65981 internal FETs and the 20-V output uses the external FET path controlled by the TPS65981 NFET drive.
  • Page 75 The TPS65981 supports either a 10-mΩ or a 5-mΩ sense resistor on the external FET path. This RSENSE resistor is used for current limiting and is used for the reverse current protection of the power path. A 5 mΩ...
  • Page 76 10.2.1.2.4 VBUS Capacitor and Ferrite Bead A 1-µF ceramic capacitor is placed close to the TPS65981 VBUS pins. A 6-A ferrite bead is used in this design along with four high frequency noise 10-nF capacitors placed close to the Type-C connector to minimize noise.
  • Page 77 PP_EXT path as a sink. If the AC- DC power supply is applied at a later time, the TPS65981 will detect the new power supply, automatically enable one of more Source PDOs, and initiate a Power Role Swap PD message to offer power to the system at the far- end of the Type-C cable.
  • Page 78 The same passive components used in the are also applicable in this design to support all of the features of the TPS65981. Additional design information is provided below for changes in passive components required by the dock or monitor application. The TPS65981 control of the HD3SS460 SuperSpeed multiplexer is explained in...
  • Page 79 The system is design to either operate bus-powered over Type-C/PD or line-powered from the DC barrel jack. The TPS65981 detects that the DC barrel jack is connected to GPIOn. In the simplest form, a voltage divider could be set to the GPIO I/O level when the DC Barrel jack voltage is present, as shown in Figure 77.
  • Page 80 Type-C or Type-C to barrel jack. When the DC barrel jack is detected the TPS65981 at the Type-C port will not request power as a USB PD sink and the system will be able to support a 5-20 V source power contract to another device.
  • Page 81: Power Supply Recommendations

    VBUS when VIN_3V3 is not available. This LDO steps down any recommended voltage on the VBUS pin. When VBUS is 20 V, as is allowable by USB PD, the internal circuitry of the TPS65981 will operate without triggering thermal shutdown; however, a significant external load on the LDO_3V3 pin may increase temperature enough to trigger thermal shutdown.
  • Page 82: Vddio

    11.3.2 Schottky for Current Surge Protection To prevent the possibility of large ground currents into the TPS65981 during sudden disconnects because of inductive effects in a cable, TI recommends that a Schottky be placed from VBUS to GND as shown in Figure 80.
  • Page 83: Layout

    Proper routing and placement will maintain signal integrity for high-speed signals and improve the thermal dissipation from the TPS65981 power path. The combination of power and high-speed data signals are easily routed if the following guidelines are followed. Consult with a printed circuit board (PCB) manufacturer to verify manufacturing capabilities.
  • Page 84 Placement of components on the top and bottom layers is used for this example to minimize solution size. The TPS65981 is placed on the top layer of the board and the majority of the components are placed on the bottom layer.
  • Page 85 PCB project. If any of the vias in the footprint are removed for placing components closer to the TPS65981, a minimum of 6 vias must be used for thermal dissipation to the GND planes. If the number of Thermal Relief vias is reduced, the majority of these vias must be placed on the right side of the device by the power path.
  • Page 86: Layout Example

    SLVSDC2B – FEBRUARY 2016 – REVISED AUGUST 2016 www.ti.com 12.2 Layout Example Copyright © 2016, Texas Instruments Incorporated Figure 83. Example Layout (Top View in 2-D) Copyright © 2016, Texas Instruments Incorporated Figure 84. Example Layout (Bottom View in 2-D) Submit Documentation Feedback Copyright ©...
  • Page 87 SLVSDC2B – FEBRUARY 2016 – REVISED AUGUST 2016 Layout Example (continued) Copyright © 2016, Texas Instruments Incorporated Figure 85. Example Layout (Top View in 3-D) Copyright © 2016, Texas Instruments Incorporated Figure 86. Example Layout (Bottom View in 3-D) Copyright ©...
  • Page 88 TPS65981 SLVSDC2B – FEBRUARY 2016 – REVISED AUGUST 2016 www.ti.com Layout Example (continued) Copyright © 2016, Texas Instruments Incorporated Figure 88. Bottom Polygonal Pours Copyright © 2016, Texas Instruments Incorporated Figure 89. CC1 and CC2 Capacitor Routing Submit Documentation Feedback Copyright ©...
  • Page 89 TPS65981 www.ti.com SLVSDC2B – FEBRUARY 2016 – REVISED AUGUST 2016 Layout Example (continued) Copyright © 2016, Texas Instruments Incorporated Figure 90. Top Layer Component Routing Copyright © 2016, Texas Instruments Incorporated Figure 91. Bottom Layer Component Routing Submit Documentation Feedback Copyright ©...
  • Page 90 TPS65981 SLVSDC2B – FEBRUARY 2016 – REVISED AUGUST 2016 www.ti.com Layout Example (continued) Copyright © 2016, Texas Instruments Incorporated Figure 92. Final Routing (Top Layer) Copyright © 2016, Texas Instruments Incorporated Figure 93. Final Routing (Inner Signal Layer) Copyright © 2016, Texas Instruments Incorporated Figure 94.
  • Page 91: Glossary

    All other trademarks are the property of their respective owners. 13.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 92: Mechanical, Packaging, And Orderable Information

    This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 93 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 94 4222809/A 03/2016 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
  • Page 95 SCALE:12X 4222809/A 03/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS65981...
  • Page 96 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) TPS65981ABIRTQR ACTIVE 2000 Green (RoHS NIPDAUAG Level-3-260C-168 HR -40 to 85 65981ABI &...
  • Page 97 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
  • Page 98 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) TPS65981ABIRTQR 2000 330.0 16.4 12.0 16.0 TPS65981ABIRTQT 180.0 16.4 12.0...
  • Page 99 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) TPS65981ABIRTQR 2000 367.0 367.0 38.0 TPS65981ABIRTQT 210.0 185.0 35.0 TPS65981ABTRTQR 2000 367.0 367.0 38.0 TPS65981ABTRTQT 210.0 185.0 35.0 Pack Materials-Page 2...
  • Page 100 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated...

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