Texas Instruments MSP430x6 series Manuals

Manuals and User Guides for Texas Instruments MSP430x6 series. We have 1 Texas Instruments MSP430x6 series manual available for free PDF download: User Manual

Texas Instruments MSP430x6 series User Manual (1190 pages)

Brand: Texas Instruments | Category: Controller | Size: 7 MB

Msp430X5Xx and Msp430X6Xx Family User's Guide

2
- Table of Contents
  2
30
Table of Contents

37
- Preface
  
  52
- System Resets, Interrupts, and Operating Modes, System Control Module (SYS)
  
  54
  - System Control Module (SYS) Introduction
    55
  - System Reset and Initialization
    55
  - BOR/POR/PUC Reset Circuit
    56
    
    Device Initial Conditions after System Reset
    57
    
    Interrupts
    57
    
    Non)Maskable Interrupts (Nmis)
    58
  - Interrupt Priority
    58
    
    Interrupt Processing
    59
    
    Maskable Interrupts
    59
    
    SNMI Timing
    59
  - Nmis with Reentrance Protection
    59
  - Interrupt Processing
    60
    
    Interrupt Nesting
    61
    
    Interrupt Vectors
    61
  - Return from Interrupt
    61
  - Interrupt Sources, Flags, and Vectors
    61
    
    SYS Interrupt Vector Generators
    62
  - Svm
    62
    
    Operating Modes
    63
  - Operation Modes
    64
  - Operation Modes
    65
    
    Entering and Exiting Low-Power Modes LPM0 through LPM4
    66
    
    Entering and Exiting Low-Power Modes Lpmx.5
    67
    
    Extended Time in Low-Power Modes
    68
    
    Principles for Low-Power Applications
    69
    
    Connection of Unused Pins
    70
    
    Reset Pin (RST/NMI) Configuration
    70
    
    Boot Code
    71
    
    Bootloader (BSL)
    71
    
    Configuring JTAG Pins
    71
    
    Memory Map - Uses and Abilities
    72
    
    JMB Configuration
    73
    
    JMBOUT0 and JMBOUT1 Outgoing Mailbox
    73
    
    JTAG Lock Mechanism Using the Electronic Fuse
    73
    
    JTAG Mailbox (JMB) System
    73
    
    Vacant Memory Space
    73
    
    Device Descriptor Table
    74
    
    JMB NMI Usage
    74
    
    JMBIN0 and JMBIN1 Incoming Mailbox
    74
    
    Identifying Device Type
    75
    
    TLV Descriptors
    75
  - Devices Descriptor Table
    75
  - Tag Values
    76
    
    Peripheral Discovery Descriptor
    77
  - Values for Memory Entry
    78
  - Values for Peripheral Entry
    78
  - Peripheral Ids
    79
  - Sample Peripheral Discovery Descriptor
    80
    
    CRC Computation
    81
    
    Calibration Values
    82
    
    Temperature Sensor Calibration for Devices with CTSD16
    83
    
    SFR Registers
    84
  - SFR Base Address
    84
    
    SFRIE1 Register
    85
  - SFRIE1 Register Description
    85
    
    SFRIFG1 Register
    86
  - SFRIFG1 Register Description
    86
    
    SFRRPCR Register
    87
  - SFRRPCR Register Description
    87
    
    SYS Registers
    88
  - SYS Base Address
    88
  - SYSCTL Register
    89
  - SYSCTL Register Description
    89
  - SYSBSLC Register
    90
  - SLAU208Q - June 2008 - Revised March 2018
    90
  - SYSBSLC Register Description
    90
    
    SYSJMBC Register
    91
  - SYSJMBC Register Description
    91
    
    SYSJMBI0 Register
    92
    
    SYSJMBI1 Register
    92
  - SYSJMBI0 Register Description
    92
  - SYSJMBI1 Register Description
    92
    
    SYSJMBO0 Register
    93
    
    SYSJMBO1 Register
    93
  - SYSJMBO0 Register Description
    93
  - SYSJMBO1 Register Description
    93
    
    SYSUNIV Register
    94
  - SYSUNIV Register Description
    94
    
    SYSSNIV Register
    95
  - SYSSNIV Register Description
    95
    
    SYSRSTIV Register
    96
  - SYSRSTIV Register Description
    96
    
    SYSBERRIV Register
    97
  - SYSBERRIV Register Description
    97
- Power Management Module and Supply Voltage Supervisor
  
  98
  - Power Management Module (PMM) Introduction
    99
  - System Frequency, Supply Voltage, and Core Voltage - See Device-Specific Data Sheet
    99
  - PMM Block Diagram
    100
  - Svs
    100
  - Svm
    100
    
    And the Regulator
    101
    
    PMM Operation
    101
    
    Supply Voltage Supervisor and Monitor
    101
  - SVS and SVM Thresholds
    102
  - Recommended SVS Settings
    102
  - Available SVM H Settings Versus VCORE Settings
    103
  - Available SVS H and SVMH
    103
    
    CORE Settings
    103
  - High-Side and Low-Side Voltage Failure and Resulting PMM Actions
    104
  - High-Side SVS and SVM
    105
  - Low-Side SVS and SVM
    106
    
    Core
    107
    
    Increasing
    107
    
    Supply Voltage Supervisor and Monitor - Power up
    107
    
    To Support Higher MCLK Frequencies
    107
  - PMM Action at Device Power-Up
    107
  - CORE and SVML and SVSL Levels
    108
    
    Brownout Reset (BOR), Software BOR, Software por
    109
    
    For Power Optimization
    109
    
    LPM3.5 and LPM4.5
    109
    
    SVS and SVM Performance Modes and Wake-Up Times
    110
  - SVS L and SVML
    111
  - Svs
    111
  - SVS L Manual Performance Modes
    111
  - Svm
    111
  - SVM L Manual Performance Modes
    111
    
    H and SVMH Control Mode Selection
    112
    
    H Automatic Performance Control
    112
    
    H Manual Performance Modes
    112
    
    PMM Interrupts
    113
    
    Port I/O Control
    113
    
    Supply Voltage Monitor Output (SVMOUT, Optional)
    113
    
    PMM Registers
    114
    
    PMMCTL0 Register
    115
  - PMMCTL0 Register Description
    115
    
    PMMCTL1 Register
    116
  - PMMCTL1 Register Description
    116
    
    SVSMHCTL Register
    117
    
    SVSMHCTL Register Description
    117
    
    SVSMLCTL Register
    118
    
    SVSMLCTL Register Description
    118
    
    SVSMIO Register
    119
    
    SVSMIO Register Description
    119
    
    PMMIFG Register
    120
    
    PMMRIE Register
    122
    
    PM5CTL0 Register
    123
- Battery Backup System
  
  124
  - Battery Backup Introduction
    125
  - Battery Backup Operation
    125
    
    Activate Access to Backup-Supplied Subsystem
    126
  - Battery Backup Switch Overview
    126
    
    Disable Switching
    127
    
    Lpmx.5 and Backup Operation
    127
    
    Manual Switching
    127
    
    Measuring the Supplies
    127
    
    Resistive Charger
    128
  - Charger Block Diagram
    128
    
    Battery Backup Registers
    129
    
    BAKCTL Register
    130
    
    BAKCHCTL Register
    131
- Auxiliary Supply System (AUX)
  
  132
  - Auxiliary Supply System Introduction
    133
  - Auxiliary Supply Operation
    134
    
    Start-Up
    135
  - Auxiliary Supply Switch Overview
    135
    
    Hardware-Controlled Switching
    136
    
    Software-Controlled Switching
    136
    
    Switching Control
    136
    
    Interactions Among F
    138
    
    SLAU208Q - June 2008 - Revised March 2018
    138
    
    SYS , VCORE , VDSYS , SVM H , and Auxxlvl
    138
  - Next Supply Voltage Selection
    138
  - System Frequency Vs Supply Voltage
    139
  - Available SVM
    139
  - Settings Vs V
    139
  - Settings
    139
    
    Auxiliary Supply Monitor
    140
  - H Settings
    140
  - Auxiliary Supply Monitor Block Diagram
    141
    
    Digital I/Os and Auxiliary Supplies
    142
    
    Lpmx.5 and Auxiliary Supply Operation
    142
    
    Measuring the Supplies
    143
  - I/Os Powered by Auxiliary Supplies
    143
  - AUX Connection to ADC
    143
    
    Auxiliary Supply Interrupts
    144
    
    Resistive Charger
    144
  - Charger Block Diagram
    144
    
    Examples of aux Operation
    146
    
    Software Flow
    146
  - Software Flow Chart
    146
  - Svs
    147
    
    AUX Registers
    149
    
    AUXCTL0 Register
    150
    
    AUXCTL1 Register
    151
    
    AUXCTL2 Register
    152
    
    AUX2CHCTL Register
    153
    
    AUX3CHCTL Register
    154
    
    AUXADCCTL Register
    155
    
    AUXIFG Register
    156
    
    AUXIE Register
    157
    
    AUXIV Register
    158
- Unified Clock System (UCS)
  
  159
  - Unified Clock System (UCS) Introduction
    160
  - UCS Block Diagram
    161
    
    Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    162
    
    UCS Module Features for Low-Power Applications
    162
    
    UCS Operation
    162
    
    Internal Trimmed Low-Frequency Reference Oscillator (REFO)
    163
    
    XT1 Oscillator
    163
    
    XT2 Oscillator
    164
    
    Digitally Controlled Oscillator (DCO)
    165
    
    Frequency Locked Loop (FLL)
    166
    
    DCO Modulator
    167
    
    Disabling FLL Hardware and Modulator
    167
    
    FLL Operation from Low-Power Modes
    167
  - Modulator Patterns
    167
    
    Operation from Low-Power Modes, Requested by Peripheral Modules
    168
  - Module Request Clock System
    168
    
    UCS Module Fail-Safe Operation
    169
  - Oscillator Fault Logic
    171
    
    Synchronization of Clock Signals
    172
    
    MODOSC Operation
    173
    
    Module Oscillator (MODOSC)
    173
  - Switch MCLK from DCOCLK to XT1CLK
    173
    
    UCS Registers
    174
    
    UCSCTL0 Register
    175
    
    UCSCTL1 Register
    176
    
    UCSCTL2 Register
    177
    
    UCSCTL3 Register
    178
    
    UCSCTL4 Register
    179
    
    UCSCTL5 Register
    180
    
    UCSCTL6 Register
    181
    
    UCSCTL7 Register
    183
    
    UCSCTL8 Register
    184
    
    UCSCTL9 Register
    185
- Cpux
  
  186
  - MSP430X CPU (CPUX) Introduction
    187
  - MSP430X CPU Block Diagram
    188
    
    Interrupts
    189
  - PC Storage on the Stack for Interrupts
    189
    
    CPU Registers
    190
    
    Program Counter (PC)
    190
    
    Stack Pointer (SP)
    190
  - Program Counter
    190
  - PC Storage on the Stack for CALLA
    190
  - Stack Pointer
    191
  - Stack Usage
    191
  - PUSHX.A Format on the Stack
    191
  - PUSH SP, POP SP Sequence
    191
    
    Status Register (SR)
    192
  - SR Bits
    192
    
    Constant Generator Registers (CG1 and CG2)
    193
    
    General-Purpose Registers (R4 to R15)
    194
  - Register-Byte and Byte-Register Operation
    194
  - Register-Word Operation
    194
  - Word-Register Operation
    195
  - Register - Address-Word Operation
    195
    
    Addressing Modes
    196
  - Address-Word - Register Operation
    196
    
    Register Mode
    197
    
    Indexed Mode
    198
  - Indexed Mode in Lower 64KB
    198
  - Indexed Mode in Upper Memory
    199
  - Overflow and Underflow for Indexed Mode
    200
  - Example for Indexed Mode
    201
    
    Symbolic Mode
    203
  - Symbolic Mode Running in Lower 64KB
    203
  - Symbolic Mode Running in Upper Memory
    204
  - Overflow and Underflow for Symbolic Mode
    205
    
    Absolute Mode
    207
    
    Indirect Register Mode
    209
    
    Indirect Autoincrement Mode
    210
    
    Immediate Mode
    211
    
    MSP430 and MSP430X Instructions
    213
    
    MSP430 Instructions
    213
  - MSP430 Double-Operand Instruction Format
    213
  - MSP430 Single-Operand Instructions
    214
  - Format of Conditional Jump Instructions
    215
  - Interrupt, Return, and Reset Cycles and Length
    216
  - MSP430 Format I Instructions Cycles and Length
    217
    
    MSP430X Extended Instructions
    218
  - Example for Extended Register or Register Instruction
    219
  - Example for Extended Immediate or Indexed Instruction
    220
  - Extended Format I Instruction Formats
    221
  - Extended Format II Instruction Format
    222
  - PUSHM and POPM Instruction Format
    223
  - Extended Emulated Instructions
    224
  - Address Instructions, Operate on 20-Bit Register Data
    225
  - MSP430X Format II Instruction Cycles and Length
    226
  - MSP430X Format I Instruction Cycles and Length
    227
  - Address Instruction Cycles and Length
    228
    
    Instruction Set Description
    229
  - Instruction Map of MSP430X
    229
    
    Extended Instruction Binary Descriptions
    230
    
    MSP430 Instructions
    232
  - Decrement Overlap
    249
  - Stack after a RET Instruction
    268
    
    Destination Operand—Arithmetic Shift Left
    270
    
    Destination Operand—Carry Left Shift
    271
  - Rotate Right Arithmetically RRA.B and RRA.W
    272
  - Rotate Right through Carry RRC.B and RRC.W
    273
  - Swap Bytes in Memory
    280
    
    Extended Instructions
    284
    
    Rotate Left Arithmetically—Rlam[.W] and RLAM.A
    307
  - Destination Operand-Arithmetic Shift Left
    308
  - Destination Operand-Carry Left Shift
    309
  - Rotate Right Arithmetically RRAM[.W] and RRAM.A
    310
  - Rotate Right Arithmetically RRAX(.B,.A) – Register Mode
    312
  - Rotate Right through Carry RRCM[.W] and RRCM.A
    314
  - Rotate Right through Carry RRCX(.B,.A) – Register Mode
    316
  - Rotate Right Unsigned RRUM[.W] and RRUM.A
    317
  - Rotate Right Unsigned RRUX(.B,.A) – Register Mode
    318
  - Swap Bytes SWPBX.A Register Mode
    322
  - Swap Bytes SWPBX[.W] Register Mode
    323
  - Sign Extend SXTX.A
    324
    
    Address Instructions
    327
- Flash Memory Controller
  
  342
  - Flash Memory Introduction
    343
  - Flash Memory Segmentation
    344
    
    Segment a
    345
  - Flash Memory Operation
    346
    
    Erasing Flash Memory
    346
  - Supported Simultaneous Code Execution and Flash Operations
    346
  - Erase Modes
    346
  - Erase Cycle Timing
    347
  - Erase Cycle from Flash
    348
  - Erase Cycle from RAM
    349
    
    Writing Flash Memory
    350
  - Write Modes
    350
  - Initiating a Byte or Word Write from Flash
    351
  - Initiating a Byte or Word Write from RAM
    352
  - Initiating Long-Word Write from Flash
    353
  - Initiating Long-Word Write from RAM
    354
  - Block-Write Cycle Timing
    355
  - Block Write Flow
    356
    
    Flash Memory Access During Write or Erase
    357
  - Flash Access While Flash Is Busy (BUSY = 1)
    357
    
    Checking Flash Memory
    358
    
    Stopping Write or Erase Cycle
    358
    
    Configuring and Accessing the Flash Memory Controller
    359
    
    Flash Memory Controller Interrupts
    359
    
    Programming Flash Memory Devices
    360
  - User-Developed Programming Solution
    360
    
    FCTL Registers
    361
    
    FCTL1 Register
    362
  - FCTL1 Register Description
    362
    
    FCTL3 Register
    363
  - FCTL3 Register Description
    363
    
    FCTL4 Register
    364
  - FCTL4 Register Description
    364
    
    SFRIE1 Register
    365
  - SFRIE1 Register Description
    365
- Memory Integrity Detection (MID)
  
  366
  - MID Overview
    367
  - Block Diagram of MID Implementation
    367
    
    Detecting Unprogrammed Memory Accesses
    368
    
    Flash Memory with MID Support
    368
    
    MID Parity Check Logic
    368
  - Overview of MSP430 Flash Memory Segmentation
    368
    
    MID Rom
    369
    
    MID Support Software Function
    369
  - Overview of MID Support Software Functions
    369
    
    Midenable() Function
    370
  - Cw0 Parameter
    370
  - Cw1 Parameter
    370
    
    Middisable() Function
    371
    
    Midgeterradr() Function
    371
    
    Midcheckmem() Function
    372
    
    Midsetraw() Function
    372
    
    Midcalcvparity() Function
    373
    
    Midgetparity() Function
    373
    
    User's UNMI Interrupt Handler
    373
    
    SLAU208Q - June 2008 - Revised March 2018
    374
- RAM Controller (RAMCTL)
  
  374
  - RAM Controller (RAMCTL) Introduction
    375
  - RAMCTL Registers
    376
  - RCCTL0 Register
    377
  - RCCTL0 Register Description
    377
- Backup RAM
  
  378
  - Backup RAM Registers
    379
    
    Backup RAM Introduction and Operation
    379
- Direct Memory Access (DMA) Controller Module
  
  380
  - Direct Memory Access (DMA) Introduction
    381
  - DMA Controller Block Diagram
    382
  - DMA Addressing Modes
    383
  - DMA Operation
    383
  - DMA Transfer Modes
    384
  - DMA Single Transfer State Diagram
    385
  - DMA Block Transfer State Diagram
    387
  - DMA Burst-Block Transfer State Diagram
    389
    
    Initiating DMA Transfers
    390
  - DMA Trigger Operation
    391
    
    Stopping DMA Transfers
    391
  - Maximum Single-Transfer DMA Cycle Time
    392
    
    DMA Transfer Cycle Time
    392
    
    Using ADC10 with the DMA Controller
    394
  - DMA Registers
    395
  - DMACTL0 Register
    397
  - DMACTL0 Register Description
    397
  - DMACTL1 Register
    398
  - DMACTL1 Register Description
    398
  - DMACTL2 Register
    399
  - DMACTL2 Register Description
    399
  - DMACTL3 Register
    400
  - DMACTL3 Register Description
    400
  - DMACTL4 Register
    401
  - DMACTL4 Register Description
    401
  - Dmaxctl Register
    402
  - Dmaxctl Register Description
    402
  - Dmaxsa Register
    404
  - Dmaxsa Register Description
    404
  - Dmaxda Register
    405
  - Dmaxda Register Description
    405
  - Dmaxsz Register
    406
  - Dmaxsz Register Description
    406
  - DMAIV Register
    407
  - DMAIV Register Description
    407
- Digital I/O Module
  
  408
  - Digital I/O Introduction
    409
  - I/O Configuration
    410
    
    Digital I/O Operation
    410
    
    Output Drive Strength Registers (Pxds)
    411
    
    Configuring Unused Port Pins
    413
  - Digital I/O Registers
    416
  - P1IV Register
    422
  - P1IV Register Description
    422
  - P2IV Register
    423
  - P2IV Register Description
    423
  - P1IES Register
    424
  - P1IE Register
    424
  - P1IFG Register
    424
  - P1IES Register Description
    424
  - P1IE Register Description
    424
  - P1IFG Register Description
    424
  - P2IES Register
    425
  - P2IE Register
    425
  - P2IFG Register
    425
  - P2IES Register Description
    425
  - P2IE Register Description
    425
  - P2IFG Register Description
    425
  - Pxin Register
    426
  - Pxout Register
    426
  - Pxdir Register
    426
  - Pxin Register Description
    426
  - Pxout Register Description
    426
  - Pxdir Register Description
    426
  - Pxren Register
    427
  - Pxds Register
    427
  - Pxsel Register
    427
  - Pxren Register Description
    427
  - Pxds Register Description
    427
  - Pxsel Register Description
    427
- Port Mapping Controller
  
  428
  - Port Mapping Controller Introduction
    429
  - Examples for Port Mapping Mnemonics and Functions
    430
  - Port Mapping Control Registers
    431
  - Port Mapping Registers for Port Px - Byte Access
    431
  - Port Mapping Registers for Port Px - Word Access
    431
    
    Port Mapping Controller Registers
    431
  - PMAPKEYID Register
    432
  - PMAPCTL Register
    432
  - Pxmapy Register
    432
  - PMAPKEYID Register Description
    432
  - PMAPCTL Register Description
    432
  - Pxmapy Register Description
    432
- Cyclic Redundancy Check (CRC) Module
  
  433
  - LFSR Implementation of CRC-CCITT Standard, Bit 0 Is the MSB of the Result
    434
    
    Cyclic Redundancy Check (CRC) Module Introduction
    434
    
    CRC Checksum Generation
    435
  - Implementation of CRC-CCITT Using the CRCDI and CRCINIRES Registers
    436
    
    Assembler Examples
    436
  - CRC Registers
    438
  - CRCDI Register
    439
  - CRCDIRB Register
    439
  - CRCDI Register Description
    439
  - CRCDIRB Register Description
    439
  - CRCINIRES Register
    440
  - CRCRESR Register
    440
  - CRCINIRES Register Description
    440
  - CRCRESR Register Description
    440
- AES Accelerator
  
  441
  - AES Accelerator Block Diagram
    442
    
    AES Accelerator Introduction
    442
  - AES State Array Input and Output
    443
    
    AES Accelerator Operation
    443
  - Encryption Process
    444
  - Decryption Process Using Aesopx = 01
    445
  - Decryption Process Using Aesopx = 10 and 11
    446
    
    Decryption Key Generation
    446
    
    Using the AES Accelerator with Low-Power Modes
    447
  - AES_ACCEL Registers
    448
  - AESACTL0 Register
    449
  - AESACTL0 Register Description
    449
  - AESASTAT Register
    450
  - AESASTAT Register Description
    450
  - AESAKEY Register
    451
  - AESAKEY Register Description
    451
  - AESADIN Register
    452
  - AESADOUT Register
    452
  - AESADIN Register Description
    452
  - AESADOUT Register Description
    452
- Watchdog Timer (WDT_A)
  
  453
  - WDT_A Introduction
    454
  - Watchdog Timer Block Diagram
    455
    
    WDT_A Operation
    456
    
    Clock Fail-Safe Feature
    457
  - WDT_A Registers
    458
  - WDTCTL Register
    459
  - WDTCTL Register Description
    459
- Timer_A
  
  460
  - Timer_A Introduction
    461
  - Timer_A Block Diagram
    462
    
    Timer_A Operation
    463
  - Up Mode
    464
  - Up Mode Flag Setting
    464
  - Timer Modes
    464
    
    Timer Mode Control
    464
  - Continuous Mode
    465
  - Continuous Mode Flag Setting
    465
  - Continuous Mode Time Intervals
    465
  - Up/Down Mode
    466
  - Up/Down Mode Flag Setting
    466
  - Output Unit in Up/Down Mode
    467
    
    Capture/Compare Blocks
    467
  - Capture Signal (SCS = 1)
    468
  - Capture Cycle
    468
  - Output Modes
    469
    
    Output Unit
    469
  - Output Example - Timer in up Mode
    470
  - Output Example - Timer in Continuous Mode
    471
  - Output Example - Timer in Up/Down Mode
    472
  - Capture/Compare Interrupt Flag
    473
    
    Timer_A Interrupts
    473
  - Timer_A Registers
    475
  - Taxctl Register
    476
  - Taxctl Register Description
    476
  - Taxr Register
    477
  - Taxr Register Description
    477
  - Taxcctln Register
    478
  - Taxcctln Register Description
    478
  - Taxccrn Register
    480
  - Taxiv Register
    480
  - Taxccrn Register Description
    480
  - Taxiv Register Description
    480
  - Taxex0 Register
    481
  - Taxex0 Register Description
    481
- Timer_B
  
  482
  - Timer_B Introduction
    483
  - Timer_B Block Diagram
    484
    
    Timer_B Operation
    485
  - Up Mode
    486
  - Up Mode Flag Setting
    486
  - Timer Modes
    486
    
    Timer Mode Control
    486
  - Continuous Mode
    487
  - Continuous Mode Flag Setting
    487
  - Continuous Mode Time Intervals
    487
  - Up/Down Mode
    488
  - Up/Down Mode Flag Setting
    488
  - Output Unit in Up/Down Mode
    489
    
    Capture/Compare Blocks
    489
  - Capture Signal (SCS = 1)
    490
  - Capture Cycle
    490
  - Tbxcln Load Events
    491
  - Compare Latch Operating Modes
    492
  - Output Modes
    492
    
    Output Unit
    492
  - Output Example - Timer in up Mode
    493
  - Output Example - Timer in Continuous Mode
    494
  - Output Example - Timer in Up/Down Mode
    495
  - Capture/Compare Tbxccr0 Interrupt Flag
    496
    
    Timer_B Interrupts
    496
  - Timer_B Registers
    498
  - Tbxctl Register
    499
  - Tbxctl Register Description
    499
  - Tbxr Register
    501
  - Tbxr Register Description
    501
  - Tbxcctln Register
    502
  - Tbxcctln Register Description
    502
  - Tbxccrn Register
    504
  - Tbxccrn Register Description
    504
  - Tbxiv Register
    505
  - Tbxiv Register Description
    505
  - Tbxex0 Register
    506
  - Tbxex0 Register Description
    506
    
    Timer_D
    507
    
    Timer_D Introduction
    508
  - Timer_D Block Diagram
    509
    
    Timer_D Operation
    510
  - High Resolution Clock Generator
    511
    
    High-Resolution Generator
    511
  - Factory Preprogrammed Frequency and Tdhmx, TDHCLKCR Bit Settings
    512
  - Timer Modes
    513
    
    Starting the Timer
    513
  - Up Mode
    514
  - Up Mode Flag Setting
    514
  - Continuous Mode
    514
  - Continuous Mode Flag Setting
    515
  - Continuous Mode Time Intervals
    515
  - Tdxccr0 PWM Generation under Continuous Mode
    516
  - Up/Down Mode
    516
  - Up/Down Mode Flag Setting
    517
  - Output Unit in Up/Down Mode
    518
    
    PWM Generation
    518
  - High-Resolution Mode Limitation (TDHEN = 1) - Minimum Duty Cycle
    519
  - High-Resolution Mode Limitation (TDHEN = 1) - Maximum Duty Cycle
    519
  - Controlling Rising and Falling Edge of PWM Output in up Mode
    520
  - Deadband Generation (Tdxcmb = 1)
    521
    
    Capture/Compare Blocks
    521
  - Capture Signal (SCS = 1)
    522
  - Single Capture Cycle
    522
  - Sequential Capture Events in Dual Capture Mode
    523
  - COV in Dual Capture Mode
    523
  - Tdclx Load Events
    524
  - Compare Latch Operating Modes
    524
    
    Compare Mode
    524
  - Output Modes
    525
    
    Switching from Capture to Compare Mode
    525
  - Output Example, Channel 1 - Timer in up Mode
    527
  - Output Example, Channel 1 - Timer in up Mode with External Fault Signal
    528
  - Output Example - Timer in up Mode with External Timer Clear Signal
    529
  - Output Example - Timer in Continuous Mode
    530
  - Output Example - Timer in Up/Down Mode
    531
  - Capture/Compare Tdxccr0 Interrupt Flag
    532
    
    Synchronization between Timer_D Instances
    532
  - Timer_D Registers
    534
  - Tdxctl0 Register
    535
  - Tdxctl0 Register Description
    535
  - Tdxctl1 Register
    537
  - Tdxctl1 Register Description
    537
  - Tdxctl2 Register
    538
  - Tdxctl2 Register Description
    538
  - Tdxr Register
    539
  - Tdxr Register Description
    539
  - Tdxcctln Register
    540
  - Tdxcctln Register Description
    540
  - Tdxccrn Register
    542
  - Tdxcln Register
    542
  - Tdxhctl0 Register
    543
  - Tdxhctl1 Register
    544
  - Tdxhint Register
    545
  - Tdxiv Register
    546
- Timer Event Control (TEC)
  
  547
  - Timer Event Control Block Diagram
    548
    
    TEC Operation
    549
  - External Input Events Affect Timer_D Output
    550
  - Timer_D Output with Channel Combination
    550
    
    Module Level Connection between TEC and Timer_D
    550
  - Module Level Connection between TEC and Timer_D
    551
    
    Synchronization Mechanism between Timer_D Instances
    552
  - Synchronization between Timer Instances
    553
    
    Timer Event Control Interrupts
    554
  - TEC Registers
    555
  - Tecxctl0 Register
    556
  - Tecxctl1 Register
    558
  - Tecxctl2 Register
    560
  - Tecxsta Register
    561
  - Tecxint Register
    562
  - Tecxiv Register
    563
- Real-Time Clock (RTC) Overview
  
  564
- Real-Time Clock (RTC_A)
  
  565
  - RTC_A Introduction
    566
  - Rtc_A
    567
    
    RTC_A Operation
    568
    
    Real-Time Clock Interrupts
    570
    
    Real-Time Clock Calibration
    572
    
    RTC_A Registers
    574
  - RTCCTL0 Register
    576
  - RTCCTL1 Register
    577
  - RTCCTL2 Register
    578
    
    RTCNT1 Register
    579
    
    RTCSEC Register – Calendar Mode with Hexadecimal Format
    580
    
    RTCMIN Register – Calendar Mode with Hexadecimal Format
    581
    
    RTCHOUR Register – Calendar Mode with Hexadecimal Format
    582
    
    RTCDOW Register – Calendar Mode
    583
    
    RTCMON Register – Calendar Mode with Hexadecimal Format
    584
    
    RTCYEARL Register – Calendar Mode with Hexadecimal Format
    585
    
    RTCYEARH Register – Calendar Mode with Hexadecimal Format
    586
    
    RTCAMIN Register – Calendar Mode with Hexadecimal Format
    587
    
    RTCAHOUR Register – Calendar Mode with Hexadecimal Format
    588
  - RTCADOW Register
    589
    
    RTCADAY Register – Calendar Mode with BCD Format
    590
    
    RTCPS0CTL Register
    591
    
    RTCPS1CTL Register
    592
    
    RT0PS Register
    593
- Real-Time Clock B (RTC_B)
  
  594
  - Real-Time Clock RTC_B Introduction
    595
  - RTC_B Block Diagram
    596
    
    RTC_B Operation
    597
    
    Reading or Writing Real-Time Clock Registers
    598
    
    Real-Time Clock Calibration
    600
    
    Real-Time Clock Operation in LPM3.5 Low-Power Mode
    601
  - RTC_B Registers
    602
  - RTCCTL0 Register
    604
  - RTCCTL1 Register
    605
  - RTCCTL2 Register
    606
    
    RTCSEC Register – Hexadecimal Format
    607
    
    RTCMIN Register – Hexadecimal Format
    608
    
    RTCHOUR Register – Hexadecimal Format
    609
  - RTCDOW Register
    610
    
    RTCMON Register – Hexadecimal Format
    611
    
    RTCYEAR Register – Hexadecimal Format
    612
    
    RTCAMIN Register – Hexadecimal Format
    613
    
    RTCAHOUR Register – Hexadecimal Format
    614
    
    RTCADOW Register
    615
    
    RTCADAY Register – Hexadecimal Format
    616
    
    RTCPS0CTL Register
    617
    
    RTCPS1CTL Register
    618
    
    RTCPS0 Register
    619
  - RTCIV Register
    620
  - BIN2BCD Register
    621
- Real-Time Clock C (RTC_C)
  
  622
- Bit Hardware Multiplier (MPY32)
  
  672
  - Bit Hardware Multiplier (MPY32) Introduction
    673
  - MPY32 Block Diagram
    674
    
    MPY32 Operation
    675
    
    Operand Registers
    676
    
    Result Registers
    677
    
    Software Examples
    678
    
    Fractional Numbers
    679
  - Result Availability in Fractional Mode (MPYFRAC = 1, MPYSAT = 0)
    680
  - Saturation Flow Chart
    681
    
    Putting It All Together
    682
  - Multiplication Flow Chart
    683
    
    Indirect Addressing of Result Registers
    685
    
    Using DMA
    686
  - MPY32 Registers
    687
  - Alternative Registers
    688
  - MPY32CTL0 Register
    689
    
    REF Introduction
    691
  - REF Block Diagram
    692
  - REF Block Diagram for Devices with a CTSD16 Module
    693
    
    Principle of Operation
    694
    
    Low-Power Operation
    695
  - REF Control of Reference System (REFMSTR = 1) (Default) for Devices with CTSD16
    696
    
    Reference System Requests
    697
  - REF Registers
    700
    
    REFCTL0 Register (Offset = 00H) [Reset = 0080H]
    701
  - Adc10_A
    703
    
    ADC10_A Introduction
    704
    
    ADC10_A Block Diagram
    705
    
    ADC10_A Operation
    706
    
    Voltage Reference Generator
    707
  - Extended Sample Mode
    708
    
    Conversion Result
    709
    
    Single-Channel Single-Conversion Mode
    710
    
    Sequence-Of-Channels Mode
    711
    
    Repeat-Single-Channel Mode
    712
    
    Repeat-Sequence-Of-Channels Mode
    713
    
    Window Comparator
    714
    
    Using the Integrated Temperature Sensor
    715
  - ADC10_A Grounding and Noise Considerations
    716
    
    ADC10_A Registers
    718
  - ADC10CTL0 Register
    719
  - ADC10CTL1 Register
    720
  - ADC10CTL2 Register
    722
  - ADC10MEM0 Register
    723
  - ADC10MCTL0 Register
    724
  - ADC10HI Register
    725
  - ADC10LO Register
    726
  - ADC10IE Register
    727
  - ADC10IFG Register
    728
  - ADC10IV Register
    729
  - Adc12_A
    730
    
    ADC12_A Introduction
    731
  - ADC12_A Block Diagram (Devices with REF Module)
    732
  - ADC12_A Msp430F54Xx (Non-A) Block Diagram
    733
    
    ADC12_A Operation
    734
    
    Voltage Reference Generator
    735
    
    Auto Power down
    736
  - Pulse Sample Mode
    737
    
    Conversion Memory
    738
  - Single-Channel Single-Conversion Mode
    739
  - Sequence-Of-Channels Mode
    740
  - Repeat-Single-Channel Mode
    741
  - Repeat-Sequence-Of-Channels Mode
    742
    
    Using the Integrated Temperature Sensor
    744
    
    ADC12_A Grounding and Noise Considerations
    745
    
    ADC12_A Interrupts
    746
  - ADC12_A Registers
    748
  - ADC12CTL0 Register
    750
  - ADC12CTL1 Register
    752
  - ADC12CTL2 Register
    753
  - Adc12Memx Register
    754
  - Adc12Mctlx Register
    755
  - ADC12IE Register
    756
  - ADC12IFG Register
    758
  - ADC12IV Register
    760
  - Sd24_B
    761
    
    SD24_B Introduction
    762
    
    SD24_B Overview Block Diagram
    763
  - SD24_B Reference and Clock Generation Block Diagram
    764
  - SD24_B Converter Block Diagram
    765
    
    SD24_B Operation
    766
    
    Voltage Reference
    767
    
    Digital Filter
    768
  - Comb Filter's Frequency Response with OSR = 32
    769
  - Digital Filter Step Response and Conversion Points Digital Filter Output
    770
  - Offset Binary Left Aligned Mapping
    771
    
    Bitstream Input and Output
    772
  - Single Conversion Examples
    773
    
    Conversion Operation Using Preload
    774
    
    Grounding and Noise Considerations
    775
    
    Trigger Generator
    776
    
    SD24_B Interrupts
    777
    
    SD24_B Registers
    778
  - SD24BCTL0 Register
    780
  - SD24BCTL1 Register
    781
  - SD24BTRGCTL Register
    782
  - SD24BIFG Register
    783
  - SD24BIE Register
    786
  - SD24BIV Register
    788
  - Sd24Bcctlx Register
    789
  - Sd24Binctlx Register
    791
  - Sd24Bosrx Register
    792
  - Sd24Bprex Register
    793
  - Sd24Bmemlx Register Description
    794
  - Sd24Bmemhx Register Description
    794
  - Ctsd16
    795
    
    CTSD16 Introduction
    796
    
    CTSD16 Block Diagram
    797
    
    CTSD16 Operation
    798
  - Voltage Reference Signal Selection Requirements
    799
    
    Analog Inputs
    800
  - Digital Filter
    801
  - Comb Filter Frequency Response with OSR = 32
    802
  - Used Bits of Digital Filter Output
    803
  - Data Format
    804
    
    Conversion Memory Registers: Ctsd16Memx
    804
  - Conversion Mode Summary
    805
  - Grouped Channel Operation Example
    806
    
    Conversion Operation Using Preload
    807
    
    Using the Integrated Temperature Sensor
    808
    
    Using the Integrated AVCC Sense
    809
  - CTSD16 Registers
    811
  - CTSD16CTL Register Description
    812
  - CTSD16CCTL0 to CTSD16CCTL6 Register Description
    813
  - CTSD16MEM0 to CTSD16MEM6 Register Description
    814
  - CTSD16INCTL0 to CTSD16INCTL6 Register Description
    815
  - CTSD16PRE0 to CTSD16PRE6 Register Description
    816
  - CTSD16IFG Register Description
    817
  - CTSD16IE Register Description
    819
  - CTSD16IV Register Description
    821
  - Dac12_A
    822
    
    DAC12_A Introduction
    823
    
    DAC12_A Block Diagram for a Device with Two Modules
    824
  - DAC12_A Block Diagram for a Device with One Module
    825
  - Eeref+ Eref+ Erefbg
    826
  - Or VREF+ or
    826
  - Or VREFBG
    826
    
    DAC12_A Operation
    826
  - Dac12Srefx = {2,3} Signal Selection Requirements for Devices with a CTSD16 Module
    827
    
    Updating the DAC12_A Voltage Output
    827
    
    DAC12_A Output Amplifier Offset Calibration
    828
    
    Grouping Multiple DAC12_A Modules
    829
    
    DAC12_A Interrupts
    830
  - DAC Output Selection
    831
  - DAC12_A Registers
    832
  - Dac12_Xctl0 Register Description
    833
  - Dac12_Xctl1 Register Description
    835
  - Dac12_Xdat Register Description
    836
    
    Dac12_Xdat Register, Unsigned 12-Bit Binary Format, Right Justified
    836
  - Dac12_Xdat Register Description
    837
    
    Dac12_Xdat Register, Twos-Complement 12-Bit Binary Format, Right Justified
    837
  - Dac12_Xdat Register Description
    838
    
    Dac12_Xdat Register, Unsigned 8-Bit Binary Format, Right Justified
    838
  - Dac12_Xdat Register Description
    839
    
    Dac12_Xdat Register, Twos-Complement 8-Bit Binary Format, Right Justified
    839
  - Dac12_Xcalctl Register Description
    840
  - Dac12_Xcaldat Register Description
    840
  - DAC12IV Register Description
    841
- Comparator B (Comp_B)
  
  842
  - Comp_B Introduction
    843
  - Comp_B Operation
    844
    
    Output Filter
    845
    
    Reference Voltage Generator
    846
    
    Comp_B Port Disable Register CBCTL3
    847
  - Temperature Measurement System
    848
  - Comp_B Registers
    850
  - CBCTL0 Register Description
    851
  - CBCTL1 Register Description
    852
  - CBCTL2 Register Description
    853
  - CBCTL3 Register Description
    854
  - CBINT Register Description
    856
  - CBIV Register Description
    857
- Operational Amplifier (OA)
  
  858
  - OA Introduction
    859
  - OA Block Diagram
    860
  - OA Mode Select
    861
    
    OA Operation
    861
    
    Ground Switches
    862
  - OA Registers
    863
  - Oanctl0 Register Description
    864
  - Oanpsw Register Description
    865
  - Oannsw Register Description
    866
  - Oangsw Register Description
    867
- LCD_B Controller
  
  868
  - LCD_B Controller Introduction
    869
  - LCD_B Controller Block Diagram
    870
    
    LCD_B Controller Operation
    871
    
    Blanking the LCD
    872
    
    LCD_B Voltage and Bias Generation
    873
  - Bias Generation
    874
  - LCD Voltage and Biasing Characteristics
    875
    
    LCD Outputs
    875
    
    Static Mode
    877
  - Static LCD Example (MAB Addresses Need to be Replaced with Lcdmx)
    878
    
    Mux Mode
    880
  - Mux LCD Example (MAB Addresses Need to be Replaced with Lcdmx)
    881
    
    Mux Mode
    883
  - Mux LCD Example (MAB Addresses Need to be Replaced with Lcdmx)
    884
    
    Mux Mode
    886
  - Mux LCD Example (MAB Addresses Need to be Replaced with Lcdmx)
    887
  - LCD_B Registers
    889
  - LCD_B Memory Registers
    890
  - LCD_B Blinking Memory Registers
    891
  - LCDBCTL0 Register Description
    892
  - LCDBCTL1 Register
    893
  - LCDBBLKCTL Register
    894
  - LCDBMEMCTL Register
    895
  - LCDBVCTL Register
    896
  - LCDBPCTL0 Register
    898
  - LCDBPCTL2 Register
    899
  - LCDBCPCTL Register
    900
  - LCDBIV Register
    901
- LCD_C Controller
  
  902
  - LCD_C Introduction
    903
  - LCD Controller Block Diagram
    904
    
    LCD_C Operation
    905
    
    LCD Timing Generation
    906
    
    Blanking the LCD
    907
    
    LCD Voltage and Bias Generation
    908
  - Bias Generation
    909
  - Bias Voltages and External Pins
    910
    
    LCD Outputs
    911
    
    LCD Interrupts
    912
    
    Static Mode
    914
    
    Mux Mode
    915
    
    Mux Mode
    916
    
    Mux Mode
    917
    
    Mux Mode
    918
    
    Mux Mode
    919
  - Example 8-Mux, 1/3 Bias Low-Power Waveforms (LCDLP = 1)
    920
    
    LCD_C Registers
    921
  - LCD_C Memory Registers for Static and 2-Mux to 4-Mux Modes
    922
  - LCD Blinking Memory Registers for Static and 2-Mux to 4-Mux Modes
    923
  - LCD Memory Registers for 5-Mux to 8-Mux
    924
  - LCDCCTL0 Register
    926
  - LCDCCTL1 Register
    928
  - LCDCBLKCTL Register
    929
  - LCDCMEMCTL Register
    930
  - LCDCVCTL Register
    931
  - LCDCPCTL0 Register
    933
  - LCDCPCTL2 Register
    934
  - LCDCCPCTL Register
    935
- Universal Serial Communication Interface – UART Mode
  
  936
  - Universal Serial Communication Interface (USCI) Overview
    937
  - USCI Introduction – UART Mode
    938
  - Usci_Ax Block Diagram – UART Mode (UCSYNC = 0)
    939
    
    USCI Operation – UART Mode
    940
  - Idle-Line Format
    941
  - Address-Bit Multiprocessor Format
    942
    
    Automatic Baud-Rate Detection
    943
    
    Irda Encoding and Decoding
    945
    
    Automatic Error Detection
    946
    
    USCI Receive Enable
    947
    
    UART Baud-Rate Generation
    948
  - BITCLK16 Modulation Pattern
    949
    
    Setting a Baud Rate
    950
    
    Receive Bit Timing
    951
    
    Typical Baud Rates and Errors
    952
  - Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 1
    954
    
    Using the USCI Module in UART Mode with Low-Power Modes
    955
    
    DMA Operation
    956
  - USCI_A UART Mode Registers
    957
  - Ucaxctl0 Register
    958
  - Ucaxctl1 Register
    959
  - Ucaxbr0 Register
    960
  - Ucaxstat Register
    961
  - Ucaxrxbuf Register
    962
  - Ucaxirtctl Register
    963
    
    Ucaxabctl Register
    964
    
    Ucaxie Register
    965
    
    Ucaxiv Register
    966
- Universal Serial Communication Interface – SPI Mode
  
  967
  - Universal Serial Communication Interface (USCI) Overview
    968
  - USCI Introduction – SPI Mode
    969
  - USCI Block Diagram – SPI Mode
    970
    
    USCI Operation – SPI Mode
    971
    
    Master Mode
    972
    
    Slave Mode
    973
    
    SPI Enable
    974
    
    Using the SPI Mode with Low-Power Modes
    975
    
    USCI Interrupts in SPI Mode
    976
  - USCI_A SPI Mode Registers
    977
  - Ucaxctl0 Register
    978
  - Ucaxctl1 Register
    979
  - Ucaxbr0 Register
    980
    
    Ucaxstat Register
    981
    
    Ucaxrxbuf Register
    982
    
    Ucaxtxbuf Register
    982
    
    Ucaxie Register
    983
    
    Ucaxifg Register
    983
    
    Ucaxiv Register 37.5 USCI_B SPI Mode Registers
    985
    
    Ucbxctl0 Register
    986
    
    Ucbxctl1 Register
    987
    
    Ucbxbr0 Register
    988
    
    Ucbxbr1 Register
    988
    
    Ucbxmctl Register
    988
    
    Ucbxstat Register
    989
    
    Ucbxrxbuf Register
    990
    
    Ucbxtxbuf Register
    990
    
    Ucbxie Register
    991
    
    Ucbxifg Register
    991
    
    Ucbxiv Register
    992
- Universal Serial Communication Interface - I 2 C Mode
  
  993
  - Universal Serial Communication Interface (USCI) Overview
    994
  - USCI Introduction - I C Mode
    995
  - USCI Operation - I C Mode
    996
    
    USCI Block Diagram – I 2 C Mode
    996
    
    C Serial Data
    997
    
    USCI Initialization and Reset
    997
    
    C Addressing Modes
    999
    
    I 2 C Slave 10-Bit Addressing Mode
    999
    
    C Module Operating Modes
    1000
    
    Arbitration Procedure between Two Master Transmitters
    1010
    
    C Clock Generation and Synchronization
    1011
    
    USCI Interrupts in I C Mode
    1012
    
    Using the USCI Module in I C Mode with Low-Power Modes
    1012
  - USCI_B I2C Mode Registers
    1015
    
    Ucbxctl0 Register
    1016
    
    Ucbxctl1 Register
    1017
    
    Ucbxbr0 Register
    1018
    
    Ucbxbr1 Register
    1018
    
    Ucbxstat Register
    1019
    
    Ucbxrxbuf Register
    1020
    
    Ucbxtxbuf Register
    1020
    
    Ucbxi2Coa Register
    1021
    
    Ucbxi2Csa Register
    1021
    
    Ucbxie Register
    1022
    
    Ucbxifg Register
    1023
    
    Ucbxiv Register
    1024
- Enhanced Universal Serial Communication Interface (Eusci) - UART Mode
  
  1025
  - Enhanced Universal Serial Communication Interface a (Eusci_A) Overview
    1026
  - Eusci_A Introduction - UART Mode
    1026
  - Eusci_Ax Block Diagram – UART Mode (UCSYNC = 0)
    1027
    
    Asynchronous Communication Format
    1028
    
    Character Format
    1028
    
    Eusci_A Initialization and Reset
    1028
    
    Eusci_A Operation - UART Mode
    1028
    
    Idle-Line Format
    1029
    
    Address-Bit Multiprocessor Format
    1030
    
    Automatic Baud-Rate Detection
    1031
    
    Irda Encoding and Decoding
    1032
    
    Automatic Error Detection
    1033
    
    Eusci_A Receive Enable
    1034
    
    UART Baud-Rate Generation
    1035
    
    BITCLK16 Modulation Pattern
    1036
    
    Setting a Baud Rate
    1037
    
    Transmit Bit Timing - Error Calculation
    1038
    
    Typical Baud Rates and Errors
    1039
  - Recommended Settings for Typical Crystals and Baud Rates
    1040
    
    Using the Eusci_A Module in UART Mode with Low-Power Modes
    1041
    
    Eusci_A Interrupts in UART Mode
    1042
    
    DMA Operation
    1043
  - Eusci_A UART Registers
    1044
  - Ucaxctlw0 Register
    1045
  - Ucaxctlw1 Register
    1046
  - Ucaxbrw Register
    1047
  - Ucaxstatw Register
    1048
  - Ucaxrxbuf Register
    1049
  - Ucaxabctl Register
    1050
  - Ucaxirctl Register
    1051
  - Ucaxie Register
    1052
  - Ucaxifg Register
    1053
  - Ucaxiv Register
    1054
  - SLAU208Q - June 2008 - Revised March 2018
    1055
- Enhanced Universal Serial Communication Interface (Eusci) – SPI Mode
  
  1055
  - Enhanced Universal Serial Communication Interfaces (Eusci_A, Eusci_B) Overview
    1056
  - Eusci Block Diagram – SPI Mode
    1057
    
    Eusci Operation – SPI Mode
    1058
    
    Character Format
    1059
    
    Slave Mode
    1060
    
    SPI Enable
    1061
    
    Using the SPI Mode with Low-Power Modes
    1062
  - Eusci_A SPI Registers
    1064
  - Ucaxctlw0 Register
    1065
  - Ucaxbrw Register
    1066
  - Ucaxstatw Register
    1067
  - Ucaxrxbuf Register
    1068
    
    Ucaxtxbuf Register
    1069
  - Ucaxie Register
    1070
  - Ucaxifg Register
    1071
  - Ucaxiv Register
    1072
  - Eusci_B SPI Registers
    1073
  - Ucbxctlw0 Register
    1074
    
    Ucbxbrw Register
    1075
    
    Ucbxrxbuf Register
    1076
    
    Ucbxie Register
    1077
    
    Ucbxiv Register
    1078
    
    Enhanced Universal Serial Communication Interface (Eusci) – I 2 C Mode
    1080
    
    Eusci_B Block Diagram – I 2 C Mode
    1081
    
    Eusci_B Initialization and Reset
    1082
    
    I 2 C Slave 10-Bit Addressing Mode
    1083
  - I 2 C Slave 10-Bit Addressing Mode
    1089
  - I 2 C Master Transmitter Mode
    1091
  - I 2 C Master Receiver Mode
    1093
  - I 2 C Master 10-Bit Addressing Mode
    1094
  - Arbitration Procedure between Two Master Transmitters
    1094
  - Clock Generators During Arbitration
    1095
    
    Glitch Filtering
    1095
    
    Byte Counter
    1097
    
    Copyright © 2008-2018, Texas Instruments Incorporated
    1097
    
    Multiple Slave Addresses
    1097
    
    Eusci_B Interrupts in I
    1098
    
    Mode with Low-Power Modes
    1098
    
    Using the Eusci_B Module in I
    1098
    
    Eusci_B I2C Registers
    1102
    
    Ucbxctlw0 Register
    1103
  - Ucbxctlw1 Register
    1105
    
    Ucbxstatw
    1107
  - Ucbxbrw Register
    1107
  - Ucbxstatw Register
    1107
  - Ucbxtbcnt Register
    1108
    
    Ucbxtxbuf
    1109
  - Ucbxrxbuf Register
    1109
  - Ucbxtxbuf Register
    1109
  - Ucbxi2Coa0 Register
    1110
  - Ucbxi2Coa1 Register
    1111
  - Ucbxi2Coa2 Register
    1111
  - Ucbxi2Coa3 Register
    1112
  - Ucbxaddrx Register
    1112
  - Ucbxaddmask Register
    1113
  - Ucbxi2Csa Register
    1113
  - Ucbxie Register
    1114
  - Ucbxifg Register
    1116
  - Ucbxiv Register
    1118
- USB Module
  
  1119
  - USB Introduction
    1120
  - USB Block Diagram
    1121
    
    USB Operation
    1122
    
    USB Transceiver (PHY)
    1122
  - USB Power System
    1123
  - USB Power up and down Profile
    1124
  - Powering Entire MSP430 from VBUS
    1125
    
    USB Phase-Locked Loop (PLL)
    1126
  - USB-PLL Analog Block Diagram
    1126
  - USB-PLL Pre-Scale Divider
    1127
    
    USB Controller Engine
    1128
  - Data Buffers and Descriptors
    1129
  - USB Buffer Memory Map
    1130
  - USB Timer and Time Stamp Generation
    1131
    
    Power Consumption
    1132
    
    USB Vector Interrupts
    1132
    
    Control Transfers
    1133
    
    Suspend and Resume
    1133
    
    USB Transfers
    1133
    
    Interrupt Transfers
    1137
    
    Bulk Transfers
    1138
    
    USB Configuration Registers
    1140
    
    USB Registers
    1140
  - USBKEYPID Register
    1141
  - USBCNF Register
    1141
  - USBPHYCTL Register
    1142
  - USBPWRCTL Register
    1143
  - USBPLLCTL Register
    1145
  - USBPLLDIVB Register
    1146
  - USBPLLIR Register
    1147
    
    USB Control Registers
    1148
  - USBIEPCNF_0 Register
    1149
  - USBIEPBCNT_0 Register
    1150
  - USBOEPCNFG_0 Register
    1151
  - USBOEPBCNT_0 Register
    1152
  - USBIEPIE Register
    1153
  - USBOEPIE Register
    1155
  - USBIEPIFG Register
    1157
  - USBOEPIFG Register
    1158
  - USBVECINT Register
    1159
  - USBMAINT Register
    1160
  - USBTSREG Register
    1161
  - USBFN Register
    1161
  - USBCTL Register
    1162
  - USBIE Register
    1163
  - USBIFG Register
    1164
  - USBFUNADR Register
    1164
    
    USB Buffer Registers and Memory
    1165
  - Usboepcnf_N Register
    1168
  - Usboepbbax_N Register
    1169
  - Usboepbctx_N Register
    1170
  - Usboepbbay_N Register
    1170
  - Usboepbcty_N Register
    1171
  - Usboepsizxy_N Register
    1171
  - Usbiepcnf_N Register
    1172
  - Usbiepbbax_N Register
    1173
  - Usbiepbctx_N Register
    1174
  - Usbiepbbay_N Register
    1174
  - Usbiepbcty_N Register
    1175
  - Usbiepsizxy_N Register
    1175
- LDO-PWR Module
  
  1176
  - LDO-PWR Introduction
    1177
  - LDO Block Diagram
    1177
    
    Enabling/Disabling
    1178
    
    LDO-PWR Operation
    1178
    
    Powering the Rest of the MSP430 from the LDO-PWR
    1178
  - V LDO Power Up/Down Profile
    1178
    
    Applications that Do Not Require LDO-PWR
    1179
    
    Current Limitation and Overload Protection
    1179
    
    Powering Other Components in the System from LDO-PWR
    1179
  - Powering Entire MSP430 from LDOI
    1179
    
    LDO-PWR Interrupts
    1180
    
    Port U Control
    1180
    
    LDO-PWR Registers
    1181
    
    PUCTL Register
    1182
  - LDOKEYPID Register
    1182
    
    LDOPWRCTL Register
    1183
- Embedded Emulation Module (EEM)
  
  1184
  - Embedded Emulation Module (EEM) Introduction
    1185
  - Large Implementation of EEM
    1186
    
    EEM Building Blocks
    1187
    
    State Storage (Internal Trace Buffer)
    1187
    
    Trigger Sequencer
    1187
    
    Triggers
    1187
  - EEM Configurations
    1188
- Revision History
  
  1189

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Motherboard Control Unit Microcontrollers Computer Hardware Calculator

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Texas Instruments MSP430x6 series Manuals

Texas Instruments MSP430x6 series User Manual (1190 pages)

Table of Contents

Msp430X5Xx and Msp430X6Xx Family User's Guide

Table of Contents

Preface

System Resets, Interrupts, and Operating Modes, System Control Module (SYS)

Power Management Module and Supply Voltage Supervisor

Battery Backup System

Auxiliary Supply System (AUX)

Unified Clock System (UCS)

Cpux

Flash Memory Controller

Memory Integrity Detection (MID)

RAM Controller (RAMCTL)

Backup RAM

Direct Memory Access (DMA) Controller Module

Digital I/O Module

Port Mapping Controller

Cyclic Redundancy Check (CRC) Module

AES Accelerator

Watchdog Timer (WDT_A)

Timer_A

Timer_B

Timer Event Control (TEC)

Real-Time Clock (RTC) Overview

Real-Time Clock (RTC_A)

Real-Time Clock B (RTC_B)

Real-Time Clock C (RTC_C)

Bit Hardware Multiplier (MPY32)

Comparator B (Comp_B)

Operational Amplifier (OA)

LCD_B Controller

LCD_C Controller

Universal Serial Communication Interface – UART Mode

Universal Serial Communication Interface – SPI Mode

Universal Serial Communication Interface - I 2 C Mode

Enhanced Universal Serial Communication Interface (Eusci) - UART Mode

Enhanced Universal Serial Communication Interface (Eusci) – SPI Mode

USB Module

LDO-PWR Module

Embedded Emulation Module (EEM)

Revision History

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