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Texas Instruments MSP430x5 series User Manual

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MSP430x5xx and MSP430x6xx Family

User's Guide

Literature Number: SLAU208Q

June 2008 – Revised March 2018

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Page 1 MSP430x5xx and MSP430x6xx Family User's Guide Literature Number: SLAU208Q June 2008 – Revised March 2018...
Page 2: Table Of Contents
1.14.1 SFRIE1 Register ....................1.14.2 SFRIFG1 Register ....................1.14.3 SFRRPCR Register ......................1.15 SYS Registers ....................1.15.1 SYSCTL Register ....................1.15.2 SYSBSLC Register Contents SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 3 Switching Control ................. 4.2.3 Software-Controlled Switching ................4.2.4 Hardware-Controlled Switching ..........4.2.5 Interactions Among f , SVM , and AUXxLVL CORE DSYS SLAU208Q – June 2008 – Revised March 2018 Contents Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 4 ..........................CPUX ................... MSP430X CPU (CPUX) Introduction ........................Interrupts ......................CPU Registers ..................6.3.1 Program Counter (PC) ....................6.3.2 Stack Pointer (SP) Contents SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 5 MidGetErrAdr() Function ..................8.6.4 MidCheckMem() Function ................... 8.6.5 MidSetRaw() Function ..................8.6.6 MidGetParity() Function ..................8.6.7 MidCalcVParity() Function ..................User's UNMI Interrupt Handler SLAU208Q – June 2008 – Revised March 2018 Contents Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 6 Digital I/O Registers ....................12.4.1 P1IV Register ....................12.4.2 P2IV Register ....................12.4.3 P1IES Register ....................12.4.4 P1IE Register ....................12.4.5 P1IFG Register Contents SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 7 16.2.1 Watchdog Timer Counter (WDTCNT) ....................16.2.2 Watchdog Mode .................... 16.2.3 Interval Timer Mode ..................16.2.4 Watchdog Timer Interrupts ..................16.2.5 Clock Fail-Safe Feature SLAU208Q – June 2008 – Revised March 2018 Contents Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 8 19.2.8 Switching From Capture to Compare Mode ...................... 19.2.9 Output Unit ............19.2.10 Synchronization Between Timer_D Instances .................... 19.2.11 Timer_D Interrupts ......................19.3 Timer_D Registers Contents SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 9 22.3.13 RTCHOUR Register – Calendar Mode With Hexadecimal Format ..........22.3.14 RTCHOUR Register – Calendar Mode With BCD Format ..............22.3.15 RTCDOW Register – Calendar Mode SLAU208Q – June 2008 – Revised March 2018 Contents Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 10 23.3.20 RTCAHOUR Register – Hexadecimal Format ..............23.3.21 RTCAHOUR Register – BCD Format ..................23.3.22 RTCADOW Register ............... 23.3.23 RTCADAY Register – Hexadecimal Format Contents SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 11 24.4.27 RTCAHOUR Register – Calendar Mode With BCD Format ..............24.4.28 RTCADOW Register – Calendar Mode ........24.4.29 RTCADAY Register – Calendar Mode With Hexadecimal Format SLAU208Q – June 2008 – Revised March 2018 Contents Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 12 27.2.2 ADC10_A Inputs and Multiplexer ................. 27.2.3 Voltage Reference Generator ....................27.2.4 Auto Power Down ................27.2.5 Sample and Conversion Timing ....................27.2.6 Conversion Result Contents SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 13 ....................29.2.5 Auto Power-Down ....................29.2.6 Analog Inputs ..................... 29.2.7 Digital Filter ..................29.2.8 Bitstream Input and Output ....................29.2.9 Conversion Modes SLAU208Q – June 2008 – Revised March 2018 Contents Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 14 DAC12_A Operation ....................31.2.1 DAC12_A Core ..................31.2.2 DAC12_A Port Selection ................... 31.2.3 DAC12_A Reference ..............31.2.4 Updating the DAC12_A Voltage Output Contents SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 15 33.5 OA Registers ..................... 33.5.1 OAnCTL0 Register ....................33.5.2 OAnPSW Register ....................33.5.3 OAnNSW Register ..................... 33.5.4 OAnGSW Register ......................LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Contents Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 16 35.3.6 LCDCPCTL0 Register ..................35.3.7 LCDCPCTL1 Register ..................35.3.8 LCDCPCTL2 Register ..................35.3.9 LCDCPCTL3 Register ..................35.3.10 LCDCCPCTL Register ....................35.3.11 LCDCIV Register Contents SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 17 USCI_A SPI Mode Registers .................... 37.4.1 UCAxCTL0 Register .................... 37.4.2 UCAxCTL1 Register ..................... 37.4.3 UCAxBR0 Register ..................... 37.4.4 UCAxBR1 Register ................... 37.4.5 UCAxMCTL Register SLAU208Q – June 2008 – Revised March 2018 Contents Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 18 39.3.4 Automatic Baud-Rate Detection 1031 ................39.3.5 IrDA Encoding and Decoding 1032 ..................39.3.6 Automatic Error Detection 1033 ..................39.3.7 eUSCI_A Receive Enable 1034 Contents SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 19 .................... 40.5.7 UCBxIFG Register 1077 ....................40.5.8 UCBxIV Register 1078 ......Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode 1079 SLAU208Q – June 2008 – Revised March 2018 Contents Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 20 ................. 42.4.3 USB Buffer Registers and Memory 1165 ......................LDO-PWR Module 1176 ....................43.1 LDO-PWR Introduction 1177 ....................43.2 LDO-PWR Operation 1178 Contents SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 21 44.2.3 State Storage (Internal Trace Buffer) 1187 ....................44.2.4 Cycle Counter 1187 ....................44.2.5 Clock Control 1187 ..................... 44.3 EEM Configurations 1188 ........................Revision History 1189 SLAU208Q – June 2008 – Revised March 2018 Contents Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 22 Available AUXxLVL Settings vs SVM Settings ................4-5. Auxiliary Supply Monitor Block Diagram ..................4-6. I/Os Powered by Auxiliary Supplies List of Figures SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 23 6-20. Symbolic Mode Running in Upper Memory ................6-21. Overflow and Underflow for Symbolic Mode ................. 6-22. MSP430 Double-Operand Instruction Format SLAU208Q – June 2008 – Revised March 2018 List of Figures Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 24 Initiating a Byte or Word Write From RAM ................7-9. Initiating Long-Word Write From Flash .................. 7-10. Initiating Long-Word Write from RAM ....................7-11. Block-Write Cycle Timing List of Figures SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 25 14-2. Implementation of CRC-CCITT Using the CRCDI and CRCINIRES Registers ......................14-3. CRCDI Register ....................... 14-4. CRCDIRB Register ..................... 14-5. CRCINIRES Register ...................... 14-6. CRCRESR Register SLAU208Q – June 2008 – Revised March 2018 List of Figures Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 26 18-13. Output Example – Timer in Continuous Mode ................18-14. Output Example – Timer in Up/Down Mode ................18-15. Capture/Compare TBxCCR0 Interrupt Flag ......................18-16. TBxCTL Register List of Figures SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 27 ...................... 20-6. TECxCTL0 Register ...................... 20-7. TECxCTL1 Register ...................... 20-8. TECxCTL2 Register ....................... 20-9. TECxSTA Register ......................20-10. TECxINT Register SLAU208Q – June 2008 – Revised March 2018 List of Figures Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 28 ......................23-8. RTCMIN Register ......................23-9. RTCMIN Register ...................... 23-10. RTCHOUR Register ...................... 23-11. RTCHOUR Register ....................... 23-12. RTCDOW Register List of Figures SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 29 ....................... 24-25. RTCYEAR Register ....................... 24-26. RTCYEAR Register ....................... 24-27. RTCAMIN Register ....................... 24-28. RTCAMIN Register ....................24-29. RTCAHOUR Register SLAU208Q – June 2008 – Revised March 2018 List of Figures Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 30 27-10. Typical Temperature Sensor Transfer Function ..............27-11. ADC10_A Grounding and Noise Considerations ....................27-12. ADC10CTL0 Register ....................27-13. ADC10CTL1 Register ....................27-14. ADC10CTL2 Register List of Figures SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 31 29-15. SD24_B Trigger Generator Block Diagram ....................29-16. SD24BCTL0 Register ....................29-17. SD24BCTL1 Register ....................29-18. SD24BTRGCTL Register ...................... 29-19. SD24BIFG Register SLAU208Q – June 2008 – Revised March 2018 List of Figures Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 32 ....................31-14. DAC12_xDAT Register ....................31-15. DAC12_xDAT Register ....................31-16. DAC12_xDAT Register ....................31-17. DAC12_xDAT Register ....................31-18. DAC12_xCALCTL Register List of Figures SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 33 35-3. LCD Memory for 5-Mux to 8-Mux Mode - Example for 160 Segments ......................35-4. Bias Generation ....................35-5. Example Static Waveforms ..................... 35-6. Example 2-Mux Waveforms ..................... 35-7. Example 3-Mux Waveforms SLAU208Q – June 2008 – Revised March 2018 List of Figures Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 34 ...................... 37-5. UCAxCTL0 Register ...................... 37-6. UCAxCTL1 Register ....................... 37-7. UCAxBR0 Register ....................... 37-8. UCAxBR1 Register ..................... 37-9. UCAxMCTL Register List of Figures SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 35 39-1. eUSCI_Ax Block Diagram – UART Mode (UCSYNC = 0) 1027 ......................39-2. Character Format 1028 ......................39-3. Idle-Line Format 1029 ................... 39-4. Address-Bit Multiprocessor Format 1030 SLAU208Q – June 2008 – Revised March 2018 List of Figures Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 36 C Time-Line Legend 1086 .................... 41-9. I C Slave Transmitter Mode 1087 ....................41-10. I C Slave Receiver Mode 1088 List of Figures SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 37 ....................42-23. USBVECINT Register 1159 ....................42-24. USBMAINT Register 1160 ....................42-25. USBTSREG Register 1161 ......................42-26. USBFN Register 1161 SLAU208Q – June 2008 – Revised March 2018 List of Figures Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 38 43-4. LDOKEYPID Register 1182 ......................43-5. PUCTL Register 1182 ....................43-6. LDOPWRCTL Register 1183 ..................44-1. Large Implementation of EEM 1186 List of Figures SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 39 ..................2-17. PMMCTL1 Register Description ..................2-18. SVSMHCTL Register Description ..................2-19. SVSMLCTL Register Description ................... 2-20. SVSMIO Register Description SLAU208Q – June 2008 – Revised March 2018 List of Tables Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 40 6-16. Address Instructions, Operate on 20-Bit Register Data ..............6-17. MSP430X Format II Instruction Cycles and Length ..............6-18. MSP430X Format I Instruction Cycles and Length List of Tables SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 41 13-3. Port Mapping Registers for Port Px – Byte Access ..............13-4. Port Mapping Registers for Port Px – Word Access SLAU208Q – June 2008 – Revised March 2018 List of Tables Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 42 ..................19-10. TDxCTL1 Register Description ..................19-11. TDxCTL2 Register Description ....................19-12. TDxR Register Description ..................19-13. TDxCCTLn Register Description List of Tables SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 43 ..................22-32. RTCPS0CTL Register Description ..................22-33. RTCPS1CTL Register Description .................... 22-34. RT0PS Register Description .................... 22-35. RT1PS Register Description SLAU208Q – June 2008 – Revised March 2018 List of Tables Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 44 ..................24-13. RTCNT3 Register Description ..................24-14. RTCNT4 Register Description ..................24-15. RTCSEC Register Description ..................24-16. RTCSEC Register Description List of Tables SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 45 25-6. Result Availability in Saturation Mode (MPYSAT = 1) ......................25-7. MPY32 Registers ..................... 25-8. Alternative Registers ..................25-9. MPY32CTL0 Register Description SLAU208Q – June 2008 – Revised March 2018 List of Tables Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 46 ..................29-14. SD24BOSRx Register Description ................. 29-15. SD24BTRGOSR Register Description ..................29-16. SD24BPREx Register Description ................. 29-17. SD24BTRGPRE Register Description List of Tables SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 47 ......................34-2. LCD_B Registers ....................34-3. LCD_B Memory Registers ..................34-4. LCD_B Blinking Memory Registers ..................34-5. LCDBCTL0 Register Description SLAU208Q – June 2008 – Revised March 2018 List of Tables Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 48 36-17. UCAxABCTL Register Description .................... 36-18. UCAxIE Register Description ..................36-19. UCAxIFG Register Description .................... 36-20. UCAxIV Register Description ....................... 37-1. UCxSTE Operation List of Tables SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 49 39-8. UCAxCTLW0 Register Description 1045 ................... 39-9. UCAxCTLW1 Register Description 1046 ..................39-10. UCAxBRW Register Description 1047 ................... 39-11. UCAxMCTLW Register Description 1047 SLAU208Q – June 2008 – Revised March 2018 List of Tables Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 50 .................... 42-1. USB-PLL Pre-Scale Divider 1127 ......42-2. Register Settings to Generate 48 MHz Using Common Clock Input Frequencies 1127 List of Tables SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 51 43-2. LDOKEYPID Register Description 1182 ................... 43-3. PUCTL Register Description 1182 ................... 43-4. LDOPWRCTL Register Description 1183 ..................... 44-1. EEM Configurations 1188 SLAU208Q – June 2008 – Revised March 2018 List of Tables Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 52: Preface
Program Counter; see Section 6.3.1 Power Mode; see Section 1.4 Power-on Reset; see Section 1.2 Power-up Clear; see Section 1.2 Read This First SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 53 Cleared by hardware Set by hardware -0,-1 Condition after PUC -(0),-(1) Condition after POR -[0],-[1] Condition after BOR -{0},-{1} Condition after Brownout SLAU208Q – June 2008 – Revised March 2018 Read This First Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 54: System Resets, Interrupts, And Operating Modes, System Control Module (Sys)
..................1.13 Device Descriptor Table ....................1.14 SFR Registers ....................1.15 SYS Registers System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 55: System Control Module (Sys) Introduction
NOTE: The number and type of resets available may vary from device to device. See the device- specific data sheet for all reset sources available. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 56: Bor/Por/Puc Reset Circuit
WDTIFG Watchdog Timer MCLK Module PUCs PUC Logic Figure 1-1. BOR/POR/PUC Reset Circuit System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 57: Device Initial Conditions After System Reset
See the device-specific data sheet for all interrupt sources and their priorities. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 58: Non)Maskable Interrupts (Nmis)
NOTE: The number and types of NMI sources may vary from device to device. See the device- specific data sheet for all NMI sources available. System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 59: Snmi Timing
1-4. The interrupt logic executes the following: 1. Any currently executing instruction is completed. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 60: Interrupt Processing
The rules above apply to all instructions that set or clear the general interrupt enable bit. Not following these rules might result in unexpected CPU execution. System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 61: Interrupt Nesting
(SFRs). The SFRs are located in the peripheral address range and are byte and word accessible. See the device-specific data sheet for the SFR configuration. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 62: Sys Interrupt Vector Generators
; Return JMBI_ISR: ; Vector C ; Task_C starts here RETI ; Return System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 63: Operating Modes
LPM2, LPM3, and LPM4 with the device connected to a development tool (for example, MSP-FET430UIF). See thePMM chapter for details. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 64: Operation Modes
‡ An enabled reset always restarts the device Arbitrary transitions Figure 1-6. Operation Modes System Resets, Interrupts, and Operating Modes, System Control Module (SYS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 65: Operation Modes
LPM3.5 and LPM4.5 modes are not available on all devices. See the device-specific data sheet for availability. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 66: Entering And Exiting Low-Power Modes Lpm0 Through Lpm4
; Exit LPM4 Interrupt Service Routine #CPUOFF+OSCOFF+SCG1+SCG0,0(SP) ; Exit LPM4 on RETI RETI System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 67: Entering And Exiting Low-Power Modes Lpmx.5
LPM4.5, but has the additional capability of having a RTC mode available. In addition to the wake-up events possible in LPM4.5, RTC wake-up events are also possible in LPM3.5. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 68: Extended Time In Low-Power Modes
; Program stops ; Interrupt Service Routine #CPUOFF+OSCOFF+SCG1+SCG0,0(SR) ; Exit LPM4 on RETI RETI System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 69: Principles For Low-Power Applications
If the application has low duty cycle, slow response time events, maximizing time in LPMx.5 can further reduce power consumption significantly. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 70: Connection Of Unused Pins
NMI. Upon an external NMI event, the NMIIFG is set. System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 71: Configuring Jtag Pins
PMM control registers only from the protected BSL memory. Once set, SYSPMMPE can only be cleared by a BOR event. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 72: Memory Map - Uses And Abilities
On vacant memory space, the value 03FFFh is driven on the data bus. System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 73: Vacant Memory Space
When JMBOUT0FG is reset, the JMBOUT0 is not ready to receive new data. JMBOUT1FG behaves similarly. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 74: Jmbin0 And Jmbin1 Incoming Mailbox
The complete device descriptor table and its contents can be found in the device specific data sheet. System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 75: Identifying Device Type
01A08h. See the device-specific data sheet for the complete TLV structure and what descriptors are available. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 76: Tag Values
// No TLV descriptor found with a matching d_ID_value Return a failing condition System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 77: Peripheral Discovery Descriptor
SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 78: Values For Memory Entry
Table 1-8. This is not a complete list, but shown as an example. System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 79: Peripheral Ids
This table is not a complete list of all peripheral IDs that might be available on a device, and is shown here for illustrative purposes only. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 80: Sample Peripheral Discovery Descriptor
For port pairs, Port 1 has higher priority than Port 2, Port 3 has higher priority than Port 4, and so on. System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 81: Crc Computation
// value stored at 0x1A02 CRCRESULT_MSB = CRCINIRES_H; // value stored at 0x1A03 SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 82: Calibration Values
If both gain and offset are corrected, the gain correction is done first: System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 83: Temperature Sensor Calibration For Devices With Ctsd16
CAL _ ADC _ T85 CAL _ ADC _ T30 è ø (11) SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 84: Sfr Registers
Reset Pin Control Read/write Word 0000h Section 1.14.3 SFRRPCR_L Read/write Byte SFRRPCR_H Read/write Byte System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 85: Sfrie1 Register
BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instruction 0b = Interrupts disabled 1b = Interrupts enabled SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 86: Sfrifg1 Register
WDTIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0b = No interrupt pending 1b = Interrupt pending System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 87: Sfrrpcr Register
NMI select. This bit selects the function for the RST/NMI pin. 0b = Reset function 1b = NMI function SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 88: Sys Registers
Word 0000h Section 1.15.9 SYSRSTIV Reset Vector Generator Read Word 0002h Section 1.15.10 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 89: Sysctl Register
0b = Interrupt vectors generated with end address TOP of lower 64KB of flash, FFFFh 1b = Interrupt vectors generated with end address TOP of RAM SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 90: Sysbslc Register
10b = Size: BSL segments 1, 2, and 3 11b = Size: BSL segments 0, 1, 2, and 3 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 91: Sysjmbc Register
0b = JMBI1 has no new data. 1b = JMBI1 has new data available. SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 92: Sysjmbi0 Register
JTAG mailbox incoming message high byte MSGLO JTAG mailbox incoming message low byte System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 93: Sysjmbo0 Register
JTAG mailbox outgoing message high byte MSGLO JTAG mailbox outgoing message low byte SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 94: Sysuniv Register
08h = BUSIFG interrupt pending (Not present on all devices. See device-specific datasheet) System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 95: Syssniv Register
10h = SVMLVLRIFG interrupt pending 12h = SVMHVLRIFG interrupt pending 14h = Reserved SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 96: Sysrstiv Register
20h = PMM password violation (PUC) 22h to 3Eh = Reserved Reset value depends on reset source. System Resets, Interrupts, and Operating Modes, System Control Module SLAU208Q – June 2008 – Revised March 2018 (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 97: Sysberriv Register
04h = Reserved for future extensions 06h = Reserved for future extensions 08h = Reserved for future extensions SLAU208Q – June 2008 – Revised March 2018 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 98: Power Management Module And Supply Voltage Supervisor
Supply Voltage Supervisor (SVS)..........................Topic Page ............ Power Management Module (PMM) Introduction ....................PMM Operation ....................PMM Registers Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 99: Power Management Module (Pmm) Introduction
The numbers within the fields denote the supported PMMCOREVx settings. Figure 2-1. System Frequency, Supply Voltage, and Core Voltage – See Device-Specific Data Sheet SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 100: Pmm Block Diagram
Regulator CORE To reset logic Reference To reset logic Ports ON Figure 2-2. PMM Block Diagram Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 101: Pmm Operation
– Detection of correct internal voltage levels when changing (especially increasing) the core voltage level before changing, for example, to higher system frequencies (also see Section 2.2.4). SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 102: Svs And Svm Thresholds
DVCC SVSHRVL[1:0] Sets SVS PMMCOREV[1:0] H_IT+ (MHz) Sets SVS Level H_IT- Levels >1.8 >2.0 >2.2 >2.4 Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 103: Available Svm H Settings Versus Vcore Settings
SVSHRVL. Thus you must select a SVSMHRRL setting that is equal to or larger than the SVSHRVL setting. SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 104: High-Side And Low-Side Voltage Failure And Resulting Pmm Actions
Set SVMLVLRIFG Set SVSLIFG Time Figure 2-4. High-Side and Low-Side Voltage Failure and Resulting PMM Actions Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 105: High-Side Svs And Svm
If the SVSMHDLYIE (SVS delay expired interrupt enable) is set when this occurs, an interrupt is also generated. SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 106: Low-Side Svs And Svm
SVMLVLRIE (SVM voltage level reached interrupt enable) is set when this occurs, an interrupt is also generated. Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 107: Supply Voltage Supervisor And Monitor - Power Up
MCLK. Figure 2-8 shows CORE this procedure. SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 108: Core And Svml And Svsl Levels
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level; // Lock PMM registers for write access PMMCTL0_H = 0x00; Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 109: For Power Optimization
SVS is enabled and a brownout condition occurs. It sustains this reset until the input power is sufficient for the logic, for proper reset of the system. SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 110: Svs And Svm Performance Modes And Wake-Up Times
Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 111: Svs L And Svml
SVMLE SVMLFP State State LPM2, LPM3, LPM4 WAKE-UP-FAST Normal Normal WAKE-UP-SLOW Full performance Full performance WAKE-UP-FAST SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 112: H And Svmh Control Mode Selection
LPM2, LPM3, and LPM4 with the device connected to a development tool (for example, MSP-FET430UIF). Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 113: Pmm Interrupts
If SVMOUTPOL is set, the output is set to 1 if an enabled interrupt flag is set. SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 114: Pmm Registers
Power mode 5 control register 0 Read/write Word 0000h Section 2.3.8 PM5CTL0_L Read/write Byte PM5CTL0_H Read/write Byte Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 115: Pmmctl0 Register
00b = V(CORE) level 0 01b = V(CORE) level 1 10b = V(CORE) level 2 11b = V(CORE) level 3 SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 116: Pmmctl1 Register
Reserved. Must always be written with 0. Reserved Reserved. Always reads as 0. Reserved Reserved. Must always be written with 0. Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 117: Svsmhctl Register
The voltage levels are defined in the device-specific data sheet. Note: SVSMHRRL must always be equal or larger than SVSHRVL. SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 118: Svsmlctl Register
SVSL. It is also used for the SVML to define the voltage reached level. Note: SVSMLRRL must always be equal or larger than SVSLRVL. Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 119: Svsmio Register
SVMOUT pin. The device-specific port logic has to be configured accordingly. Reserved Reserved. Always reads as 0. SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 120: Pmmifg Register
SVM high-side interrupt flag. The bit is cleared by software. 0b = No interrupt pending 1b = Interrupt pending Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 121 The bit is cleared by software or by reading the interrupt vector word. 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 122: Pmmrie Register
SVM low-side interrupt enable. This bit is cleared by software or if the interrupt vector word is read. SVSMLDLYIE SVS and SVM low-side delay expired interrupt enable Power Management Module and Supply Voltage Supervisor SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 123: Pm5Ctl0 Register
1b = I/O pin configuration remains locked. Pin state is held during LPMx.5 entry and exit. SLAU208Q – June 2008 – Revised March 2018 Power Management Module and Supply Voltage Supervisor Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 124: Battery Backup System
........................... Topic Page ................Battery Backup Introduction ................. Battery Backup Operation .................. Battery Backup Registers Battery Backup System SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 125: Battery Backup Introduction
If the backup-supplied subsystem is powered by the primary supply DVCC and LOCKBAK = 0, the modules located in the subsystem can be access and controlled normally. SLAU208Q – June 2008 – Revised March 2018 Battery Backup System Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 126: Activate Access To Backup-Supplied Subsystem
If LOCKBAK = 1, the supply for the backup-supplied subsystem has not settled yet. Continue with step 4. Enable RTC interrupts. 5. The enabled RTC interrupts will now be serviced as normal interrupts. Battery Backup System SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 127: Manual Switching
(that is, the time without any primary supply). SLAU208Q – June 2008 – Revised March 2018 Battery Backup System Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 128: Resistive Charger
2.7-V limit only once during each VLO clock cycle, and only then is charging disabled or re-enabled. DVCC Charger Charger enable BAKCHV1 BAKCHCx ~2.7V VBAT Figure 3-2. Charger Block Diagram Battery Backup System SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 129: Battery Backup Registers
Retention Section BAKCTL Battery Backup Control Read/write not retained Section 3.3.1 BAKCHCTL Battery Charger Control Read/write not retained Section 3.3.2 SLAU208Q – June 2008 – Revised March 2018 Battery Backup System Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 130: Bakctl Register
DVCC or due to LPMx.5 operation. 0b = Backup subsystem not locked 1b = Backup subsystem locked Battery Backup System SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 131: Bakchctl Register
11b = Charge current defined by a maximum 20-kΩ resistor BAKCHEN Charger enable 0b = Charger disabled 1b = Charger enabled SLAU208Q – June 2008 – Revised March 2018 Battery Backup System Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 132: Auxiliary Supply System (Aux)
This chapter describes the AUX..........................Topic Page ..............Auxiliary Supply System Introduction ................Auxiliary Supply Operation ....................AUX Registers Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 133: Auxiliary Supply System Introduction
The backup subsystem usually contains a real-time clock (RTC) module with a 32-kHz crystal oscillator, backup RAM, and optionally (device-specific) up to two digital I/O pins. SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 134: Auxiliary Supply Operation
• The data stored in the backup RAM (if available) is retained but cannot be accessed. Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 135: Start-Up
To ensure reliable operation, the selected supply voltage (by default, the highest voltage in the system) must always supply at least 0.5 µA to critical circuitry. SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 136: Switching Control
SVM. When a switch occurs, interrupts are generated as described in Section 4.2.11. Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 137 To avoid rapid switching back and forth between supplies, any further switching is prevented during a "recovery time" of several hundred microseconds as specified in the device-specific data sheetafter each switch-over. SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 138: Interactions Among F
) for each system CORE DSYS frequency. For details on the recommended settings for PMMCOREV[1:0] and supply voltage, see Section 2.2.2.1. Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 139: System Frequency Vs Supply Voltage
011 (3) 010 (2) 001 (1) Invalid 000 (0) PMMCOREVx Figure 4-3. Available SVM Settings vs V Settings CORE SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 140: Auxiliary Supply Monitor
AUXxDRPIFG is set. Figure 4-5 shows a principle block diagram of the monitoring circuitry. Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 141: Auxiliary Supply Monitor Block Diagram
AUX2LVLx AUX0OK Threshold DVCC Comparator AUX1OK AUXVCC1 AUX2OK AUXVCC2 VLOCLK Control Logic Figure 4-5. Auxiliary Supply Monitor Block Diagram SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 142: Lpmx.5 And Auxiliary Supply Operation
Check connection of external loads at digital I/Os to avoid high voltage drops across switches. This might cause unwanted resets. Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 143: Measuring The Supplies
AUXVCC1 AUXVCC2 AUXADC ADC Sampling and INCHx = 0Ch AUXADCRx To ADC (A12) Figure 4-7. AUX Connection to ADC SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 144: Resistive Charger
(AUXxMD = 0). A (maskable) interrupt request is generated if the corresponding AUXxDRPIE bit and the GIE bit are set. Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 145 AUXSWNMIFG is set because the user-NMI has a higher priority. In this case, both interrupt vector generators, the SYSUNIV and the AUXIV, indicate a pending AUXSWNMIFG. SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 146: Software Flow
This example shows configuration for running at 25-MHz system frequency at a supply voltage of 3 V ±0.3 V, maintaining that frequency when switching to AUX1 or AUX2. Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 147: Svs
Given that the system frequency should be changed to 12 MHz when running from AUX1, settings must be changed when switching to AUX1. When switching from AUX0 (DVCC/AVCC) to AUX1: SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 148 2. Decrease core voltage level by setting PMMCOREV = 0 (also change SVS settings) 3. Decrease the SVM level by setting SVSMHRRL = 0 4. Set AUX1LVL and AUX2LVL to 0 Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 149: Aux Registers
0000h Section 4.3.8 AUXIV AUX Interrupt Vector Word Read/write 0000h Section 4.3.9 Access protected by key AUXKEY in AUXCTL0. SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 150: Auxctl0 Register
0b = Auxiliary supply system not locked 1b = Auxiliary supply system is locked and operating from DVCC or AUXVCC1 Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 151: Auxctl1 Register
0b = Supply not okay, below AUX0LVLx if AUX0MD = 0 1b = Supply okay, above AUX0LVLx if AUX0MD = 0 SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 152: Auxctl2 Register
011b = ≈2.26 V 100b = ≈2.40 V 101b = ≈2.70 V 110b = ≈3.00 V 111b = ≈3.00 V Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 153: Aux2Chctl Register
11b = Charge current defined by a maximum 20-kΩ resistor AUXCHEN Charger enable 0b = Charger disabled 1b = Charger enabled SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 154: Aux3Chctl Register
11b = Charge current defined by a maximum 20-kΩ resistor AUXCHEN Charger enable 0b = Charger disabled 1b = Charger enabled Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 155: Auxadcctl Register
11b = AUXVCC3 AUXADC Auxiliary supplies to ADC 0b = Auxiliary supply measurement disabled 1b = Auxiliary supply measurement enabled SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 156: Auxifg Register
1b = Interrupt pending AUX0SWIFG Switched to DVCC interrupt flag. 0b = No interrupt pending 1b = Interrupt pending Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 157: Auxie Register
0b = Interrupt disabled 1b = Interrupt enabled AUX0SWIE Switched to DVCC interrupt enable. 0b = Interrupt disabled 1b = Interrupt enabled SLAU208Q – June 2008 – Revised March 2018 Auxiliary Supply System (AUX) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 158: Auxiv Register
0Eh = Interrupt Source: AUXVCC2 below threshold interrupt flag; Interrupt Flag: AUX2DRPIFG 10h = Interrupt Source: Supply monitor interrupt flag; Interrupt Flag: AUXMONIFG; Interrupt Priority: Lowest Auxiliary Supply System (AUX) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 159: Unified Clock System (Ucs)
........................... Topic Page ............Unified Clock System (UCS) Introduction ....................UCS Operation ................Module Oscillator (MODOSC) ....................UCS Registers SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 160: Unified Clock System (Ucs) Introduction
1, 2, 4, 8, 16, or 32 within the FLL block. SMCLK can be divided by 1, 2, 4, 8, 16, or 32. SMCLK is software selectable by individual peripheral modules. Figure 5-1 shows the block diagram of the UCS module. Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 161: Ucs Block Diagram
Unconditonal XT2 Oscillator XT2OUT MODOSC requests MODCLK MODOSC Copyright © 2016, Texas Instruments Incorporated Figure 5-1. UCS Block Diagram SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 162: Ucs Operation
The VLO is enabled when it is used to source ACLK, MCLK, or SMCLK (SELA = {1} or SELM = {1} or SELS = {1}). Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 163: Internal Trimmed Low-Frequency Reference Oscillator (Refo)
When used with an external signal, the external frequency must meet the data sheet parameters for the chosen mode. XT1 is powered down when used in bypass mode. SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 164: Xt2 Oscillator
When used with an external signal, the external frequency must meet the data sheet parameters for the chosen mode. XT2 is powered down when used in bypass mode. Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 165: Digitally Controlled Oscillator (Dco)
The FLLD bits configure the FLL prescaler divider value D to 1, 2, 4, 8, 16, or 32. By default, D = 2, and MCLK and SMCLK are sourced from DCOCLKDIV, providing a clock frequency DCOCLK/2. SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 166: Frequency Locked Loop (Fll)
DCO to settle. The value n is defined by the FLLREFDIV bits (n = 1, FLLREFCLK 2, 4, 8, 12, or 16). Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 167: Dco Modulator
FLL remains disabled and the DCO operates at the previous setting as defined in UCSCTL0 and UCSCTL1. SCG0 can be cleared by user software if FLL operation is required. SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 168: Operation From Low-Power Modes, Requested By Peripheral Modules
Table 5-1 shows the relationship between the system clocks and the low-power modes in conjunction with the clock request logic. Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 169: Ucs Module Fail-Safe Operation
The OFIFG flag must be cleared by software. The source of the fault can be identified by checking the individual fault bits. SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 170 DCOCLKDIV is active even at the lowest DCO tap. The clock signal is available for the CPU to execute code and service an NMI during an oscillator fault. Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 171: Oscillator Fault Logic
XT1HFOFFG XT2_OscFault XT2_OF CTSD16OFFG (from CTSD16 module) XT2OFFG OscFault_Set OFIFG NMIRS OscFault_Clr OFIE NMI_IRQA Figure 5-4. Oscillator Fault Logic SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 172: Synchronization Of Clock Signals
The clock remains high until the next rising edge of the new clock. • The new clock source is selected and continues with a full high period. Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 173: Module Oscillator (Modosc)
ADC12OSC clock source. Upon doing so, the MODOSC source is enabled, if it is not already enabled by previous requests from other modules. SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 174: Ucs Registers
UCSCTL9_L Read/write Byte UCSCTL9_H Read/write Byte This register is not available on all devices. See the device-specific data sheet. Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 175: Ucsctl0 Register
0 to the maximum count, the DCO register value is also decremented. Reserved Reserved. Always reads as 0. SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 176: Ucsctl1 Register
Reserved. Always reads as 0. DISMOD Modulation. This bit enables or disables the modulation. 0b = Modulation enabled 1b = Modulation disabled Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 177: Ucsctl2 Register
Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to FLLN causes N to be set to 1. SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 178: Ucsctl3 Register
110b = Reserved for future use. Defaults to f /16. FLLREFCLK 111b = Reserved for future use. Defaults to f /16. FLLREFCLK Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 179: Ucsctl4 Register
110b = Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. 111b = Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 180: Ucsctl5 Register
110b = Reserved for future use. Defaults to f /32. MCLK 111b = Reserved for future use. Defaults to f /32. MCLK Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 181: Ucsctl6 Register
XT1BYPASS XT1 bypass select 0b = XT1 sourced from external crystal 1b = XT1 sourced from external clock signal SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 182 1b = XT1 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source required for FLL operation. Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 183: Ucsctl7 Register
1b = DCO fault. A DCO fault occurred after the last reset. Not available on all devices. When not available, this bit is reserved. SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 184: Ucsctl8 Register
ACLK clock request enable. Setting this enables conditional module requests for ACLK 0b = ACLK conditional requests are disabled. 1b = ACLK conditional requests are enabled. Unified Clock System (UCS) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 185: Ucsctl9 Register
Selects XT1 bypass input swing level. Must be set for reduced swing operation. 0b = Input range from 0 to DVCC 1b = Input range from 0 to DVIO SLAU208Q – June 2008 – Revised March 2018 Unified Clock System (UCS) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 186: Cpux
..............MSP430X CPU (CPUX) Introduction ......................Interrupts ....................CPU Registers .................... Addressing Modes ..............MSP430 and MSP430X Instructions ................Instruction Set Description CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 187: Msp430X Cpu (Cpux) Introduction
Direct memory-to-memory transfers without intermediate register holding • Byte, word, and 20-bit address-word addressing The block diagram of the MSP430X CPU is shown in Figure 6-1. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 188: Msp430X Cpu Block Diagram
General Purpose General Purpose General Purpose General Purpose Zero, Z Carry, C MCLK 16/20-bit ALU Overflow,V Negative,N Figure 6-1. MSP430X CPU Block Diagram CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 189: Interrupts
20-bit PC is restored making return from interrupt to any address in the memory range possible. Item n−1 PC.15:0 PC.19:16 SR.11:0 Figure 6-2. PC Storage on the Stack for Interrupts SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 190: Cpu Registers
Figure 6-5 shows the SP. The SP is initialized into RAM by the user, and is always aligned to even addresses. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 191: Stack Pointer
The POP SP instruction places SP1 into the stack pointer SP (SP2 = SP1) Figure 6-8. PUSH SP, POP SP Sequence SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 192: Status Register (Sr)
Carry. This bit is set when the result of an operation produced a carry and cleared when no carry occurred. NOTE: Bit manipulations of the SR should be done by the following instructions: MOV, BIS, and BIC. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 193: Constant Generator Registers (Cg1 And Cg2)
#0 is replaced by the assembler, and R3 is used with As = 00. INC dst is replaced by: ADD #1,dst SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 194: General-Purpose Registers (R4 To R15)
Register-Word Operation High Byte Low Byte 19 16 15 Register used Memory Operation Memory Figure 6-11. Register-Word Operation CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 195: Word-Register Operation
High Byte Low Byte 19 16 15 Register Unused Memory +2 Memory Operation Memory +2 Memory Figure 6-13. Register – Address-Word Operation SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 196: Addressing Modes
Throughout MSP430 documentation, EDE, TONI, TOM, and LEO are used as generic labels. They are only labels and have no special meaning. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 197: Register Mode
Register Space Space 21036h xxxxh AA550h 21036h xxxxh AA550h 11111h BB551h 21034h D546h 21034h D546h 21032h 1800h 21032h 1800h AA550h.or.11111h = BB551h SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 198: Indexed Mode
The byte pointed to by R6 + F000h results in address 01778h + F000h = 00778h after truncation to a 16-bit address. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 199: Indexed Mode In Upper Memory
16-bit byte index (sign extended to 20 bits) 10000 0FFFF 20-bit signed add 00000 Memory address Figure 6-16. Indexed Mode in Upper Memory SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 200: Overflow And Underflow For Indexed Mode
23456h + F8346h = 1B79Ch. Destination: The word pointed to by R6 + 2100h results in address 15678h + 2100h = 17778h. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 201: Example For Indexed Mode
Two words pointed to by R5 + 12346h which results in address 23456h + 12346h = 3579Ch. Destination: Two words pointed to by R6 + 32100h which results in address 45678h + 32100h = 77778h. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 202 Two words pointed to by R5 + 8002h and R5 + 8002h + 2h which results in address 00100h + F8002h (+2h) = F8102h and F8104h. Destination: Register R6 CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 203: Symbolic Mode
Byte TONI located at address 00778h, pointed to by PC + F740h, is the truncated 16-bit result of 00778h – 1038h = FF740h. Address 01038h is the location of the index for this example. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 204: Symbolic Mode Running In Upper Memory
16-bit byte index (sign extended to 20 bits) 10000 0FFFF 20-bit signed add 00000 Memory address Figure 6-20. Symbolic Mode Running in Upper Memory CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 205: Overflow And Underflow For Symbolic Mode
3379Ch – 2F036h = 04766h. Address 2F036h is the location of the index for this example. Destination: Word TONI located at address 00778h pointed to by the absolute address 00778h SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 206 Byte TONI located at address 77778h, pointed to by PC + 56740h, is the 20-bit result of 77778h – 21038h = 56740h. Address 21038h is the address of the index in this example. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 207: Absolute Mode
This instruction adds the 16-bit data contained in the absolute source and destination addresses and places the result into the destination. Source: Word at address EDE Destination: Word at address TONI SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 208 Source: Two words beginning with address EDE Destination: Two words beginning with address TONI CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 209: Indirect Register Mode
Word pointed to by R5. R5 contains address 3579Ch for this example. Destination: Word pointed to by R6 + 2100h, which results in address 45678h + 2100h = 7778h SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 210: Indirect Autoincrement Mode
Byte pointed to by R5. R5 contains address 3579Ch for this example. Destination: Byte pointed to by R6 + 0h, which results in address 0778h for this example CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 211: Immediate Mode
This instruction adds the 16-bit immediate operand 3456h to the data in the destination address TONI. Source: 16-bit immediate value 3456h Destination: Word at address TONI SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 212 3456h 21036h 3456h 50F2h 50F2h 21034h 21034h 1907h 1907h 21032h 21032h 23456h 7777Ah 0001h 7777Ah 0003h +12345h 3579Bh 2345h 579Bh 77778h 77778h CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 213: Msp430 And Msp430X Instructions
Table 6-4 lists the 12 MSP430 double-operand instructions. Op-code Rsrc Rdst Source or Destination 15:0 Destination 15:0 Figure 6-22. MSP430 Double-Operand Instruction Format SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 214: Msp430 Single-Operand Instructions
* = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 215: Format Of Conditional Jump Instructions
* = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 216: Interrupt, Return, And Reset Cycles And Length
Instruction PUSH CALL SWPB, SXT SWPB R5 RRC @R9 @Rn+ SWPB @R10+ CALL #LABEL X(Rn) CALL 2(R7) PUSH EDE &EDE SXT &EDE CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 217: Msp430 Format I Instructions Cycles And Length
MOV &EDE,R8 BR &EDE TONI MOV &EDE,TONI x(Rm) MOV &EDE,0(SP) &TONI MOV &EDE,&TONI MOV, BIT, and CMP instructions execute in one fewer cycle. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 218: Msp430X Extended Instructions
Table 6-12. An example is shown in Figure 6-28. Source bits 19:16 Destination bits 19:16 Figure 6-26. Extension Word for Non-Register Modes CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 219: Example For Extended Register Or Register Instruction
8(R8) XORX instruction Source R9 Destination R8 Destination register mode Source register mode Figure 6-27. Example for Extended Register or Register Instruction SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 220: Example For Extended Immediate Or Indexed Instruction
* = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 221: Extended Format I Instruction Formats
Figure 6-30. Address+2 ..................19:16 Operand LSBs 15:0 Address Figure 6-30. 20-Bit Addresses in Memory SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 222: Extended Format Ii Instruction Format
The three possible addressing mode combinations for Format II instructions are shown in Figure 6-31. n−1/Rn Op-code Op-code dst.19:16 Op-code dst.15:0 Figure 6-31. Extended Format II Instruction Format CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 223: Pushm And Popm Instruction Format
Figure 6-34. BRA Instruction Format Op-code Rdst Op-code Rdst index15:0 Op-code #imm/ix/abs19:16 #imm15:0 / index15:0 / &abs15:0 Figure 6-35. CALLA Instruction Format SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 224: Extended Emulated Instructions
Test Rdst (compare with 0) TSTX(.B,.A) dst CMPX(.B,.A) #0,dst Test dst (compare with 0) POPX dst MOVX(.B, .A) @SP+,dst Pop to dst CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 225: Address Instructions, Operate On 20-Bit Register Data
* = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 226: Msp430X Format Ii Instruction Cycles And Length
5, 3 5, 3 POPX.A 4, 2 – – – 7, 3 7, 3 7, 3 Add one cycle when Rn = SP CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 227: Msp430X Format I Instruction Cycles And Length
Reduce the cycle count by two for MOV, BIT, and CMP instructions. Reduce the cycle count by one for MOV, ADD, and SUB instructions. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 228: Address Instruction Cycles And Length
MOVA 2(R5),R8 – – MOVA 2(R6),PC – – MOVA EDE,R8 – – MOVA EDE,PC &EDE – – MOVA &EDE,R8 – – MOVA &EDE,PC CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 229: Instruction Set Description
SUB, SUB.B 9xxx CMP, CMP.B Axxx DADD, DADD.B Bxxx BIT, BIT.B Cxxx BIC, BIC.B Dxxx BIS, BIS.B Exxx XOR, XOR.B Fxxx AND, AND.B SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 230: Extended Instruction Binary Descriptions
– 1 RRCM.W #n,Rdst RRAM.W RRAM.W #n,Rdst n – 1 RLAM.W n – 1 RLAM.W #n,Rdst RRUM.W RRUM.W #n,Rdst n – 1 CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 231 POPM.A n – 1 dst – n + 1 POPM.A #n,Rdst POPM.W n – 1 dst – n + 1 POPM.W #n,Rdst SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 232: Msp430 Instructions
Instruction Set Description www.ti.com 6.6.2 MSP430 Instructions The MSP430 instructions are listed and described on the following pages. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 233 The 8-bit counter pointed to by R13 is added to a 16-bit counter pointed to by R12. ADD.B @R13,0(R12) ; Add LSDs ADC.B 1(R12) ; Add carry to MSD SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 234 The table pointer is auto-incremented by 1. R6.19:8 = 0 ADD.B @R5+,R6 ; Add byte to R6. R5 + 1. R6: 000xxh TONI ; Jump if no carry ; Carry occurred CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 235 ADDC.B @R5+,R6 ; Add table byte + C to R6. R5 + 1 TONI ; Jump if no carry ; Carry occurred SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 236 1 after the fetching of the byte. R6.19:8 = 0 AND.B @R5+,R6 ; AND table byte with R6. R5 + 1 CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 237 A table byte pointed to by R5 (20-bit address) is used to clear bits in Port1. BIC.B @R5,&P1OUT ; Clear I/O port P1 bits set in @R5 SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 238 A table byte pointed to by R5 (20-bit address) is used to set bits in Port1. R5 is incremented by 1 afterwards. BIS.B @R5+,&P1OUT ; Set I/O port P1 bits. R5 + 1 CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 239 ; Test I/O port P1 bits. R5 + 1 TONI ; No corresponding bit is set ; At least one bit is set SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 240 ; starting at X). X can be an address or a label ; Core instruction MOV X(R5),PC ; Indirect, indirect R5 + X CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 241 Indirect Mode: Call a subroutine at the 16-bit address contained in the word pointed to by register R5 (20-bit address). CALL ; Start address at @R5 SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 242 TONI ; 0 -> TONI Example Register R5 is cleared. Example RAM byte TONI is cleared. CLR.B TONI ; 0 -> TONI CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 243 @R13,0(R12) ; add 16-bit counter to low word of 32-bit counter DADC 2(R12) ; add carry to high word of 32-bit counter SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 244 CLRN CALL SUBR .... SUBR SUBRET ; If input is negative: do nothing and return ....SUBRET CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 245 (R5 + X); for example, a table with addresses starting at X. The address is within the lower 64KB. X is within ±32KB. CALL X(R5) ; Start address at @(R5+X). z16(R5) SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 246 Jump to label TONI if values are equal. The next table byte is addressed. CMP.B @R5+,&P1OUT ; Compare P1 bits with table. R5 + 1 TONI ; Equal contents ; Not equal CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 247 ; Reset carry ; next instruction's start condition is defined DADD.B R5,0(R8) ; Add LSDs + C DADC 1(R8) ; Add carry to MSDs SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 248 BCD number contained in R4. The carry C is added, also. R4.19:8 = 0 CLRC ; Clear carry DADD.B &BCD,R4 ; Add BCD to R4 decimally. R4: 0,00ddh CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 249: Decrement Overlap
Do not transfer tables using the routine above with the overlap shown in Figure 6-36. TONI EDE+254 TONI+254 Figure 6-36. Decrement Overlap SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 250 DECD Example Memory at location LEO is decremented by two. DECD.B ; Decrement MEM(LEO) Decrement status byte STATUS by two DECD.B STATUS CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 251 The rules above apply to all instructions that clear the general interrupt enable bit. Not following these rules might result in unexpected CPU execution. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 252 The rules above apply to all instructions that set the general interrupt enable bit. Not following these rules might result in unexpected CPU execution. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 253 The status byte, STATUS, of a process is incremented. When it is equal to 11, a branch to OVFL is taken. INC.B STATUS CMP.B #11,STATUS OVFL SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 254 The byte on the top of the stack is incremented by two. INCD.B 0(SP) ; Byte on TOS is increment by two CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 255 Content of memory byte LEO is negated. MOV.B #0AEh,LEO MEM(LEO) = 0AEh INV.B ; Invert LEO, MEM(LEO) = 051h INC.B ; MEM(LEO) is negated, MEM(LEO) = 052h SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 256 ; Is R5 >= 12345h? Info to C Label2 ; Yes, 12344h < R5 <= F,FFFFh. C = 1 ; No, R5 < 12345h. Continue CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 257 R7 (20-bit counter) is incremented. If its content is zero, the program continues at Label4. ADDA #1,R7 ; Increment R7 Label4 ; Zero reached: Go to Label4 ; R7 not equal 0. Continue here. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 258 CMPA #12345h,R5 ; Is R5 >= 12345h? Label2 ; Yes, 12344h < R5 <= 7FFFFh ; No, 80000h <= R5 < 12345h CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 259 CMPA #12345h,R5 ; Is R5 < 12345h? Label2 ; Yes, 80000h =< R5 < 12345h ; No, 12344h < R5 <= 7FFFFh SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 260 ; No Timer_A interrupt pending IHCCR1 ; Timer block 1 caused interrupt IHCCR2 ; Timer block 2 caused interrupt RETI ; No legal interrupt, return CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 261 Label4. Program in full memory range. SUBA #1,R7 ; Decrement R7 Label4 ; R7 < 0: Go to Label4 ; R7 >= 0. Continue here. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 262 TONI is within PC ± 32 K. TONI,R5 ; TONI + R5 -> R5. Carry -> C Label0 ; No carry ; Carry = 1: continue here CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 263 Label4. Program in full memory range. SUBA #1,R7 ; Decrement R7 Label4 ; Zero not reached: Go to Label4 ; Yes, R7 = 0. Continue here. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 264 Loop MOV.B @R10+,TOM-EDE-1(R10) ; R10 points to both tables. ; R10+1 ; Decrement counter Loop ; Not yet done ; Copy completed CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 265 No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status Bits Status bits are not affected. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 266 ; Last word on stack moved to the SR NOTE: System stack pointer The system SP is always incremented by two, independent of the byte suffix. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 267 Save the two bytes EDE and TONI on the stack. The addresses EDE and TONI are within PC ± 32 K. PUSH.B ; Save EDE xxXXh PUSH.B TONI ; Save TONI xxYYh SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 268: Stack After A Ret Instruction
; Return to lower 64 K Item n Item n Return Stack before RET Stack after RET instruction instruction Figure 6-37. Stack After a RET Instruction CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 269 ; Interrupt handler code POPM.A #2,R14 ; Restore R13 and R14 (20-bit data) RETI ; Return to 20-bit address in full memory range SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 270: Destination Operand—Arithmetic Shift Left
The assembler does not recognize the instructions: @R5+ RLA.B @R5+ RLA(.B) @R5 They must be substituted by: @R5+,-2(R5) ADD.B @R5+,-1(R5) ADD(.B) @R5 CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 271: Destination Operand—Carry Left Shift
The assembler does not recognize the instructions: @R5+ RLC.B @R5+ RLC(.B) @R5 They must be substituted by: ADDC @R5+,-2(R5) ADDC.B @R5+,-1(R5) ADDC(.B) @R5 SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 272: Rotate Right Arithmetically Rra.b And Rra.w
The signed RAM byte EDE is shifted arithmetically right one position. RRA.B ; EDE/2 -> EDE Figure 6-40. Rotate Right Arithmetically RRA.B and RRA.W CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 273: Rotate Right Through Carry Rrc.b And Rrc.w
; Prepare carry for MSB ; EDE = EDE >> 1 + 8000h Figure 6-41. Rotate Right Through Carry RRC.B and RRC.W SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 274 ; Subtract LSDs SBC.B 1(R12) ; Subtract carry from MSD NOTE: Borrow implementation The borrow is treated as a .NOT. carry: Borrow Carry Bit CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 275 ; Emulate subtraction by addition of: ; (010000h - R5 - 1) ; R6 = R6 + R5 + 1 ; R6 = 0150h SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 276 The negative bit (N) is set. Status Bits Not affected Not affected Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 277 The zero bit (Z) is set. Status Bits Not affected Not affected Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 278 Byte CNT is subtracted from byte R12 points to. The address of CNT is within PC ± 32K. The address R12 points to is in full memory range. SUB.B CNT,0(R12) ; Subtract CNT from @R12 CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 279 Byte CNT is subtracted from the byte, R12 points to. The carry of the previous instruction is used. The address of CNT is in lower 64 K. SUBC.B &CNT,0(R12) ; Subtract byte CNT from @R12 SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 280: Swap Bytes In Memory
Figure 6-42. Swap Bytes in Memory Before SWPB High Byte Low Byte After SWPB Low Byte High Byte Figure 6-43. Swap Bytes in a Register CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 281 R7. MOV.B EDE,R5 ; EDE -> R5. 00XXh ; Sign extend low byte to R5.19:8 ADDA R5,R7 ; Add signed 20-bit values SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 282 ; Low byte of R7 is positive but not zero R7NEG ..; Low byte of R7 is negative R7ZERO ..; Low byte of R7 is zero CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 283 R7.19:8 = 0. The address of EDE is within PC ± 32 K. XOR.B EDE,R7 ; Set different bits to 1 in R7. INV.B ; Invert low byte of R7, high byte is 0h SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 284: Extended Instructions
20-bit values when preceded by the extension word. The MSP430X extended instructions are listed and described in the following pages. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 285 The 40-bit counter, pointed to by R12 and R13, is incremented. INCX.A @R12 ; Increment lower 20 bits ADCX.A @R13 ; Add carry to upper 20 bits SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 286 ; Jump if no carry ; Carry occurred Note: Use ADDA for the following two cases for better code density and execution. ADDX.A Rsrc,Rdst ADDX.A #imm20,Rdst CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 287 ADDCX.B @R5+,R6 ; Add table byte + C to R6. R5 + 1 TONI ; Jump if no carry ; Carry occurred SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 288 A table byte pointed to by R5 (20-bit address) is logically ANDed with R6. R6.19:8 = 0. The table pointer is auto-incremented by 1. ANDX.B @R5+,R6 ; AND table byte with R6. R5 + 1 CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 289 A table byte pointed to by R5 (20-bit address) is used to clear bits in output Port1. BICX.B @R5,&P1OUT ; Clear I/O port P1 bits SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 290 A table byte pointed to by R5 (20-bit address) is used to set bits in output Port1. BISX.B @R5,&P1OUT ; Set I/O port P1 bits CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 291 ; Test input P1 bits. R5 + 1 TONI ; No corresponding input bit is set ; At least one bit is set SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 292 Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example RAM address-word TONI is cleared. CLRX.A TONI ; 0 -> TONI CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 293 ; Equal contents ; Not equal Note: Use CMPA for the following two cases for better density and execution. CMPA Rsrc,Rdst CMPA #imm20,Rdst SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 294 The 40-bit counter, pointed to by R12 and R13, is incremented decimally. DADDX.A #1,0(R12) ; Increment lower 20 bits DADCX.A 0(R13) ; Add carry to upper 20 bits CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 295 The two-digit BCD number contained in 20-bit address BCD is added decimally to a two- digit BCD number contained in R4. CLRC ; Clear carry DADDX.B BCD,R4 ; Add BCD to R4 decimally. ; R4: 000ddh SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 296 Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example RAM address-word TONI is decremented by one. DECX.A TONI ; Decrement TONI CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 297 Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example RAM address-word TONI is decremented by two. DECDX.A TONI ; Decrement TONI SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 298 Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example RAM address-wordTONI is incremented by one. INCX.A TONI ; Increment TONI (20-bits) CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 299 OSCOFF, CPUOFF, and GIE are not affected. Example RAM byte LEO is incremented by two; PC points to upper memory. INCDX.B ; Increment LEO by two SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 300 Content of memory byte LEO is negated. PC is pointing to upper memory. INVX.B ; Invert LEO INCX.B ; MEM(LEO) is negated CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 301 ; Indirect,Auto/Reg MOVX.A Rsrc,&abs20 MOVA Rsrc,&abs20 ; Reg/Absolute The next four replacements are possible only if 16-bit indexes are sufficient for the addressing: SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 302 MOVA z16(Rsrc),Rdst ; Indexed/Reg MOVX.A Rsrc,z20(Rdst) MOVA Rsrc,z16(Rdst) ; Reg/Indexed MOVX.A symb20,Rdst MOVA symb16,Rdst ; Symbolic/Reg MOVX.A Rsrc,symb20 MOVA Rsrc,symb16 ; Reg/Symbolic CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 303 Example Restore the 16-bit registers R9, R10, R11, R12, R13 from the stack. POPM.W #5,R13 ; Restore R9, R10, R11, R12, R13 SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 304 Save the five 16-bit registers R9, R10, R11, R12, R13 on the stack PUSHM.W #5,R13 ; Save R13, R12, R11, R10, R9 CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 305 &EDE ; Write word to address EDE Example Write the 20-bit value on TOS to R9 POPX.A ; Write address-word to R9 SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 306 ; Save byte at address EDE Example Save the 20-bit value in R9 on the stack. PUSHX.A ; Save address-word in R9 CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 307: Rotate Left Arithmetically—Rlam[.W] And Rlam.a
The 20-bit operand in R5 is shifted left by three positions. It operates equal to an arithmetic multiplication by 8. RLAM.A #3,R5 ; R5 = R5 x 8 0000 Figure 6-44. Rotate Left Arithmetically—RLAM[.W] and RLAM.A SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 308: Destination Operand-Arithmetic Shift Left
Example The 20-bit value in R7 is multiplied by 2 RLAX.A ; Shift left R7 (20-bit) Figure 6-45. Destination Operand-Arithmetic Shift Left CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 309: Destination Operand-Carry Left Shift
The RAM byte LEO is shifted left one position. PC is pointing to upper memory. RLCX.B ; RAM(LEO) x 2 + C -> RAM(LEO) Figure 6-46. Destination Operand-Carry Left Shift SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 310: Rotate Right Arithmetically Rram[.W] And Rram.a
#1,R15 ; (1.5 y R15) y 0.5 = 0.75 y R15 -> R15 0000 Figure 6-47. Rotate Right Arithmetically RRAM[.W] and RRAM.A CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 311 The signed 20-bit number in R5 is shifted arithmetically right four positions. RRAX.A ; R5/16 -> R5 Example The signed 8-bit value in EDE is multiplied by 0.5. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 312: Rotate Right Arithmetically Rrax(.B,.A) – Register Mode
; EDE/2 -> EDE 0000 Figure 6-48. Rotate Right Arithmetically RRAX(.B,.A) – Register Mode Figure 6-49. Rotate Right Arithmetically RRAX(.B,.A) – Non-Register Mode CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 313 Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4) Reset Mode Bits OSCOFF, CPUOFF, and GIE are not affected. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 314: Rotate Right Through Carry Rrcm[.W] And Rrcm.a
MSB–1 is loaded with the contents of the carry flag. RRCM.W #2,R6 ; R6 = R6 » 2. R6.19:16 = 0 Figure 6-50. Rotate Right Through Carry RRCM[.W] and RRCM.A CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 315 ; Prepare carry for MSB RRCX.A ; EDE = EDE » 1 + 80000h Example The word in R6 is shifted right by 12 positions. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 316: Rotate Right Through Carry Rrcx(.B,.A) – Register Mode
0 − − − − − − − − − − − − − − − − − − − − 0 Figure 6-51. Rotate Right Through Carry RRCX(.B,.A) – Register Mode Figure 6-52. Rotate Right Through Carry RRCX(.B,.A) – Non-Register Mode CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 317: Rotate Right Unsigned Rrum[.W] And Rrum.a
The word in R6 is shifted right by one bit. The MSB R6.15 is loaded with 0. RRUM.W #1,R6 ; R6 = R6/2. R6.19:15 = 0 0000 Figure 6-53. Rotate Right Unsigned RRUM[.W] and RRUM.A SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 318: Rotate Right Unsigned Rrux(.B,.A) – Register Mode
0 − − − − − − − − − − − − − − − − − − − − 0 Figure 6-54. Rotate Right Unsigned RRUX(.B,.A) – Register Mode CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 319 ; Subtract LSDs SBCX.B 1(R12) ; Subtract carry from MSD NOTE: Borrow implementation The borrow is treated as a .NOT. carry: Borrow Carry Bit SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 320 ; Subtract CNT from @R12 Note: Use SUBA for the following two cases for better density and execution. SUBX.A Rsrc,Rdst SUBX.A #imm20,Rdst CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 321 Byte CNT is subtracted from the byte R12 points to. The carry of the previous instruction is used. 20-bit addresses. SUBCX.B &CNT,0(R12) ; Subtract byte CNT from @R12 SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 322: Swap Bytes Swpbx.a Register Mode
Figure 6-55. Swap Bytes SWPBX.A Register Mode Before SWPBX.A High Byte Low Byte After SWPBX.A Low Byte High Byte Figure 6-56. Swap Bytes SWPBX.A In Memory CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 323: Swap Bytes Swpbx[.W] Register Mode
Figure 6-57. Swap Bytes SWPBX[.W] Register Mode Before SWPBX High Byte Low Byte After SWPBX Low Byte High Byte Figure 6-58. Swap Bytes SWPBX[.W] In Memory SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 324: Sign Extend Sxtx.a
8 7 6 SXTX.A dst 8 7 6 ..Figure 6-59. Sign Extend SXTX.A SXTX[.W] Rdst SXTX[.W] dst Figure 6-60. Sign Extend SXTX[.W] CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 325 ; LEO is zero LEOPOS ..; LEO is positive but not zero LEONEG ..; LEO is negative LEOZERO ..; LEO is zero SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 326 (20-bit address) XORX.B EDE,R7 ; Set different bits to 1 in R7 INV.B ; Invert low byte of R7. R7.19:8 = 0. CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 327: Address Instructions
MOVA instruction. Restricting the addressing modes removes the need for the additional extension-word op-code improving code density and execution time. The MSP430X address instructions are listed and described in the following pages. SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 328 R5 is increased by 0A4320h. The jump to TONI is performed if a carry occurs. ADDA #0A4320h,R5 ; Add A4320h to 20-bit R5 TONI ; Jump on carry ; No carry occurred CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 329 Indirect mode: Branch to the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5. ; MOVA @R5,PC SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 330 Note: If the 16-bit index is not sufficient, a 20-bit index X may be used with the following instruction: MOVX.A X(R5),PC ; 1M byte range with 20-bit index CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 331 Indirect mode: Call a subroutine at the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5. CALLA ; Start address at @R5 SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 332 LSBs, (R5 + X + 2) points to the MSBs of the word address. X is within R5 ± 32 K. Indirect, indirect (R5 + X). CALLA X(R5) ; Start address at @(R5+X). z16(R5) CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 333 The destination register is cleared. Status Bits Status bits are not affected. Example The 20-bit value in R10 is cleared. CLRA ; 0 -> R10 SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 334 R6, the program continues at label GRE. CMPA R6,R5 ; Compare R6 with R5 (R5 - R6) ; R5 >= R6 ; R5 < R6 CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 335 OSCOFF, CPUOFF, and GIE are not affected. Example The 20-bit value in R5 is decremented by 2. DECDA ; Decrement R5 by two SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 336 OSCOFF, CPUOFF, and GIE are not affected. Example The 20-bit value in R5 is incremented by two. INCDA ; Increment R5 by two CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 337 Copy 20-bit value R9 points to (20 bit address) to R8. Source operand in addresses @R9 LSBs and @(R9 + 2) MSBs. MOVA @R9,R8 ; @R9 -> R8. 2 words transferred SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 338 Move 20-bit value in R13 to 20-bit addresses EDE (LSBs) and EDE+2 (MSBs). PC index ± 32 K. MOVA R13,EDE ; R13 -> EDE. 2 words transferred CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 339 ; Save R14 and R13 (20 bit data) ; Subroutine code POPM.A #2,R14 ; Restore R13 and R14 (20 bit data) RETA ; Return (to full address space) SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 340 The 20-bit value in R5 is subtracted from R6. If a carry occurs, the program continues at label TONI. SUBA R5,R6 ; R6 - R5 -> R6 TONI ; Carry occurred ; No carry CPUX SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 341 ; R7 is zero R7POS ..; R7 is positive but not zero R7NEG ..; R7 is negative R7ZERO ..; R7 is zero SLAU208Q – June 2008 – Revised March 2018 CPUX Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 342: Flash Memory Controller
This chapter describes the operation of the flash memory controller..........................Topic Page ................Flash Memory Introduction ................Flash Memory Segmentation ................... Flash Memory Operation ....................FCTL Registers Flash Memory Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 343: Flash Memory Introduction
Control Registers Address/Data Latch Timing Generator Flash Memory Array Programming Voltage Generator Figure 7-1. Flash Memory Module Block Diagram SLAU208Q – June 2008 – Revised March 2018 Flash Memory Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 344: Flash Memory Segmentation
Flash Memory Flash Memory Bank C Bank D Segment 126 Segment 127 Figure 7-2. 256KB of Flash Memory Segments Example Flash Memory Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 345: Segment A
; No, lock SegmentA SEGA_LOCKED ; Yes, continue ; SegmentA is locked ; Lock Info Memory #FWPW+LOCKINFO,&FCTL4 ; Set LOCKINFO SLAU208Q – June 2008 – Revised March 2018 Flash Memory Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 346: Flash Memory Operation
Bank operations are not supported on all devices. See the device-specific data sheet for support of bank operations. Flash Memory Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 347: Erase Cycle Timing
They are not erased during a bank erase or a mass erase. Erasing is only possible by first clearing the LOCKINFO bit. SLAU208Q – June 2008 – Revised March 2018 Flash Memory Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 348: Erase Cycle From Flash
&0FC10h ; Dummy write #BUSY,&FCTL3 ; Test BUSY ; Loop while busy #FWPW+LOCK,&FCTL3 ; Done, set LOCK ; Re-enable WDT? Flash Memory Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 349: Erase Cycle From Ram
&0FC10h ; Dummy write #BUSY,&FCTL3 ; Test BUSY ; Loop while busy #FWPW+LOCK,&FCTL3 ; Done, set LOCK ; Re-enable WDT? SLAU208Q – June 2008 – Revised March 2018 Flash Memory Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 350: Writing Flash Memory
See the device-specific data sheet for specifications. Flash Memory Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 351: Initiating A Byte Or Word Write From Flash
; Enable write #0123h,&0FF1Eh ; 0123h -> 0x0FF1E #FWPW,&FCTL1 ; Done. Clear WRT #FWPW+LOCK,&FCTL3 ; Set LOCK ; Re-enable WDT? SLAU208Q – June 2008 – Revised March 2018 Flash Memory Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 352: Initiating A Byte Or Word Write From Ram
; 0123h -> 0x0FF1E #BUSY,&FCTL3 ; Test BUSY ; Loop while busy #FWPW,&FCTL1 ; Clear WRT #FWPW+LOCK,&FCTL3 ; Set LOCK ; Re-enable WDT? Flash Memory Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 353: Initiating Long-Word Write From Flash
; 0123h -> 0x0FF1C #45676h,&0FF1Eh ; 04567h -> 0x0FF1E #FWPW,&FCTL1 ; Done. Clear BLKWRT #FWPW+LOCK,&FCTL3 ; Set LOCK ; Re-enable WDT? SLAU208Q – June 2008 – Revised March 2018 Flash Memory Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 354: Initiating Long-Word Write From Ram
; 4567h -> 0x0FF1E #BUSY,&FCTL3 ; Test BUSY ; Loop while busy #FWPW,&FCTL1 ; Clear WRT #FWPW+LOCK,&FCTL3 ; Set LOCK ; Re-enable WDT? Flash Memory Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 355: Block-Write Cycle Timing
Cumulative Programming Time < t , V Current Consumption is Increased BUSY Block,0 Block,1–(N-1) Block,N WAIT Figure 7-11. Block-Write Cycle Timing SLAU208Q – June 2008 – Revised March 2018 Flash Memory Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 356: Block Write Flow
Set BLKWRT=0 BUSY = 1 Another Block? Set WRT = 0, LOCK = 1, Reenable WDT Figure 7-12. Block Write Flow Flash Memory Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 357: Flash Memory Access During Write Or Erase
Block write Write ACCVIFG = 0: Valid write Instruction fetch ACCVIFG = 1: LOCK = 1, block write is exited SLAU208Q – June 2008 – Revised March 2018 Flash Memory Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 358: Stopping Write Or Erase Cycle
During marginal read mode, the flash access speed (MCLK) must be limited to 1 MHz (see the device-specific data sheet). Flash Memory Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 359: Configuring And Accessing The Flash Memory Controller
The password violation flag, KEYV, is set when any of the flash control registers are written with an incorrect password. When this occurs, a PUC is generated immediately, resetting the device. SLAU208Q – June 2008 – Revised March 2018 Flash Memory Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 360: Programming Flash Memory Devices
Commands and data UART, CPU executes Host MSP430 Px.x, user software Read and write flash memory Figure 7-13. User-Developed Programming Solution Flash Memory Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 361: Fctl Registers
Byte FCTL3_H Read/Write Byte FCTL4 Flash Memory Control 4 Read/write Word 9600h Section 7.4.3 FCTL4_L Read/Write Byte FCTL4_H Read/Write Byte SLAU208Q – June 2008 – Revised March 2018 Flash Memory Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 362: Fctl1 Register
1-0 = Bank erase (erase of one bank) 1-1 = Mass erase (erase all flash memory banks) Reserved Reserved. Always reads as 0. Flash Memory Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 363: Fctl3 Register
Busy. This bit indicates if the flash is currently busy erasing or programming. 0b = Not busy 1b = Busy SLAU208Q – June 2008 – Revised March 2018 Flash Memory Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 364: Fctl4 Register
Voltage changed during program error. This bit is set by hardware and can only be cleared by software. If DVCC changed significantly during programming, this bit is set to indicate an invalid result. Flash Memory Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 365: Sfrie1 Register
1b = Interrupt enabled These bits may be used by other modules (see the device-specific data sheet and the SYS chapter for details). SLAU208Q – June 2008 – Revised March 2018 Flash Memory Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 366: Memory Integrity Detection (Mid)
MID Parity Check Logic ............Detecting Unprogrammed Memory Accesses ......................MID ROM ................MID Support Software Function ................User's UNMI Interrupt Handler Memory Integrity Detection (MID) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 367: Mid Overview
Array (plain Programming data) Voltage Generator MSP430 Flash MID Add-on Memory Controller Figure 8-1. Block Diagram of MID Implementation SLAU208Q – June 2008 – Revised March 2018 Memory Integrity Detection (MID) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 368: Flash Memory With Mid Support
(0). Enabling the MID functionality for nonprogrammed memory ranges allows detecting memory accesses to these nonprogrammed addresses. Memory Integrity Detection (MID) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 369: Mid Rom
0x18 Read out horizontal parity bit MidCalcVParity 0x1C Calculating vertical parity Reserved 0x20 Reserved 0x24 Reserved 0x28 Reserved 0x2C SLAU208Q – June 2008 – Revised March 2018 Memory Integrity Detection (MID) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 370: Midenable() Function
Enables or disables MID for the flash information memory segment A. 0 = MID support is deactivated 1 = MID support is active Memory Integrity Detection (MID) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 371: Middisable() Function
SYSBERRIV register. The code example in Section 8.7 shows where the MidGetErrAdr() function call should be placed. SLAU208Q – June 2008 – Revised March 2018 Memory Integrity Detection (MID) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 372: Midcheckmem() Function
// data that will be written into flash memory Parity=0; // parity bit that will be written MIDSetRaw(Data,Parity,&FlashAdr,FWKEY); // write data and parity bit while(1); Memory Integrity Detection (MID) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 373: Midgetparity() Function
// MID error <place your MID error handler code here> break; case 0x08: break; default: break; break; default: break; SLAU208Q – June 2008 – Revised March 2018 Memory Integrity Detection (MID) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 374: Slau208Q - June 2008 - Revised March 2018
The RAM controller (RAMCTL) allows control of the operation of the RAM..........................Topic Page ............... RAM Controller (RAMCTL) Introduction ................... RAMCTL Operation ................... RAMCTL Registers RAM Controller (RAMCTL) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 375: Ram Controller (Ramctl) Introduction
RCRS7OFF can be set to switch off this memory if it is not required for USB operation or is not being used in normal operation. SLAU208Q – June 2008 – Revised March 2018 RAM Controller (RAMCTL) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 376: Ramctl Registers
Type Access Reset Section RCCTL0 RAM Controller Control 0 Read/write Word 6900h Section 9.3.1 RCCTL0_L Read/write Byte RCCTL0_H Read/write Byte RAM Controller (RAMCTL) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 377: Rcctl0 Register
All data of the RAM sector 0 is lost. See the device-specific data sheet to find the the number of RAM sectors available along with their respective address ranges and sizes. SLAU208Q – June 2008 – Revised March 2018 RAM Controller (RAMCTL) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 378: Backup Ram
(if supported by the device). This chapter describes the backup RAM..........................Topic Page ............10.1 Backup RAM Introduction and Operation .................. 10.2 Battery Backup Registers Backup RAM SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 379: Backup Ram Registers
Undefined retained BAKMEM3 Battery Backup Memory 3 Read/write Word Undefined retained BAKMEM3_L Read/write Byte Undefined retained BAKMEM3_H Read/write Byte Undefined retained SLAU208Q – June 2008 – Revised March 2018 Backup RAM Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 380: Direct Memory Access (Dma) Controller Module
Topic Page ............11.1 Direct Memory Access (DMA) Introduction ....................11.2 DMA Operation ....................11.3 DMA Registers Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 381: Direct Memory Access (Dma) Introduction
Four addressing modes • Single, block, or burst-block transfer modes Figure 11-1 shows the DMA controller block diagram. SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 382: Dma Controller Block Diagram
DMAEN DMASRCINCR DMARMWDIS DMAnTRIG31 11111 Halt CPU to USB if available Figure 11-1. DMA Controller Block Diagram Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 383: Dma Addressing Modes
Block Of Addresses To Fixed Address Block Of Addresses To Block Of Addresses Figure 11-2. DMA Addressing Modes SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 384: Dma Transfer Modes
Repeated block transfer A complete block is transferred with one trigger. DMAEN remains enabled. Repeated burst-block 110, 111 CPU activity is interleaved with a block transfer. DMAEN remains enabled. transfer Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 385: Dma Single Transfer State Diagram
AND DMAEN = 1 Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd Figure 11-3. DMA Single Transfer State Diagram SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 386 In repeated block transfer mode, the DMAEN bit remains set after completion of the block transfer. The next trigger after the completion of a repeated block transfer triggers another block transfer. Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 387: Dma Block Transfer State Diagram
AND Trigger = 0] Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd Figure 11-4. DMA Block Transfer State Diagram SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 388 DMAEN bit, or by an (non)maskable interrupt (NMI) when ENNMI is set. In repeated burst- block mode, the CPU executes at 20% capacity continuously until the repeated burst-block transfer is stopped. Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 389: Dma Burst-Block Transfer State Diagram
2 × MCLK Burst State (release CPU for 2 × MCLK) Figure 11-5. DMA Burst-Block Transfer State Diagram SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 390: Initiating Dma Transfers
CPU finishes the currently executing read-modify-write operation before the DMA controller halts the CPU and the transfer begins (see Table 11-2). Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 391: Dma Trigger Operation
ROUNDROBIN bit is cleared, the channel priority returns to the default priority. DMA Priority Transfer Occurs New DMA Priority DMA0-DMA1-DMA2 DMA1 DMA2-DMA0-DMA1 DMA2-DMA0-DMA1 DMA2 DMA0-DMA1-DMA2 DMA0-DMA1-DMA2 DMA0 DMA1-DMA2-DMA0 SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 392: Maximum Single-Transfer Dma Cycle Time
DMAIV register, DMA0IFG is reset automatically. After the RETI instruction of the interrupt service routine is executed, the DMA2IFG generates another interrupt. Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 393 DMA0_HND ; Vector 2: DMA channel 0 ; Task starts here RETI ; Back to main program SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 394: Using Adc10 With The Dma Controller
CPU execution. The DAC12_xCTL DAC12IFG flag is automatically cleared when the DMA controller accesses the DAC12_xDAT register. Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 395: Dma Registers
Word, undefined Section 11.3.8 double word DMA5SZ DMA Channel 5 Transfer Size Read/write Word undefined Section 11.3.9 SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 396 Word, undefined Section 11.3.8 double word DMA7SZ DMA Channel 7 Transfer Size Read/write Word undefined Section 11.3.9 Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 397: Dmactl0 Register
00000b = DMA0TRIG0 00001b = DMA0TRIG1 00010b = DMA0TRIG2 ⋮ 11110b = DMA0TRIG30 11111b = DMA0TRIG31 SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 398: Dmactl1 Register
00000b = DMA2TRIG0 00001b = DMA2TRIG1 00010b = DMA2TRIG2 ⋮ 11110b = DMA2TRIG30 11111b = DMA2TRIG31 Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 399: Dmactl2 Register
00000b = DMA4TRIG0 00001b = DMA4TRIG1 00010b = DMA4TRIG2 ⋮ 11110b = DMA4TRIG30 11111b = DMA4TRIG31 SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 400: Dmactl3 Register
00000b = DMA6TRIG0 00001b = DMA6TRIG1 00010b = DMA6TRIG2 ⋮ 11110b = DMA6TRIG30 11111b = DMA6TRIG31 Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 401: Dmactl4 Register
DMAABORT is set. 0b = NMI does not interrupt DMA transfer. 1b = NMI interrupts a DMA transfer. SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 402: Dmaxctl Register
0b = Edge sensitive (rising edge) 1b = Level sensitive (high level) DMAEN DMA enable 0b = Disabled 1b = Enabled Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 403 DMA request. Software-controlled DMA start. DMAREQ is reset automatically. 0b = No DMA start 1b = Start DMA SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 404: Dmaxsa Register
Reading or writing bits 19-16 requires the use of extended instructions. When writing to DMAxSA with word instructions, bits 19-16 are cleared. Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 405: Dmaxda Register
Reading or writing bits 19-16 requires the use of extended instructions. When writing to DMAxDA with word instructions, bits 19-16 are cleared. SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 406: Dmaxsz Register
00002h = Two bytes or words are transferred. ⋮ 0FFFFh = 65535 bytes or words are transferred. Direct Memory Access (DMA) Controller Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 407: Dmaiv Register
0Eh = Interrupt Source: DMA channel 6; Interrupt Flag: DMA6IFG 10h = Interrupt Source: DMA channel 7; Interrupt Flag: DMA7IFG; Interrupt Priority: Lowest SLAU208Q – June 2008 – Revised March 2018 Direct Memory Access (DMA) Controller Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 408: Digital I/O Module
Digital I/O Introduction ..................12.2 Digital I/O Operation ..........12.3 I/O Configuration and LPMx.5 Low-Power Modes ..................12.4 Digital I/O Registers Digital I/O Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 409: Digital I/O Introduction
Ports PB, PC, PD, PE, and PF behave similarly. When reading from ports that contain less than the maximum bits possible, unused bits are read as zeros (similarly for port PJ). SLAU208Q – June 2008 – Revised March 2018 Digital I/O Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 410: I/O Configuration
PxDIR, PxREN, and PxOUT for proper I/O configuration. Table 12-1. I/O Configuration PxDIR PxREN PxOUT I/O Configuration Input Input with pulldown resistor Input with pullup resistor Output Digital I/O Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 411: Output Drive Strength Registers (Pxds)
RETI instruction of a Px interrupt service routine is executed, the set PxIFG flag generates another interrupt. This ensures that each transition is acknowledged. SLAU208Q – June 2008 – Revised March 2018 Digital I/O Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 412 ; Vector 4: Port 1 bit 1 ; Task starts here RETI ; Back to main program P1_0_HND ; Vector 2: Port 1 bit 0 Digital I/O Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 413: Configuring Unused Port Pins
LPMx.5 low-power modes that are available. With respect to the digital I/O, this section is applicable for both LPM3.5 and LPM4.5. SLAU208Q – June 2008 – Revised March 2018 Digital I/O Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 414 PxIFG flags. These flags can be used directly, or the corresponding PxIV register may be used. Note that the PxIFG flag cannot be cleared until the LOCKLPM5 bit has been cleared. Digital I/O Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 415 NOTE: It is possible that multiple events occurred on various ports. In these cases, multiple PxIFG flags will be set, and it cannot be determined which port has caused the I/O wakeup. SLAU208Q – June 2008 – Revised March 2018 Digital I/O Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 416: Digital I/O Registers
Port 3 Input Read only Byte Section 12.4.9 PBIN_L P3OUT or Port 3 Output Read/write Byte undefined Section 12.4.10 PBOUT_L Digital I/O Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 417 Port 7 Drive Strength Read/write Byte Section 12.4.13 PDDS_L P7SEL or Port 7 Port Select Read/write Byte Section 12.4.14 PDSEL_L SLAU208Q – June 2008 – Revised March 2018 Digital I/O Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 418 Port A Output Read/write Word undefined PAOUT_L Read/write Byte undefined PAOUT_H Read/write Byte undefined PADIR Port A Direction Read/write Word 0000h Digital I/O Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 419 Read/write Byte undefined PCOUT_H Read/write Byte undefined PCDIR Port C Direction Read/write Word 0000h PCDIR_L Read/write Byte PCDIR_H Read/write Byte SLAU208Q – June 2008 – Revised March 2018 Digital I/O Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 420 Read/write Word 0000h PESEL_L Read/write Byte PESEL_H Read/write Byte PFIN Port F Input Read only Word PFIN_L Read only Byte Digital I/O Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 421 PJDS_L Read/write Byte PJDS_H Read/write Byte PJSEL Port J Port Select Read/write Word 0000h PJSEL_L Read/write Byte PJSEL_H Read/write Byte SLAU208Q – June 2008 – Revised March 2018 Digital I/O Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 422: P1Iv Register
0Eh = Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG.6 10h = Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG.7; Interrupt Priority: Lowest Digital I/O Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 423: P2Iv Register
0Eh = Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG.6 10h = Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG.7; Interrupt Priority: Lowest SLAU208Q – June 2008 – Revised March 2018 Digital I/O Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 424: P1Ies Register
Field Type Reset Description P1IFG Port 1 interrupt flag 0b = No interrupt is pending 1b = Interrupt is pending Digital I/O Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 425: P2Ies Register
Field Type Reset Description P2IFG Port 2 interrupt flag 0b = No interrupt is pending 1b = Interrupt is pending SLAU208Q – June 2008 – Revised March 2018 Digital I/O Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 426: Pxin Register
Field Type Reset Description PxDIR Port x direction 0b = Port configured as input 1b = Port configured as output Digital I/O Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 427: Pxren Register
Reset Description PxSEL Port x function selection 0b = I/O function is selected 1b = Peripheral module function is selected SLAU208Q – June 2008 – Revised March 2018 Digital I/O Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 428: Port Mapping Controller
Topic Page ..............13.1 Port Mapping Controller Introduction ..............13.2 Port Mapping Controller Operation ..............13.3 Port Mapping Controller Registers Port Mapping Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 429: Port Mapping Controller Introduction
The use of mapping mnemonics to abstract the underlying PxMAPy values is recommended to allow simple portability between different devices. Table 13-1 shows some examples for mapping mnemonics of some common peripherals. SLAU208Q – June 2008 – Revised March 2018 Port Mapping Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 430: Examples For Port Mapping Mnemonics And Functions
USCI_B0 SPI slave transmit enable (direction controlled by USCI) PM_ANALOG Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals Port Mapping Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 431: Port Mapping Control Registers
Device dependent PxMAP45 Port Px.4/Port Px.5 mapping register Read/write Device dependent PxMAP67 Port Px.6/Port Px.7 mapping register Read/write Device dependent SLAU208Q – June 2008 – Revised March 2018 Port Mapping Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 432: Pmapkeyid Register
Table 13-7. PxMAPy Register Description Field Type Reset Description PMAPx Selects secondary port function. Settings are device-dependent; see the device- specific data sheet. Port Mapping Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 433: Cyclic Redundancy Check (Crc) Module
Cyclic Redundancy Check (CRC) Module Introduction ................14.2 CRC Standard and Bit Order ................14.3 CRC Checksum Generation ....................14.4 CRC Registers SLAU208Q – June 2008 – Revised March 2018 Cyclic Redundancy Check (CRC) Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 434: Lfsr Implementation Of Crc-Ccitt Standard, Bit 0 Is The Msb Of The Result
The CRC16 module therefore provides a bit reversed register pair for CRC16 operations to support both conventions. Cyclic Redundancy Check (CRC) Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 435: Crc Checksum Generation
If the checksum itself (with reversed bit order) is included into the CRC operation (as data written to CRCDI or CRCDIRB), the result in the CRCINIRES and CRCRESR registers must be zero. SLAU208Q – June 2008 – Revised March 2018 Cyclic Redundancy Check (CRC) Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 436: Implementation Of Crc-Ccitt Using The Crcdi And Crcinires Registers
; Result = 0? CRC_ERROR ; No, CRCRES <> 0: error ; Yes, CRCRES=0: ; information ok. ; Restore registers Cyclic Redundancy Check (CRC) Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 437 ; "9" #029B1h,&CRCINIRES ; compare result ; CRCRESR contains 08D94h &Success ; no error &Error ; to error handler SLAU208Q – June 2008 – Revised March 2018 Cyclic Redundancy Check (CRC) Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 438: Crc Registers
0006h CRCRESR_L Read only Byte 0007h CRCRESR_H Read only Byte Not available on MSP430F543x and MSP430F541x non-A versions. Cyclic Redundancy Check (CRC) Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 439: Crcdi Register
CRCINIRES and CRCRESR registers according to the CRC-CCITT standard. Reading the register returns the register CRCDI content. SLAU208Q – June 2008 – Revised March 2018 Cyclic Redundancy Check (CRC) Module Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 440: Crcinires Register
CRC-CCITT standard). The order of bits is reversed (for example, CRCINIRES[15] = CRCRESR[0]) compared to the order of bits in the CRCINIRES register (see example code). Cyclic Redundancy Check (CRC) Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 441: Aes Accelerator
AES accelerator..........................Topic Page ................15.1 AES Accelerator Introduction ................15.2 AES Accelerator Operation ..................15.3 AES_ACCEL Registers SLAU208Q – June 2008 – Revised March 2018 AES Accelerator Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 442: Aes Accelerator Block Diagram
AES accelerator block diagram. AESADIN AES128 Encryption/ AESAKEY Decryption Key Buffer Core AESADOUT Figure 15-1. AES Accelerator Block Diagram AES Accelerator SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 443: Aes State Array Input And Output
NOTE: When using a code debugger, the AES module does not stop its operation when program code is halted or single stepped. SLAU208Q – June 2008 – Revised March 2018 AES Accelerator Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 444: Encryption Process
AES Accelerator SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 445: Decryption Process Using Aesopx = 01
AESADIN after the results of the operation on the previous data were read from AESADOUT. When additional 16 data bytes are written, the module automatically starts the decryption using the key loaded in step 2. SLAU208Q – June 2008 – Revised March 2018 AES Accelerator Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 446: Decryption Process Using Aesopx = 10 And 11
AESKEYWR flag by software to indicate that the key is already valid. Afterward, the steps described in Section 15.2.2 to load the data and the rest of the process must be followed. AES Accelerator SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 447: Using The Aes Accelerator With Low-Power Modes
15.2.6 Implementing Block Cipher Modes All block cipher modes must be implemented in software. The AES accelerator supports only encrypt and decrypt functionality. SLAU208Q – June 2008 – Revised March 2018 AES Accelerator Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 448: Aes_Accel Registers
AESADIN AES accelerator data in register Read/write Word Section 15.3.4 00Ah AESADOUT AES accelerator data out register Read/write Word Section 15.3.5 AES Accelerator SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 449: Aesactl0 Register
10 = Generate first round key required for decryption. 11 = Decryption. The provided key is the first round key required for decryption. SLAU208Q – June 2008 – Revised March 2018 AES Accelerator Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 450: Aesastat Register
1 = All bytes written AESBUSY AES accelerator module busy; encryption, decryption, or key generation in progress. 0 = Not busy 1 = Busy AES Accelerator SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 451: Aesakey Register
Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1. SLAU208Q – June 2008 – Revised March 2018 AES Accelerator Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 452: Aesadin Register
AES data out byte n when AESADOUT is read as word. AES next data out byte when AESADOUT_L is read as byte. Do not mix word and byte access. AES Accelerator SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 453: Watchdog Timer (Wdt_A)
The enhanced watchdog timer, WDT_A, is implemented in all devices..........................Topic Page ..................16.1 WDT_A Introduction ..................... 16.2 WDT_A Operation ..................... 16.3 WDT_A Registers SLAU208Q – June 2008 – Revised March 2018 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 454: Wdt_A Introduction
~32-ms reset interval using the SMCLK. The user must setup or halt the WDT_A prior to the expiration of the initial reset interval. Watchdog Timer (WDT_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 455: Watchdog Timer Block Diagram
WDTIS2 WDTIS1 WDTIS0 X_CLK request Clock SMCLK request Request ACLK request Logic VLOCLK request Figure 16-1. Watchdog Timer Block Diagram SLAU208Q – June 2008 – Revised March 2018 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 456: Wdt_A Operation
In interval timer mode, the WDTIFG flag is reset automatically when the interrupt is serviced, or can be reset with software. Watchdog Timer (WDT_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 457: Clock Fail-Safe Feature
; Change watchdog timer interval MOV #WDTPW+WDTCNTCL+SSEL,&WDTCTL ; Stop the watchdog MOV #WDTPW+WDTHOLD,&WDTCTL ; Change WDT to interval timer mode, clock/8192 interval MOV #WDTPW+WDTCNTCL+WDTTMSEL+WDTIS2+WDTIS0,&WDTCTL SLAU208Q – June 2008 – Revised March 2018 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 458: Wdt_A Registers
Register Name Type Access Reset Section WDTCTL Watchdog Timer Control Read/write Word 6904h Section 16.3.1 WDTCTL_L Read/write Byte WDTCTL_H Read/write Byte Watchdog Timer (WDT_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 459: Wdtctl Register
110b = Watchdog clock source /(2 ) (15.625 ms at 32.768 kHz) 111b = Watchdog clock source /(2 ) (1.95 ms at 32.768 kHz) SLAU208Q – June 2008 – Revised March 2018 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 460: Timer_A
Timer_A module..........................Topic Page ..................17.1 Timer_A Introduction .................... 17.2 Timer_A Operation .................... 17.3 Timer_A Registers Timer_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 461: Timer_A Introduction
= 0. The suffix n, where n = 0 to 6, represents the specific capture/compare registers associated with the Timer_A instantiation. SLAU208Q – June 2008 – Revised March 2018 Timer_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 462: Timer_A Block Diagram
D Set Q Unit4 OUT6 Signal EQU0 Timer Clock Reset OUTMOD Copyright © 2016, Texas Instruments Incorporated Figure 17-1. Timer_A Block Diagram Timer_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 463: Timer_A Operation
TAxCCR0. In this scenario, the timer starts incrementing in the up direction from zero. SLAU208Q – June 2008 – Revised March 2018 Timer_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 464: Up Mode
However, one additional count may occur before the counter rolls to zero. Timer_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 465: Continuous Mode
TAxCCR1b TAxCCR1c TAxCCR0d TAxCCR0b TAxCCR0c 0FFFFh TAxCCR1a TAxCCR1d TAxCCR0a Figure 17-6. Continuous Mode Time Intervals SLAU208Q – June 2008 – Revised March 2018 Timer_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 466: Up/Down Mode
When the timer is counting in the up direction and the new period is less than the current count value, the timer begins counting down. However, one additional count may occur before the counter begins counting down. Timer_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 467: Output Unit In Up/Down Mode
Setting the SCS bit to synchronize the capture signal with the timer clock is recommended (see Figure 17-10). SLAU208Q – June 2008 – Revised March 2018 Timer_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 468: Capture Signal (Scs = 1)
Capture Read and No Capture Capture Clear Bit COV in Register TAxCCTLn Second Capture Idle Taken COV = 1 Figure 17-11. Capture Cycle Timer_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 469: Output Modes
The output is reset when the timer counts to the TAxCCRn value. It is set when the timer Reset/Set counts to the TAxCCR0 value. SLAU208Q – June 2008 – Revised March 2018 Timer_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 470: Output Example - Timer In Up Mode
Output Mode 7: Reset/Set EQU0 EQU1 EQU0 EQU1 EQU0 Interrupt Events TAIFG TAIFG TAIFG Figure 17-12. Output Example – Timer in Up Mode Timer_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 471: Output Example - Timer In Continuous Mode
Output Mode 6: Toggle/Set Output Mode 7: Reset/Set TAIFG EQU1 EQU0 TAIFG EQU1 EQU0 Interrupt Events Figure 17-13. Output Example – Timer in Continuous Mode SLAU208Q – June 2008 – Revised March 2018 Timer_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 472: Output Example - Timer In Up/Down Mode
NOR gate decodes output mode 0. A safe method for switching between output modes is to use output mode 7 as a transition state: #OUTMOD_7,&TA0CCTL1 ; Set output mode=7 #OUTMOD,&TA0CCTL1 ; Clear unwanted bits Timer_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 473: Capture/Compare Interrupt Flag
TAxIV register, TAxCCR1 CCIFG is reset automatically. After the RETI instruction of the interrupt service routine is executed, the TAxCCR2 CCIFG flag generates another interrupt. SLAU208Q – June 2008 – Revised March 2018 Timer_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 474 ; Task starts here RETI ; Back to main program CCIFG_1_HND ; Vector 2: TA0CCR1 ; Task starts here RETI ; Back to main program Timer_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 475: Timer_A Registers
0000h Section 17.3.4 TAxIV Timer_Ax Interrupt Vector Read only Word 0000h Section 17.3.5 TAxEX0 Timer_Ax Expansion 0 Read/write Word 0000h Section 17.3.6 SLAU208Q – June 2008 – Revised March 2018 Timer_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 476: Taxctl Register
Timer_A interrupt enable. This bit enables the TAIFG interrupt request. 0b = Interrupt disabled 1b = Interrupt enabled TAIFG Timer_A interrupt flag 0b = No interrupt pending 1b = Interrupt pending Timer_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 477: Taxr Register
Table 17-5. TAxR Register Description Field Type Reset Description 15-0 TAxR Timer_A register. The TAxR register is the count of Timer_A. SLAU208Q – June 2008 – Revised March 2018 Timer_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 478: Taxcctln Register
Output. For output mode 0, this bit directly controls the state of the output. 0b = Output low 1b = Output high Timer_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 479 0b = No capture overflow occurred 1b = Capture overflow occurred CCIFG Capture/compare interrupt flag 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 Timer_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 480: Taxccrn Register
0Ch = Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG 0Eh = Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest Timer_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 481: Taxex0 Register
011b = Divide by 4 100b = Divide by 5 101b = Divide by 6 110b = Divide by 7 111b = Divide by 8 SLAU208Q – June 2008 – Revised March 2018 Timer_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 482: Timer_B
(see the device-specific data sheet). This chapter describes the operation and use of the Timer_B module..........................Topic Page ..................18.1 Timer_B Introduction .................... 18.2 Timer_B Operation .................... 18.3 Timer_B Registers Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 483: Timer_B Introduction
Timer_B TBxCCRn registers are double-buffered and can be grouped. • All Timer_B outputs can be put into a high-impedance state. • The SCCI bit function is not implemented in Timer_B. SLAU208Q – June 2008 – Revised March 2018 Timer_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 484: Timer_B Block Diagram
UP/DOWN CCR1 Set TBxCCR6 CCIFG Output D Set Q OUT6 Signal Unit6 EQU0 Timer Clock Reset OUTMOD Figure 18-1. Timer_B Block Diagram Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 485: Timer_B Operation
TBxCL0. In this scenario, the timer starts incrementing in the up direction from zero. SLAU208Q – June 2008 – Revised March 2018 Timer_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 486: Up Mode
If the new period is less than the current count value, the timer rolls to zero. However, one additional count may occur before the counter rolls to zero. Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 487: Continuous Mode
TBxCL1b TBxCL1c TBxCL0d TBxCL0b TBxCL0c TBxR (max) TBxCL1a TBxCL1d TBxCL0a EQU0 Interrupt EQU1 Interrupt Figure 18-6. Continuous Mode Time Intervals SLAU208Q – June 2008 – Revised March 2018 Timer_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 488: Up/Down Mode
TBxCL0 load mode is immediate, the timer continues its descent until it reaches zero. The new period takes effect after the counter counts down to zero. Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 489: Output Unit In Up/Down Mode
The input signal level can be read at any time from the CCI bit. Devices may have different signals connected to CCIxA and CCIxB. See the device-specific data sheet for the connections of these signals. SLAU208Q – June 2008 – Revised March 2018 Timer_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 490: Capture Signal (Scs = 1)
Capture Read and No Capture Capture Clear Bit COV in Register TBxCCTLn Second Capture Idle Taken COV = 1 Figure 18-11. Capture Cycle Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 491: Tbxcln Load Events
TBxCCRn to TBxCLn when TBxR counts to the old TBxCL0 value or to 0 for up/down mode. New data is transferred from TBxCCRn to TBxCLn when TBxR counts to the old TBxCLn value. SLAU208Q – June 2008 – Revised March 2018 Timer_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 492: Compare Latch Operating Modes
The output is reset when the timer counts to the TBxCLn value. It is set when the timer Reset/Set counts to the TBxCL0 value. Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 493: Output Example - Timer In Up Mode
Output Mode 7: Reset/Set EQU0 EQU1 EQU0 EQU1 EQU0 Interrupt Events TBIFG TBIFG TBIFG Figure 18-12. Output Example – Timer in Up Mode SLAU208Q – June 2008 – Revised March 2018 Timer_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 494: Output Example - Timer In Continuous Mode
Output Mode 6: Toggle/Set Output Mode 7: Reset/Set Interrupt Events TBIFG EQU1 EQU0 TBIFG EQU1 EQU0 Figure 18-13. Output Example – Timer in Continuous Mode Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 495: Output Example - Timer In Up/Down Mode
NOR gate decodes output mode 0. A safe method for switching between output modes is to use output mode 7 as a transition state: #OUTMOD_7,&TBCCTLx ; Set output mode=7 #OUTMOD,&TBCCTLx ; Clear unwanted bits SLAU208Q – June 2008 – Revised March 2018 Timer_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 496: Capture/Compare Tbxccr0 Interrupt Flag
The latencies are: • Capture/compare block CCR0: 11 cycles • Capture/compare blocks CCR1 to CCR6: 16 cycles • Timer overflow TBIFG: 14 cycles Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 497 ; Task starts here RETI ; Back to main program CCIFG_1_HND ; Vector 2: TB0CCR1 ; Task starts here RETI ; Back to main program SLAU208Q – June 2008 – Revised March 2018 Timer_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 498: Timer_B Registers
0000h Section 18.3.4 TBxIV Timer_B Interrupt Vector Read only Word 0000h Section 18.3.5 TBxEX0 Timer_B Expansion 0 Read/write Word 0000h Section 18.3.6 Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 499: Tbxctl Register
TBIE Timer_B interrupt enable. This bit enables the TBIFG interrupt request. 0b = Interrupt disabled 1b = Interrupt enabled SLAU208Q – June 2008 – Revised March 2018 Timer_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 500 Table 18-6. TBxCTL Register Description (continued) Field Type Reset Description TBIFG Timer_B interrupt flag 0b = No interrupt pending 1b = Interrupt pending Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 501: Tbxr Register
Table 18-7. TBxR Register Description Field Type Reset Description 15-0 TBxR Timer_B register. The TBxR register is the count of Timer_B. SLAU208Q – June 2008 – Revised March 2018 Timer_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 502: Tbxcctln Register
CCIFG flag. 0b = Interrupt disabled 1b = Interrupt enabled Undef Capture/compare input. The selected input signal can be read by this bit. Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 503 0b = No capture overflow occurred 1b = Capture overflow occurred CCIFG Capture/compare interrupt flag 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 Timer_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 504: Tbxccrn Register
Timer_B Register, TBR. Capture mode: The Timer_B Register, TBR, is copied into the TBxCCRn register when a capture is performed. Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 505: Tbxiv Register
0Ch = Interrupt Source: Capture/compare 6; Interrupt Flag: TBxCCR6 CCIFG 0Eh = Interrupt Source: Timer overflow; Interrupt Flag: TBxCTL TBIFG; Interrupt Priority: Lowest SLAU208Q – June 2008 – Revised March 2018 Timer_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 506: Tbxex0 Register
011b = Divide by 4 100b = Divide by 5 101b = Divide by 6 110b = Divide by 7 111b = Divide by 8 Timer_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 507: Timer_D
Timer_D is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes Timer_D..........................Topic Page ..................19.1 Timer_D Introduction .................... 19.2 Timer_D Operation .................... 19.3 Timer_D Registers SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 508: Timer_D Introduction
Timer_D supports external fault input, external clear input, and signal. See the TEC chapter detailed information. • Timer_D can synchronize with a second timer instance when available. See the TEC chapter detailed information. Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 509: Timer_D Block Diagram
CCIFG TD6CMB CH0EVNT Output CH5EVNT Set Q Unit6 OUT6 Signal Timer Clock EXTCLR Reset CH6EVNT EQU6 OUTMODx Figure 19-1. Timer_D Block Diagram SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 510: Timer_D Operation
, for the selectable lengths is 0FFh, 03FFh, 0FFFh, and 0FFFFh, respectively. Data (max) written to the TDxR register in 8-, 10-, and 12-bit mode is right justified with leading zeros. Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 511: High Resolution Clock Generator
+1 or -1 at a time. All other settings must not be altered manually. Using TDHCLKTRIMx allows changing the frequency by at least ±20% from TDHCLKTRIM = 64. SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 512: Factory Preprogrammed Frequency And Tdhmx, Tdhclkcr Bit Settings
If the TDHREGEN bit is cleared, the continuous regulation is stopped and the high-resolution frequency enters free-running mode. The latest settings are kept. Example 20-1 shows how to set the timer to high-resolution mode. Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 513: Timer Modes
The timer repeatedly counts from zero to the value selected by the TDCNTLx bits. Up/down The timer repeatedly counts from zero up to the value of TDxCL0 and then back down to zero. SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 514: Up Mode
(see Figure 19-5). (max) The compare latch TDxCL0 works the same way as the other capture/compare registers. (max) Figure 19-5. Continuous Mode Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 515: Continuous Mode Flag Setting
TDxCL0 value. When the sum of the previous TDCLx value plus t is greater than the TDCL0 data, the old TDCL0 value must be subtracted to obtain the correct time interval. SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 516: Tdxccr0 Pwm Generation Under Continuous Mode
If this is not desired, the TDCLR bit must be used to clear the direction. The TDCLR bit also clears the TDR value and the TDCLK divider. Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 517: Up/Down Mode Flag Setting
= Cycle time of the timer clock timer TDCLx = Content of compare latch x The ability to simultaneously load grouped compare latches ensures the dead times. SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 518: Output Unit In Up/Down Mode
TDCCRx register is programmed to values beyond the recommended range of values dependent on the OUTMODx setting. Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 519: High-Resolution Mode Limitation (Tdhen = 1) - Minimum Duty Cycle
TDHMx = 00: | TDCCR - TDCCR | > 7 if TDHMx = 01: | TDCCR - TDCCR | > 15 SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 520: Controlling Rising And Falling Edge Of Pwm Output In Up Mode
TDxCCRx registers are paired. Combining two pairs of CCRx channels to two PWM outputs can be used to generate non-overlapping PWM channels. Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 521: Deadband Generation (Tdxcmb = 1)
Setting the SCS bit to synchronize the capture signal with the timer clock is recommended (see Figure 19-14). In high-resolution mode, the SCS bit is ignored. SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 522: Capture Signal (Scs = 1)
19-16). The third capture event again shifts the TDCCRx register content to the TDCLx register. The first capture value is no longer available. Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 523: Sequential Capture Events In Dual Capture Mode
TDCCRx = 3rd TDCCRx = 2nd TDCLx = 2nd TDCLx = 1st COV = 1 Figure 19-17. COV in Dual Capture Mode SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 524: Tdclx Load Events
Table 19-6. Compare Latch Operating Modes TDCLGRPx Grouping Update Control None Individual TDxCL1+TDxCL2 TDxCCR1 TDxCL3+TDxCL4 TDxCCR3 TDxCL5+TDxCL6 TDxCCR5 TDxCL1+TDxCL2+TDxCL3 TDxCCR1 TDxCL4+TDxCL5+TDxCL6 TDxCCR4 TDxCL0+TDxCL1+TDxCL2+TDxCL3+TDxCL4+TDxCL5+TDxCL6 TDxCCR1 Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 525: Output Modes
Reset events: Timer counts to TDyCLx, external fault (TECyFLTx). It remains reset until another output mode is selected and affects the output. SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 526 TD6CMB = 1: Reset events: Timer counts to TDyCL6, external fault (TECyFLT6). Set events: Timer counts to TDyCL5, external fault (TECyFLT5), external clear (TECyCLR).TDxCMB=0: Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 527: Output Example, Channel 1 - Timer In Up Mode
Output Mode 7: Reset/Set EQU0 EQU1 EQU0 EQU1 EQU0 Interrupt Events TDIFG TDIFG TDIFG Figure 19-18. Output Example, Channel 1 – Timer in Up Mode SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 528: Output Example, Channel 1 - Timer In Up Mode With External Fault Signal
EQU1 EQU0 EQU1 EQU0 Interrupt Events TECxFLT1 Figure 19-19. Output Example, Channel 1 - Timer in Up Mode With External Fault Signal Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 529: Output Example - Timer In Up Mode With External Timer Clear Signal
Output Mode 7: Reset/Set EQU0 EQU1 EQU0 EQU1 EQU0 TECEXCLR Figure 19-20. Output Example - Timer in Up Mode with External Timer Clear Signal SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 530: Output Example - Timer In Continuous Mode
Output Mode 6: Toggle/Set Output Mode 7: Reset/Set Interrupt Events TDIFG EQU1 EQU0 TDIFG EQU1 EQU0 Figure 19-21. Output Example – Timer in Continuous Mode Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 531: Output Example - Timer In Up/Down Mode
NOR gate decodes output mode 0. A safe method for switching between output modes is to use output mode 7 as a transition state: BIS #OUTMOD_7,&TDCCTLx ; Set output mode=7 BIC #OUTMODx,&TDCCTLx ; Clear unwanted bits SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 532: Capture/Compare Tdxccr0 Interrupt Flag
TDxCCR2 CCIFG flag generates another interrupt. Write access of the TDIV register clears all pending interrupt conditions and flags. Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 533 ; 9 cycles may be saved if another interrupt is pending CCIFG_1_HANDLER ; Vector 2: Module 1 ; Task starts here JMP TD_HANDLER ; Look for pending ints SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 534: Timer_D Registers
Section 19.3.9 003Ch TDxHINT Timer_D High-Resolution Interrupt Read/write On POR Section 19.3.10 003Eh TDxIV Timer_D Interrupt Vector Read only On POR Section 19.3.11 Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 535: Tdxctl0 Register
Reserved. Always reads as 0. TDSSELx Timer_D clock source select 00b = TDCLK 01b = ACLK 10b = SMCLK 11b = Inverted TDCLK SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 536 Timer_D interrupt enable. This bit enables the TDIFG interrupt request. 0b = Interrupt disabled 1b = Interrupt enabled TDIFG Timer_D interrupt flag 0b = No interrupt pending 1b = Interrupt pending Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 537: Tdxctl1 Register
00b = External clock source is used 01b = High-resolution local clock is used 10b = Auxiliary clock source from another timer instance is used 11b = Reserved SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 538: Tdxctl2 Register
0b = Single capture mode 1b = Dual capture mode TDCAPM0 Capture mode of channel 0 0b = Single capture mode 1b = Dual capture mode Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 539: Tdxr Register
Timer_D register. The TDxR register is the count of Timer_D. In high-resolution mode, the bits 0 to 3 return zero when the TDxR register is read. SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 540: Tdxcctln Register
CCIFG flag. 0b = Interrupt disabled 1b = Interrupt enabled Capture/compare input. The selected input signal can be read by this bit. Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 541 0b = No capture overflow occurred 1b = Capture overflow occurred CCIFG Capture/compare interrupt flag 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 542: Tdxccrn Register
Timer_D capture/compare latch register. TDCLx register holds the comparison value in compare mode. In capture mode the register content of TDxCCRx is copied into TDxCLx at each capture event. Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 543: Tdxhctl0 Register
Whenever a high-resolution TDAUXCLK from another Timer_D instance is used, this bit must also be set. 0b = High-resolution mode disable 1b = High-resolution mode enable SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 544: Tdxhctl1 Register
TDHCLKTRIMx bits is approximately half of the TDHCLKSRx bits in each clock range. If TDHREGEN = 1, these register bits are modified by hardware. Reserved Reserved. Always reads as 0. Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 545: Tdxhint Register
If the bit is set until cleared by writing o it. 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 Timer_D Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 546: Tdxiv Register
18h = Interrupt Source: High-resolution frequency unlocked; Interrupt Flag: TDxHINT TDHUNLKIFG 1Ah = Reserved 1Ch = Reserved 1Eh = Reserved ; Interrupt Priority: Lowest Timer_D SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 547: Timer Event Control (Tec)
TEC Module..........................Topic Page ............... 20.1 Timer Event Control Introduction ....................20.2 TEC Operation ....................20.3 TEC Registers SLAU208Q – June 2008 – Revised March 2018 Timer Event Control (TEC) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 548: Timer Event Control Block Diagram
00 01 10 11 TECAXCLRIN EQU6 CH6EVNT TEC CCR6 Block TECxFLTEN6 TECxFLT6 TECxFLTHLD6 Figure 20-1. Timer Event Control Block Diagram Timer Event Control (TEC) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 549: Tec Operation
TECXFLTHLDx control bit holds the external fault signal. Clearing the TECXFLTxSTA status bits also resets the held signal back to zero. SLAU208Q – June 2008 – Revised March 2018 Timer Event Control (TEC) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 550: External Input Events Affect Timer_D Output
Figure 20-4 shows the interconnection between TEC and Timer_D module. See the Timer_D chapter for more Timer_D module information. Timer Event Control (TEC) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 551: Module Level Connection Between Tec And Timer_D
OUTMODx TEC - CCR6 Block EQU6 CH6EVNT TECXFLTEN6 TECXFLT6 TECXFLTHLD6 Figure 20-4. Module Level Connection Between TEC and Timer_D SLAU208Q – June 2008 – Revised March 2018 Timer Event Control (TEC) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 552: Synchronization Mechanism Between Timer_D Instances
TD1CCTL2 |= OUTMOD_7; // TD1CCR2, Reset/Set // Start timers and select Up-mode TD0CTL0 |= MC_1 + TDCLR; // up-mode, start timer Timer Event Control (TEC) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 553: Synchronization Between Timer Instances
EXTCLR TECEXCLRHLD Timer Clock CLKSELx = 0 00 01 10 11 TECAXCLRIN TDAUXCLK Figure 20-5. Synchronization Between Timer Instances SLAU208Q – June 2008 – Revised March 2018 Timer Event Control (TEC) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 554: Timer Event Control Interrupts
Write access of the TECxIV register clears all pending interrupt conditions and flags. Timer Event Control (TEC) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 555: Tec Registers
Timer Event Control External Interrupt Read/write 0000h Section 20.3.5 000Ah TECxIV Timer Event Control Interrupt Vector Read only 0000h Section 20.3.6 SLAU208Q – June 2008 – Revised March 2018 Timer Event Control (TEC) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 556: Tecxctl0 Register
External fault signal hold bit for CE3 0b = External fault signal is not held 1b = External fault signal is held Timer Event Control (TEC) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 557 External fault signal hold bit for CE0 0b = External fault signal is not held 1b = External fault signal is held SLAU208Q – June 2008 – Revised March 2018 Timer Event Control (TEC) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 558: Tecxctl1 Register
0b = Selects falling edge in edge sensitive or low level in level sensitive 1b = Selects rising edge in edge sensitive or high level in level sensitive Timer Event Control (TEC) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 559 0b = Selects falling edge in edge sensitive or low level in level sensitive 1b = Selects rising edge in edge sensitive or high level in level sensitive SLAU208Q – June 2008 – Revised March 2018 Timer Event Control (TEC) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 560: Tecxctl2 Register
Auxiliary clock source selection bits 00b = Clock input from a Timer_D master instance 01b = Reserved 10b = Reserved 11b = Reserved Timer Event Control (TEC) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 561: Tecxsta Register
If the bit is set it remains set until cleared by writing 0 to it. 0b = No external fault detected 1b = External fault detected SLAU208Q – June 2008 – Revised March 2018 Timer Event Control (TEC) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 562: Tecxint Register
If the bit is set it remains set until cleared by reading it or writing a 0 to it. 0b = No interrupt pending 1b = Interrupt pending Timer Event Control (TEC) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 563: Tecxiv Register
04h = Interrupt Source: External clear; Interrupt Flag: TECEXCLRIFG 06h = Interrupt Source: Auxiliary clear; Interrupt Flag: TECAXCLRIFG; Interrupt Priority: Lowest SLAU208Q – June 2008 – Revised March 2018 Timer Event Control (TEC) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 564: Real-Time Clock (Rtc) Overview
See the device-specific data sheet. Total adjustment range of offset calibration plus temperature compensation. See the RTC_C chapter for details. Real-Time Clock (RTC) Overview SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 565: Real-Time Clock (Rtc_A)
This chapter describes the RTC_A module..........................Topic Page ..................22.1 RTC_A Introduction ....................22.2 RTC_A Operation ....................22.3 RTC_A Registers SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 566: Rtc_A Introduction
Real-time clock initialization Most RTC_A module registers have no initial condition. These registers must be configured by user software before use. Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 567: Rtc_A
16-bit overflow/hour changed 24-bit overflow/midnight 32-bit overflow/noon Calendar RTCYEARH RTCYEARL RTCMON RTCDAY Set_RTCAIFG Alarm RTCADOW RTCADAY RTCAHOUR RTCAMIN Figure 22-1. RTC_A SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 568: Rtc_A Operation
Changing the state of RTCBCD clears the seconds, minutes, hours, day-of-week, and year counts and sets day-of-month and month counts to 1. In addition, RT0PS and RT1PS are cleared. Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 569 Because the system clock may be asynchronous to the RTC_A clock source, special care must be taken when accessing the real-time clock registers. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 570: Real-Time Clock Interrupts
The RTCRDY bit sources the real-time clock interrupt, RTCRDYIFG, and is useful in synchronizing the read of time registers with the system clock. Setting the RTCRDYIE bit enables the interrupt. Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 571 ; Task starts here RT0PSIFG_HND ; Vector 8: RT0PSIFG ; Task starts here RT1PSIFG_HND ; Vector A: RT1PSIFG ; Task starts here SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 572: Real-Time Clock Calibration
RTCCAL = 0h would result in a -4 ppm decrease in frequency. Similarly, setting RTCCALS = 1 and RTCCAL = 0h would result in a +8 ppm increase in frequency. Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 573 Because the frequency change is small and infrequent over a very long time interval, it can be difficult to observe. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 574: Rtc_A Registers
Real-Time Clock Hour, Day of Week Read/write Word undefined or RTCNT34 Real-Time Counter 3, 4 RTCHOUR Real-Time Clock Hour Read/write Byte undefined Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 575 Real-Time Clock Day of Week Alarm Read/write Byte undefined or RTCADOWDAY_L RTCADAY Real-Time Clock Day of Month Alarm Read/write Byte undefined or RTCADOWDAY_H SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 576: Rtcctl0 Register
RTCRDYIFG Real-time clock read ready flag 0b = RTC cannot be read safely. 1b = RTC can be read safely. Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 577: Rtcctl1 Register
00b = Minute changed 01b = Hour changed 10b = Every day at midnight (00:00) 11b = Every day at noon (12:00) SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 578: Rtcctl2 Register
00b = No frequency output to RTCCLK pin 01b = 512 Hz 10b = 256 Hz 11b = 1 Hz Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 579: Rtcnt1 Register
RTCNT4 Table 22-9. RTCNT4 Register Description Field Type Reset Description RTCNT4 undefined The RTCNT4 register is the count of RTCNT4. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 580: Rtcsec Register – Calendar Mode With Hexadecimal Format
Seconds – high digit (0 to 5) Seconds – low digit undefined Seconds – low digit (0 to 9) Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 581: Rtcmin Register – Calendar Mode With Hexadecimal Format
Minutes – high digit (0 to 5) Minutes – low digit undefined Minutes – low digit (0 to 9) SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 582: Rtchour Register – Calendar Mode With Hexadecimal Format
Hours – high digit (0 to 2) Hours – low digit undefined Hours – low digit (0 to 9) Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 583: Rtcdow Register – Calendar Mode
Day of month – high digit (0 to 3) digit Day of month – low undefined Day of month – low digit (0 to 9) digit SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 584: Rtcmon Register – Calendar Mode With Hexadecimal Format
Month – high digit (0 or 1) Month – low digit undefined Month – low digit (0 to 9) Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 585: Rtcyearl Register – Calendar Mode With Hexadecimal Format
Reset Description Decade undefined Decade (0 to 9) Year – lowest digit undefined Year – lowest digit (0 to 9) SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 586: Rtcyearh Register – Calendar Mode With Hexadecimal Format
Century – high digit (0 to 4) Century – low digit undefined Century – low digit (0 to 9) Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 587: Rtcamin Register – Calendar Mode With Hexadecimal Format
Minutes – high digit (0 to 5) Minutes – low digit undefined Minutes – low digit (0 to 9) SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 588: Rtcahour Register – Calendar Mode With Hexadecimal Format
Hours – high digit (0 to 2) Hours – low digit undefined Hours – low digit (0 to 9) Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 589: Rtcadow Register
1b = This alarm register is enabled Always 0 Day of month undefined Day of month (1 to 28, 29, 30, 31) SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 590: Rtcaday Register – Calendar Mode With Bcd Format
Day of month – high digit (0 to 3) digit Day of month – low undefined Day of month – low digit (0 to 9) digit Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 591: Rtcps0Ctl Register
1b = Interrupt enabled RT0PSIFG Prescale timer 0 interrupt flag 0b = No time event occurred 1b = Time event occurred SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 592: Rtcps1Ctl Register
1b = Interrupt enabled RT1PSIFG Prescale timer 1 interrupt flag 0b = No time event occurred 1b = Time event occurred Real-Time Clock (RTC_A) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 593: Rt0Ps Register
0Ah = Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG 0Ch = Reserved 0Eh = Reserved 10h = Reserved ; Interrupt Priority: Lowest SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock (RTC_A) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 594: Real-Time Clock B (Rtc_B)
This chapter describes the RTC_B module..........................Topic Page ..............23.1 Real-Time Clock RTC_B Introduction ....................23.2 RTC_B Operation ....................23.3 RTC_B Registers Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 595: Real-Time Clock Rtc_B Introduction
Real-time clock initialization Most RTC_B module registers have no initial condition. These registers must be configured by user software before use. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 596: Rtc_B Block Diagram
Calendar RTCYEARH RTCYEARL RTCMON RTCDAY Set_RTCAIFG Alarm RTCADOW RTCADAY RTCAHOUR RTCAMIN Figure 23-1. RTC_B Block Diagram Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 597: Rtc_B Operation
RTCAIE, RTCAIFG, and AE bits before writing initial or new time values to the RTC time registers. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 598: Reading Or Writing Real-Time Clock Registers
In addition, all flags can be cleared by software. Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 599 ; Back to main program RTCAIFG_HND ; Vector 6: RTCAIFG Flag ; Task starts here RETI ; Back to main program SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 600: Real-Time Clock Calibration
Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 601: Real-Time Clock Operation In Lpm3.5 Low-Power Mode
If a fault occurs during LPM3.5 and the RTCOFIE was set before entering LPM3.5, a wake-up event is issued. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 602: Rtc_B Registers
Real-Time Clock Hour Read/write Byte undefined retained or RTCTIM1_L RTCDOW Real-Time Clock Day of Week Read/write Byte undefined retained or RTCTIM1_H Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 603 BCD2BIN BCD-to-Binary Conversion Register Read/write Word not retained Do not access the RTCYEAR register in byte mode. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 604: Rtcctl0 Register
Real-time clock ready interrupt flag 0b = RTC cannot be read safely 1b = RTC can be read safely Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 605: Rtcctl1 Register
00b = Minute changed 01b = Hour changed 10b = Every day at midnight (00:00) 11b = Every day at noon (12:00) SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 606: Rtcctl2 Register
00b = No frequency output to RTCCLK pin 01b = 512 Hz 10b = 256 Hz 11b = 1 Hz Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 607: Rtcsec Register – Hexadecimal Format
Seconds – high digit. Valid values are 0 to 5. Seconds – low digit undefined Seconds – low digit. Valid values are 0 to 9. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 608: Rtcmin Register – Hexadecimal Format
Minutes – high digit. Valid values are 0 to 5. Minutes – low digit undefined Minutes – low digit. Valid values are 0 to 9. Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 609: Rtchour Register – Hexadecimal Format
Hours – high digit. Valid values are 0 to 2. Hours – low digit undefined Hours – low digit. Valid values are 0 to 9. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 610: Rtcdow Register
Day of month – low undefined Day of month – low digit. Valid values are 0 to 9. digit Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 611: Rtcmon Register – Hexadecimal Format
Month – high digit. Valid values are 0 or 1. Month – low digit undefined Month – low digit. Valid values are 0 to 9. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 612: Rtcyear Register – Hexadecimal Format
Decade. Valid values are 0 to 9. Year – lowest digit undefined Year – lowest digit. Valid values are 0 to 9. Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 613: Rtcamin Register – Hexadecimal Format
Minutes – high digit. Valid values are 0 to 5. Minutes – low digit undefined Minutes – low digit. Valid values are 0 to 9. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 614: Rtcahour Register – Hexadecimal Format
Hours – high digit. Valid values are 0 to 2. Hours – low digit undefined Hours – low digit. Valid values are 0 to 9. Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 615: Rtcadow Register
1b = This alarm register is enabled Always reads as 0. Day of week undefined Day of week. Valid values are 0 to 6. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 616: Rtcaday Register – Hexadecimal Format
Day of month – low undefined Day of month – low digit. Valid values are 0 to 9. digit Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 617: Rtcps0Ctl Register
1b = Interrupt enabled RT0PSIFG Prescale timer 0 interrupt flag 0b = No time event occurred 1b = Time event occurred SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 618: Rtcps1Ctl Register
Prescale timer 1 interrupt flag. In modules supporting LPMx.5 this interrupt can be used as LPMx.5 wake-up event. 0b = No time event occurred 1b = Time event occurred Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 619: Rtcps0 Register
Figure 23-29. RTCPS1 Register RT1PS Table 23-29. RTCPS1 Register Description Field Type Reset Description RT1PS undefined Prescale timer 1 counter value SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 620: Rtciv Register
0Ah = Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG 0Ch = Interrupt Source: RTC oscillator failure; Interrupt Flag: RTCOFIFG 0Eh = Reserved; Interrupt Priority: Lowest Real-Time Clock B (RTC_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 621: Bin2Bcd Register
15-0 BCD2BINx Read: 12-bit binary conversion of previously written 16-bit BCD number Write: 16-bit BCD number to be converted SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock B (RTC_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 622: Real-Time Clock C (Rtc_C)
Real-Time Clock (RTC_C) Introduction ....................24.2 RTC_C Operation ........... 24.3 RTC_C Operation - Device-Dependent Features ....................24.4 RTC_C Registers Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 623: Real-Time Clock (Rtc_C) Introduction
Most RTC_C module registers have no initial condition. These registers must be configured by user software before use. Figure 24-1 shows the RTC_C block diagram. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 624: Rtc_C Block Diagram (Rtcmode = 1)
Alarm RTCADOW RTCADAY RTCAHOUR RTCAMIN Copyright © 2016, Texas Instruments Incorporated Figure 24-1. RTC_C Block Diagram (RTCMODE = 1) Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 625: Rtc_C Operation
RTCADAY, RTCAHOUR, and RTCAMIN, the alarm is enabled. When enabled, the RTCAIFG is set when the time count transitions from 06:29:59 to 06:30:00 and the RTCDAY equals 5. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 626: Real-Time Clock Protection
; Write into RTCCTL0 with correct key in word mode MOV.B #00h, &RTCCTL0_H ; Write incorrect key to lock RTC_C Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 627: Reading Or Writing Real-Time Clock Registers
32768 Hz, so intervals of 16384 Hz, 8192 Hz, 4096 Hz, 2048 Hz, 1024 Hz, 512 Hz, 256 Hz, or 128 Hz are possible. Setting the RT0PSIE bit enables the interrupt. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 628 ; Back to main program RT1PSIFG_HND ; Vector C: RT1PSIFG ; Task starts here RETI ; Back to main program Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 629: Real-Time Clock Calibration For Crystal Offset Error
RT0PS interrupt triggered by RT0PS – Q1 to Q7 (RT0IPx ≠ 000) is based on the calibrated clock. RT1PS interrupt (RT1PSIFG) and RTC counter interrupt (RTCTEVIFG) are also based on the calibrated clock. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 630: Real-Time Clock Compensation For Crystal Temperature Drift
RTCTCMP again when RTCTCRDY is set. Figure 24-2 shows the scheme for real-time clock offset error calibration and temperature compensation. Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 631: Rtc_C Offset Error Calibration And Temperature Compensation Scheme
RTCTCMP register. The value written into RTCTCMP in this case would be effective until it is updated again by software. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 632: Real-Time Clock Operation In Lpm3.5 Low-Power Mode
If a fault occurs during LPM3.5 and the RTCOFIE was set before entering LPM3.5, a wake-up event is issued. Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 633 ISR. If this bit is clear, these logics are writable and can be reset by PUC, POR, and BOR. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 634: Rtc_C Operation - Device-Dependent Features
Set_RTCTEVIFG 16-bit overflow 24-bit overflow 32-bit overflow Figure 24-3. RTC_C Functional Block Diagram in Counter Mode (RTCMODE = 0) Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 635 For example, if RTPS0 is being updated, set RTCPS1HOLD = 1, and if RTPS1 is being updated, set RTCHOLD = 1. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 636 The RTCOFIFG bit flags a failure of the 32-kHz crystal oscillator. It's main purpose is to wake-up the CPU from LPM3.5 in case an oscillator failure occurred. Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 637: Real-Time Clock Event/Tamper Detection With Time Stamp
Table 24-1 shows how to use the DIR, REN, and OUT bits in RTCCAPxCTL for proper configuration of RTCCAPx pins. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 638: Rtccapx Pin Configuration
(one per tamper source). When RTCIV is read, the RTCCAPIFG is cleared but not the status flags (CAPEV bits). Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 639: Rtc_C Registers
Real-Time Prescale Timer 0, 1 RTCPS Read/write Word none retained Counter Real-Time Prescale Timer 0 RT0PS Read/write Byte none retained Counter or RTCPS_L SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 640 BCD-to-binary conversion BCD2BIN Read/write Word 0000h not retained register Do not access the year register RTCYEAR in byte mode. Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 641: Rtc_C Event And Tamper Detection Registers
Word undefined retained RTCCNT3 Real-Time Counter 3 Read/write Byte undefined retained RTCCNT4 Real-Time Counter 4 Read/write Byte undefined retained SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 642: Rtcctl0_L Register
Real-time clock ready interrupt flag 0b = RTC cannot be read safely 1b = RTC can be read safely Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 643: Rtcctl0_H Register
Real-time clock key. This register should be written with A5h to unlock RTC_C. A write with a value other than A5h locks the module. A read from this register always returns 96h. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 644: Rtcctl1 Register
Counter Mode (RTCMODE = 0) 00b = 8-bit overflow 01b = 16-bit overflow 10b = 24-bit overflow 11b = 32-bit overflow Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 645: Rtcctl3 Register
+1 ppm (RTCOCALS = 1) or –1 ppm (RTCOCALS = 0) adjustment in frequency. Maximum effective calibration value is ±240 ppm. Excess values written above ±240 ppm are ignored by hardware. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 646: Rtctcmp Register
Excess values written above ±240 ppm are ignored by hardware. Changing the sign-bit by writing to RTCTCMP_H becomes effective only after also writing RTCTCMP_L. Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 647: Rtcnt1 Register
Table 24-14. RTCNT4 Register Description Field Type Reset Description RTCNT4 undefined The RTCNT4 register is the count of RTCNT4. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 648: Rtcsec Register – Calendar Mode With Hexadecimal Format
Seconds – high digit (0 to 5) Seconds – low digit undefined Seconds – low digit (0 to 9) Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 649: Rtcmin Register – Calendar Mode With Hexadecimal Format
Minutes – high digit (0 to 5) Minutes – low digit undefined Minutes – low digit (0 to 9) SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 650: Rtchour Register – Calendar Mode With Hexadecimal Format
Hours – high digit (0 to 2) Hours – low digit undefined Hours – low digit (0 to 9) Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 651: Rtcdow Register – Calendar Mode
Day of month – high digit (0 to 3) digit Day of month – low undefined Day of month – low digit (0 to 9) digit SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 652: Rtcmon Register – Calendar Mode With Hexadecimal Format
Month – high digit (0 or 1) Month – low digit undefined Month – low digit (0 to 9) Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 653: Rtcyear Register – Calendar Mode With Hexadecimal Format
Century – low digit (0 to 9) Decade undefined Decade (0 to 9) Year – lowest digit undefined Year – lowest digit (0 to 9) SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 654: Rtcamin Register – Calendar Mode With Hexadecimal Format
Minutes – high digit (0 to 5) Minutes – low digit undefined Minutes – low digit (0 to 9) Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 655: Rtcahour Register
Hours – high digit (0 to 2) Hours – low digit undefined Hours – low digit (0 to 9) SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 656: Rtcadow Register – Calendar Mode
1b = This alarm register is enabled Always 0 Day of week undefined Day of week (0 to 6) Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 657: Rtcaday Register – Calendar Mode With Hexadecimal Format
Day of month – high digit (0 to 3) digit Day of month – low undefined Day of month – low digit (0 to 9) digit SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 658: Rtcps0Ctl Register
1b = Interrupt enabled RT0PSIFG Prescale timer 0 interrupt flag 0b = No time event occurred 1b = Time event occurred Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 659: Rtcps1Ctl Register
111b = Divide by 256 RT1PSIE Prescale timer 1 interrupt enable 0b = Interrupt not enabled 1b = Interrupt enabled (LPMx.5 wake-up enabled) SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 660 Prescale timer 1 interrupt flag. This interrupt can be used as LPMx.5 wake-up event. 0b = No time event occurred 1b = Time event occurred Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 661: Rtcps0 Register
Figure 24-37. RTCPS1 Register RT1PS Table 24-38. RTCPS1 Register Description Field Type Reset Description RT1PS undefined Prescale timer 1 counter value SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 662: Rtciv Register
0Ch = Interrupt Source: RTC prescaler 0; Interrupt Flag: RT0PSIFG 0Eh = Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG 10h = Reserved ; Interrupt Priority: Lowest Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 663: Bin2Bcd Register
15-0 BCD2BINx Read: 12-bit binary conversion of previously written 16-bit BCD number. Write: 16-bit BCD number to be converted. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 664: Rtcsecbakx Register – Hexadecimal Format
Seconds – high digit. Valid values are 0 to 5. Seconds – low digit Seconds – low digit. Valid values are 0 to 9. Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 665: Rtcminbakx Register – Hexadecimal Format
Minutes – high digit. Valid values are 0 to 5. Minutes – low digit Minutes – low digit. Valid values are 0 to 9. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 666: Rtchourbakx Register – Hexadecimal Format
Hours – high digit. Valid values are 0 to 2. Hours – low digit Hours – low digit. Valid values are 0 to 9. Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 667: Rtcdaybakx Register – Hexadecimal Format
Day of month – low Day of month – low digit. Valid values are 0 to 9. digit SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 668: Rtcmonbakx Register – Hexadecimal Format
Month – high digit. Valid values are 0 to 3. Month – low digit Month – low digit. Valid values are 0 to 9. Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 669: Rtcyearbakx Register – Hexadecimal Format
Decade. Valid values are 0 to 9. Year – lowest digit Year – lowest digit. Valid values are 0 to 9. SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 670: Rtctcctl0 Register
1b = At least one tamper event occurred. Status of individual tamper events can be found from the CAPEV bit in RTCCAPxCTL. Real-Time Clock C (RTC_C) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 671: Rtccapxctl Register
CAPEV is cleared by the user. Can only be written as 0. 0b = Tamper event did not occur 1b = Tamper event occurred SLAU208Q – June 2008 – Revised March 2018 Real-Time Clock C (RTC_C) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 672: Bit Hardware Multiplier (Mpy32)
........................... Topic Page ..........25.1 32-Bit Hardware Multiplier (MPY32) Introduction ....................25.2 MPY32 Operation ....................25.3 MPY32 Registers 32-Bit Hardware Multiplier (MPY32) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 673: Bit Hardware Multiplier (Mpy32) Introduction
8-bit and 24-bit multiplications without requiring a "sign extend" instruction The MPY32 block diagram is shown in Figure 25-1. SLAU208Q – June 2008 – Revised March 2018 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 674: Mpy32 Block Diagram
MPYSAT 32-bit Adder MPYFRAC MPYC 32-bit Demultiplexer SUMEXT RES3 RES2 RES1/RESHI RES0/RESLO 32-bit Multiplexer Figure 25-1. MPY32 Block Diagram 32-Bit Hardware Multiplier (MPY32) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 675: Mpy32 Operation
24/32 × 8/16 OP2 written OP2L written 8/16 × 24/32 OP2H written OP2L written 24/32 × 24/32 OP2H written SLAU208Q – June 2008 – Revised March 2018 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 676: Operand Registers
During the execution of the 16-bit operation, the content of the high-word is ignored. 32-Bit Hardware Multiplier (MPY32) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 677: Result Registers
00000h = Result was positive or zero 0 = No carry for result 0FFFFh = Result was negative 1 = Result has a carry SLAU208Q – June 2008 – Revised March 2018 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 678: Software Examples
; 8x8 Signed Multiply. Absolute addressing. MOV.B #012h,&MPYS_B ; Load 1st operand MOV.B #034h,&OP2_B ; Load 2nd operand ; Process results 32-Bit Hardware Multiplier (MPY32) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 679: Fractional Numbers
In fractional mode, the SUMEXT register contains the sign extended bits 32 and 33 of the shifted result for 16×16-bit operations and bits 64 and 65 for 32×32-bit operations – not only bits 32 or 64, respectively. SLAU208Q – June 2008 – Revised March 2018 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 680: Result Availability In Fractional Mode (Mpyfrac = 1, Mpysat = 0)
&K2,&OP2 ; Load K2 to get A2*K2 &RES1,&PROD ; Save A1*K1+A2*K2 as result #MPYSAT+MPYFRAC,&MPY32CTL0 ; turn back to normal 32-Bit Hardware Multiplier (MPY32) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 681: Saturation Flow Chart
14=0 RES0 = 00000h RES0 = 00000h 32-bit Saturation 64-bit Saturation completed completed Figure 25-4. Saturation Flow Chart SLAU208Q – June 2008 – Revised March 2018 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 682: Putting It All Together
25.2.5 Putting It All Together Figure 25-5 shows the complete multiplication flow, depending on the various selectable modes for the MPY32 module. 32-Bit Hardware Multiplier (MPY32) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 683: Multiplication Flow Chart
MPYC and bit 15 of unshifted RES1. unshifted RES3. MPYSAT=1 MPYSAT=1 32-bit Saturation 64-bit Saturation Multiplication completed Figure 25-5. Multiplication Flow Chart SLAU208Q – June 2008 – Revised March 2018 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 684 08000 0000h. Adding a negative number to it would again cause an underflow, thus, the final result is also saturated to 08000 0000h. 32-Bit Hardware Multiplier (MPY32) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 685: Indirect Addressing Of Result Registers
; Interrupts may be enabled before ; processing results if result ; registers are stored and restored in ; interrupt service routines SLAU208Q – June 2008 – Revised March 2018 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 686: Using Dma
DMA. The signal into the DMA controller is 'Multiplier ready' (see the DMA Controller chapter for details). 32-Bit Hardware Multiplier (MPY32) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 687: Mpy32 Registers
24-bit operand 1 – signed multiply – high byte Read/write Byte Undefined MAC32L 32-bit operand 1 – multiply accumulate – low word Read/write Word Undefined SLAU208Q – June 2008 – Revised March 2018 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 688: Alternative Registers
8-bit operand one – signed multiply accumulate MACS_B or MACS_L MACS32L_B or MACS32L_L 16x16-bit result low word RESLO RES0 16x16-bit result high word RESHI RES1 32-Bit Hardware Multiplier (MPY32) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 689: Mpy32Ctl0 Register
It is used to restore the SUMEXT content in MAC mode. 0b = No carry for result 1b = Result has a carry SLAU208Q – June 2008 – Revised March 2018 32-Bit Hardware Multiplier (MPY32) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 690 This chapter describes the REF module..........................Topic Page ....................26.1 REF Introduction ..................26.2 Principle of Operation ....................26.3 REF Registers SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 691: Ref Introduction
V REFBG Devices with ADC10_A might not include the reference voltage output to an external pin. Refer to the device-specific data sheet. SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 692: Ref Block Diagram
From REFGEN Channel 1 − DAC12OG COMP_B0 Local Buffer COMP_B1 Local Buffer Copyright © 2017, Texas Instruments Incorporated Figure 26-1. REF Block Diagram SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 693: Ref Block Diagram For Devices With A Ctsd16 Module
Reference REFBG from REFGEN variable reference Copyright © 2017, Texas Instruments Incorporated Figure 26-2. REF Block Diagram for Devices With a CTSD16 Module SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 694: Principle Of Operation
Therefore, if the external reference is selected, make sure that no other modules are requesting internal reference V is available when V is not enabled. REFBG eREF+ REFBG SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 695: Low-Power Operation
Setting this bits enables the variable reference line voltage to be present external to the device through a buffer REFOUT (external reference buffer). REFTCOFF Setting this bit disables the temperature sensor (when available) to conserve power. SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 696: Ref Control Of Reference System (Refmstr = 1) (Default) For Devices With Ctsd16
(ADC12REFOUT = 0) or the external buffer (ADC12REFOUT = 1) is enabled only during a conversion and is disabled automatically to conserve power. SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 697: Reference System Requests
The REFGENBUSY signal is asserted to indicate that a module is using the reference and that reference settings cannot be changed. For example, during an active ADC12_A conversion, the reference voltage level should not be changed. SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 698 The DAC12_A module requires either /2 or /3 of the variable reference. The selection of these depends on the control bits inside the DAC12_A module (DAC12IR, DAC12OG) and is handled automatically by the REF module. SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 699 LCDON = 1 of the LCD_B or LCD_C module. This causes a REFBGREQ from the LCD module to be asserted. The buffered bandgap is available on the bandgap reference line for use by the LCD module. SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 700: Ref Registers
Acronym Register Name Type Access Reset Section REFCTL0 REF Control Register 0 Read/write Word 0080h Section 26.3.1 REFCTL0_L Read/write Byte REFCTL0_H Read/write Byte SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 701: Refctl0 Register (Offset = 00H) [Reset = 0080H]
For devices with CTSD16, REFON must also be set to 1 for V to be REFBG available continuously. Otherwise, V is only available externally when a REFBG module requests it. SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 702 0b = Disables reference if no other reference requests are pending. 1b = Enables reference. SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 703: Adc10_A
ADC10_A module..........................Topic Page ..................27.1 ADC10_A Introduction ..................27.2 ADC10_A Operation ..................27.3 ADC10_A Registers SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 704: Adc10_A Introduction
ADC10_A. The on-chip reference voltage generation is located in the reference module (see the device-specific data sheet). ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 705: Adc10_A Block Diagram
To Interrupt Logic Comparator ADC10MEM ADC10LOx Copyright © 2017, Texas Instruments Incorporated MODCLK is generated by the MODOSC, which is part of the UCS. See the UCS chapter for more information. When using ADC10SHP = 0 no synchronisation of the trigger input is done.
Page 706: Adc10_A Operation
These transients decay and settle before causing an errant conversion. 50 k ADC10MCTL0.0–3 ≈ Input ESD Protection Figure 27-2. Analog Multiplexer ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 707: Voltage Reference Generator
10-bit resolution mode. One additional ADC10CLK is used for the window comparator. Two different sample-timing methods are defined by control bit ADC10SHP, extended sample mode and pulse mode. SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 708: Extended Sample Mode
NOTE: The ADC10SC bit is automatically cleared. Do not modify this bit while it is set. Start Stop Start Conversion Sampling Sampling Conversion Complete 12 × ADC10CLK SAMPCON sample convert sync ADC10CLK Figure 27-4. Pulse Sample Mode ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 709: Conversion Result
A sequence of channels is converted once. Repeat-single-channel A single channel is converted repeatedly. Repeat-sequence-of-channels (repeated autoscan) A sequence of channels is converted repeatedly. SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 710: Single-Channel Single-Conversion Mode
= Pointer to the selected ADC10_A channel defined by ADC10INCHx All bit and register names are bold font; signals names are normal font. Figure 27-6. Single-Channel Single-Conversion Mode ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 711: Sequence-Of-Channels Mode
** Two ADC10CLK cycles are needed. All bit and register names are bold font; signals names are normal font. Figure 27-7. Sequence-of-Channels Mode SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 712: Repeat-Single-Channel Mode
** Two ADC10CLK cycles are needed. All bit and register names are bold font; signals names are normal font. Figure 27-8. Repeat-Single-Channel Mode ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 713: Repeat-Sequence-Of-Channels Mode
** Two ADC10CLK cycles are needed. All bit and register names are bold font; signals names are normal font. Figure 27-9. Repeat-Sequence-of-Channels Mode SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 714: Window Comparator
When the user uses the window comparator flags, it must be ensured that they are reset by software according to the application needs. ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 715: Using The Integrated Temperature Sensor
0.800 0.700 0.600 = 0.00252 x (TEMP ) + 0.688 TEMP 0.500 –50 Temperature (°C) Figure 27-10. Typical Temperature Sensor Transfer Function SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 716: Adc10_A Grounding And Noise Considerations
ADC10MEM0 register or may be reset with software. Write access of the ADC10IV register clears all pending interrupt conditions and flags. ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 717 ADLO ; Handle window comparator low interrupt RETI ; Return ; ADIN ; Handle window comparator in window interrupt RETI ; Return SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 718: Adc10_A Registers
Read/write 0000h Section 27.3.11 ADC10IFG ADC10_A Interrupt Flag register Read/write 0000h Section 27.3.12 ADC10IV ADC10_A Interrupt Vector register Read/write 0000h Section 27.3.13 ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 719: Adc10Ctl0 Register
ADC10SC and ADC10ENC may be set together with one instruction. ADC10SC is reset automatically. 0b = No sample-and-conversion-start 1b = Start sample-and-conversion SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 720: Adc10Ctl1 Register
011b = Divide by 4 100b = Divide by 5 101b = Divide by 6 110b = Divide by 7 111b = Divide by 8 ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 721 ADC10_A busy. This bit indicates an active sample or conversion operation. 0b = No operation is active 1b = A sequence, sample, or conversion is active SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 722: Adc10Ctl2 Register
0b = ADC10_A buffer supports up to approximately 200 ksps. 1b = ADC10_A buffer supports up to approximately 50 ksps. Reserved Reserved. Always reads as 0. ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 723: Adc10Mem0 Register
Writing to the conversion memory register corrupts the results. Reserved Reserved. Always reads as 0. SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 724: Adc10Mctl0 Register
1000b = A8 1001b = A9 1010b = A10 1011b = A11 1100b = A12 1101b = A13 1110b = A14 1111b = A15 ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 725: Adc10Hi Register
Bit 15 is the MSB. Bits 5-0 are 0 in 10-bit mode, and bits 7-0 are 0 in 8- bit mode. This data format is used if ADC10DF = 1. Reserved Reserved. Always reads as 0. SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 726: Adc10Lo Register
Bit 15 is the MSB. Bits 5-0 are 0 in 10-bit mode, and bits 7-0 are 0 in 8- bit mode. This data format is used if ADC10DF = 1. Reserved Reserved. Always reads as 0. ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 727: Adc10Ie Register
Interrupt enable. This bits enable or disable the interrupt request for a completed ADC10_A conversion. 0b = Interrupt disabled 1b = Interrupt enabled SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 728: Adc10Ifg Register
The ADC10IFG0 is set when an ADC10_A conversion is completed. This bit gets reset, when the ADC10MEM0 get read, or may be reset by software. 0b = No interrupt pending 1b = Interrupt pending ADC10_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 729: Adc10Iv Register
0Ah = Interrupt Source: ADC10IN Interrupt flag; Interrupt Flag: ADC10INIFG 0Ch = Interrupt Source: ADC10_A memory Interrupt flag; Interrupt Flag: ADC10IFG0; Interrupt Priority: Lowest SLAU208Q – June 2008 – Revised March 2018 ADC10_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 730: Adc12_A
ADC12_A module..........................Topic Page ..................28.1 ADC12_A Introduction ..................28.2 ADC12_A Operation ..................28.3 ADC12_A Registers ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 731: Adc12_A Introduction
REF module available. Figure 28-2 shows the block diagram for the MSP430F54xx (non-A only) which does not incorporate the REF module. SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 732: Adc12_A Block Diagram (Devices With Ref Module)
UCS chapter for more information. See the device-specific data sheet for timer sources available. Figure 28-1. ADC12_A Block Diagram (Devices With REF Module) ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 733: Adc12_A Msp430F54Xx (Non-A) Block Diagram
ADC12OSC refers to the MODCLK from the UCS. See the UCS chapter for more information. See the device-specific data sheet for timer sources available. Figure 28-2. ADC12_A MSP430F54xx (non-A) Block Diagram SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 734: Adc12_A Operation
These transients decay and settle before causing errant conversion. R ~ 100 W ADC12MCTLx.0–3 Input ESD Protection Figure 28-3. Analog Multiplexer ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 735: Voltage Reference Generator
When ADC12REFBURST = 0, the buffer is on continuously. This allows the reference voltage to be present outside the device continuously if ADC12REFOUT = 1 (REFOUT = 1 when using REF module). SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 736: Auto Power Down
The ADC12SHTx bits select the sampling time in 4× multiples of ADC12CLK. ADC12SHT0x selects the sampling time for ADC12MCTL0 to ADC12MCTL7. ADC12SHT1x selects the sampling time for ADC12MCTL8 to ADC12MCTL15. ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 737: Pulse Sample Mode
) × 25 pF + 800 ns sample For example, for 12-bit resolution, if R is 10 kΩ, t must be greater than 3.46 µs. sample SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 738: Conversion Memory
A sequence of channels is converted once. Repeat-single-channel A single channel is converted repeatedly. Repeat-sequence-of-channels (repeated autoscan) A sequence of channels is converted repeatedly. ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 739: Single-Channel Single-Conversion Mode
Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set x = pointer to ADC12MCTLx Conversion result is unpredictable. Figure 28-7. Single-Channel Single-Conversion Mode SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 740: Sequence-Of-Channels Mode
ADC12EOS.x = 0 ADC12EOS.x = 0 Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set x = pointer to ADC12MCTLx Figure 28-8. Sequence-of-Channels Mode ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 741: Repeat-Single-Channel Mode
ADC12ENC = 1 ADC12ENC = 1 Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set x = pointer to ADC12MCTLx Figure 28-9. Repeat-Single-Channel Mode SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 742: Repeat-Sequence-Of-Channels Mode
(ADC12ENC = 1 or ADC12EOS.x = 0) ADC12EOS.x = 0) Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set x = pointer to ADC12MCTLx Figure 28-10. Repeat-Sequence-of-Channels Mode ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 743 If no ADC12EOS bit is set and a sequence mode is selected, resetting the ADC12ENC bit does not stop the sequence. To stop the sequence, first select a single-channel mode and then reset ADC12ENC. SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 744: Using The Integrated Temperature Sensor
0.950 0.900 0.850 0.800 0.750 0.700 0.650 0.600 0.550 −40 −20 Ambient Temperature – °C Figure 28-11. Typical Temperature Sensor Transfer Function ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 745: Adc12_A Grounding And Noise Considerations
µ 100 nF REF– eREF– Using an External Negative Reference 10 F µ 100 nF Figure 28-12. ADC12_A Grounding and Noise Considerations SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 746: Adc12_A Interrupts
ADC12IV register, the ADC12OV interrupt condition is reset automatically. After the RETI instruction of the interrupt service routine is executed, the ADC12IFG3 generates another interrupt. ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 747 ; Other instruction needed? RETI ; Return ADTOV ; Handle Conv. time overflow RETI ; Return ADOV ; Handle ADCMEMx overflow RETI ; Return SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 748: Adc12_A Registers
ADC12MEM5_H Read/write Byte undefined ADC12MEM6 ADC12_A Memory 6 Read/write Word undefined Section 28.3.4 ADC12MEM6_L Read/write Byte undefined ADC12MEM6_H Read/write Byte undefined ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 749 Section 28.3.5 ADC12MCTL14 ADC12_A Memory Control 14 Read/write Byte undefined Section 28.3.5 ADC12MCTL15 ADC12_A Memory Control 15 Read/write Byte undefined Section 28.3.5 SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 750: Adc12Ctl0 Register
(non-A), the REF module is not available. 0b = Reference off 1b = Reference on ADC12ON ADC12_A on 0b = ADC12_A off 1b = ADC12_A on ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 751 ADC12SC and ADC12ENC may be set together with one instruction. ADC12SC is reset automatically. 0b = No sample-and-conversion-start 1b = Start sample-and-conversion SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 752: Adc12Ctl1 Register
ADC12_A busy. This bit indicates an active sample or conversion operation. 0b = No operation is active. 1b = A sequence, sample, or conversion is active. ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 753: Adc12Ctl2 Register
1b = Reference output on ADC12REFBURST Reference burst 0b = Reference buffer on continuously 1b = Reference buffer on only during sample-and-conversion SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 754: Adc12Memx Register
8-bit mode. The data is stored in the right-justified format and is converted to the left-justified twos-complement format during read back. ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 755: Adc12Mctlx Register
1100b = A12. On devices with the Battery Backup System, VBAT can be measured internally by the ADC. 1101b = A13 1110b = A14 1111b = A15 SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 756: Adc12Ie Register
Interrupt enable. This bit enables or disables the interrupt request for the ADC12IFG6 bit. 0b = Interrupt disabled 1b = Interrupt enabled ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 757 Interrupt enable. This bit enables or disables the interrupt request for the ADC12IFG0 bit. 0b = Interrupt disabled 1b = Interrupt enabled SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 758: Adc12Ifg Register
This bit is reset if the ADC12MEM8 is accessed, or it may be reset with software. 0b = No interrupt pending 1b = Interrupt pending ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 759 This bit is reset if the ADC12MEM0 is accessed, or it may be reset with software. 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 ADC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 760: Adc12Iv Register
22h = Interrupt Source: ADC12MEM14 interrupt flag; Interrupt Flag: ADC12IFG14 24h = Interrupt Source: ADC12MEM15 interrupt flag; Interrupt Flag: ADC12IFG15; Interrupt Priority: Lowest ADC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 761: Sd24_B
SD24_B module..........................Topic Page ..................29.1 SD24_B Introduction .................... 29.2 SD24_B Operation ..................... 29.3 SD24_B Registers SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 762: Sd24_B Introduction
The reference voltage generation is located in the shared reference module (see the device-specific data sheet). Figure 29-3 shows the converter-specific block diagram. SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 763: Sd24_B Overview Block Diagram
SD24GRP0SC SD0P0 SD24GRP0SC SD0N0 SD24GRP0SC SD24GRP0SC Converter 1 SD1P0 SD1N0 Converter 7 SD7P0 SD7N0 Trigger Generator Figure 29-1. SD24_B Overview Block Diagram SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 764: Sd24_B Reference And Clock Generation Block Diagram
/1 /2 /3 /4 ... /32 ACLK (to modulators) ext. Clock SD24CLKOS (to Manchester decoder) to Pad Figure 29-2. SD24_B Reference and Clock Generation Block Diagram SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 765: Sd24_B Converter Block Diagram
Output to Pad Encoder Data Input from Pad Clock Decoder Converter 2 (up to Converter 7) Figure 29-3. SD24_B Converter Block Diagram SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 766: Sd24_B Operation
. The resulting 1-bit data stream is averaged by the digital filter for the conversion result. SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 767: Voltage Reference
With SD24CAL = 1, the offset of the converter can be measured and calibrated in software afterwards. SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 768: Digital Filter
The digital filter processes the 1-bit data stream from the modulator. 29.2.7.1 SINC Filter Figure 29-6 shows the structure of a SINC filter. SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 769: Comb Filter's Frequency Response With Osr = 32
SD24BMEMx register at the sample frequency f -100 -120 -140 Figure 29-7. Comb Filter's Frequency Response With OSR = 32 SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 770: Digital Filter Step Response And Conversion Points Digital Filter Output
If right alignment is selected with SD24ALGN = 0, the digital filter's output value is directly mapped to the SD24_B conversion result registers SD24BMEMHx and SD24BMEMLx with the LSB of the filter's output being mapped to the LSB of SD24BMEMLx. SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 771: Offset Binary Left Aligned Mapping
FF00 0000 FF00 0000 00FF FFFF 7FFF FF80 Bipolar twos complement, 0000 0000 0000 0000 left aligned FF00 0000 8000 0000 SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 772: Bitstream Input And Output
SD24SCSx bits. There are up to four software start-of-conversion triggers and three external (for example a timer output) start-of-conversion triggers available. SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 773: Single Conversion Examples
Setting the SD24SC bit of an individual converter in a group immediately starts conversion for this converter independent of the group's start of conversion trigger. SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 774: Conversion Operation Using Preload
SD24BPREx. SD24OSRx = 32 Load SD24BPREx with SD24PREx = 8 Figure 29-13. Conversion Delay Using Preload - Example SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 775: Grounding And Noise Considerations
If the internal reference is used, the reference voltage should be buffered externally by connecting a small (approximately 100 nF) capacitor to VREF to reduce the noise on the reference. SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 776: Trigger Generator
Trigger 3 Conversion Logic SD24GRP0SC SD24GRP1SC SD24GRP2SC SD24GRP3SC SD24BTRGOSR (Decimation) Trigger Pulse Counter Set TRGIFG SD24BTRGPRE Figure 29-15. SD24_B Trigger Generator Block Diagram SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 777: Sd24_B Interrupts
SD24IFGx flag does not trigger a transfer. Any SD24IFGx is automatically cleared when the DMA controller accesses the corresponding SD24BMEMHx and SD24BMEMLx registers. SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 778: Sd24_B Registers
SD24_B Converter 7 Preload Register Read/write 0000h Section 29.3.11 SD24_B Converter 0 Conversion Memory SD24BMEML0 Read/write 0000h Section 29.3.13 Low Word Register SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 779 SD24_B Converter 7 Conversion Memory SD24BMEML7 Read/write 0000h Section 29.3.13 Low Word Register SD24_B Converter 7 Conversion Memory SD24BMEMH7 Read/write 0000h Section 29.3.14 High Word Register SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 780: Sd24Bctl0 Register
1b = Overflow on 32-bit (2 words); that is, both SD24BMEMx and SD24BMEMHx registers must be read to prevent the overflow interrupt flag being set. Reserved Reserved. Always reads as 0. SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 781: Sd24Bctl1 Register
SD24_B Group 0 start of conversion. Software controlled start of conversion for all converters belonging to group 0. 0b = No conversion start 1b = Start conversion for group 0 SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 782: Sd24Btrgctl Register
SD24SC = 1. 0b = No conversion start or stop conversion 1b = Start conversion or trigger generation SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 783: Sd24Bifg Register
When only one of the corresponding conversion registers SD24BMEML3 or SD24BMEMH3 is read before new values are loaded (SD24OV32 = 1). 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 784 The bits are reset by reading one of the SD24BMEML3 or SD24BMEMH3 registers, or may be reset by software. 0b = No interrupt pending 1b = Interrupt pending SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 785 The bits are reset by reading one of the SD24BMEML0 or SD24BMEMH0 registers, or may be reset by software. 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 786: Sd24Bie Register
0b = Interrupt disabled 1b = Interrupt enabled SD24IE3 SD24_B converter 3 interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 787 0b = Interrupt disabled 1b = Interrupt enabled SD24IE0 SD24_B converter 0 interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 788: Sd24Biv Register
12h = Interrupt Source: SD24_B converter 6 memory interrupt flag; Interrupt Flag: SD24IFG6 14h = Interrupt Source: SD24_B converter 7 memory interrupt flag; Interrupt Flag: SD24IFG7; Interrupt Priority: Lowest SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 789: Sd24Bcctlx Register
00b = Offset binary 01b = Twos complement 10b = Reserved (defaults to 00, offset binary) 11b = Reserved (defaults to 01, twos complement) SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 790 0b = No conversion start (that is, conversion stopped) 1b = Conversion ongoing SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 791: Sd24Binctlx Register
001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 Reserved Reserved SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 792: Sd24Bosrx Register
SD24OSRx Oversampling rate. The oversampling rate is defined as OSRx + 1. Valid oversampling rates are 1 to 1024. Default is 256. SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 793: Sd24Bprex Register
Table 29-17. SD24BTRGPRE Register Description Field Type Reset Description 15-10 Reserved Reserved. Always reads as 0. SD24BPREx Digital filter preload value SLAU208Q – June 2008 – Revised March 2018 SD24_B Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 794: Sd24Bmemlx Register Description
Field Type Reset Description 15-0 Conversion Results - Conversion results. Actual format depends on selected data format, and High Word oversampling rate. SD24_B SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 795: Ctsd16
CTSD16 module..........................Topic Page ..................30.1 CTSD16 Introduction .................... 30.2 CTSD16 Operation ..................... 30.3 CTSD16 Registers SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 796: Ctsd16 Introduction
Software-selectable AVCC sense, VBAT sense, and temperature sensor accessible by all channels Figure 30-1 shows the block diagram of the CTSD16 module. CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 797: Ctsd16 Block Diagram
AD2+ AD2- AD3+ AD3- AD4+ REFBG VeREF+ AD4- AD4+ DAC0 AD4- REFBG VeREF+ up to Channel 1-6 Figure 30-1. CTSD16 Block Diagram SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 798: Ctsd16 Operation
. The resulting 1-bit data stream is averaged by the digital filter for the conversion result. CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 799: Voltage Reference Signal Selection Requirements
CTSD16REFS = 1, the CTSD16 module bursts the request for the V signal to the REF module so it is REFBG only requested when CTSD16 is actively converting. SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 800: Analog Inputs
CTSD16RRIBURST bit can be set to allow the CTSD16 to only request the charge pump for rail-to-rail input mode when CTSD16 is converting. CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 801: Digital Filter
The digital filter for each enabled ADC channel completes the decimation of the digital bitstream and outputs new conversion results to the corresponding CTSD16MEMx register at the sample frequency f SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 802: Comb Filter Frequency Response With Osr = 32
An asynchronous step requires one additional conversion before valid data is available. Asynchronous Step Synchronous Step Conversions Conversions Figure 30-5. Digital Filter Step Response and Conversion Points Digital Filter Output CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 803: Used Bits Of Digital Filter Output
11 10 OSR=32, LSBACC=x 23 22 21 19 18 17 15 14 13 11 10 Figure 30-6. Used Bits of Digital Filter Output SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 804: Data Format
−V FSR Voltage 8000h 0000h +V FSR Input Voltage 0000h 8000h −V FSR +V FSR Figure 30-7. Input Voltage vs Digital Output CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 805: Conversion Mode Summary
CTSD16GRP = 0 CTSD16SC Set by Software Cleared by Software Time = Result written to CTSD16MEMx Figure 30-8. Single Channel Operation Example SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 806: Grouped Channel Operation Example
CTSD16GRP = 0 CTSD16SC Cleared by Software Set by Software Time = Result written to CTSD16MEMx Figure 30-9. Grouped Channel Operation Example CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 807: Conversion Operation Using Preload
It is recommended that CTSD16PREx = 0 for the master channel to maintain a consistent delay between the master and remaining channels in the group when they are re-enabled. SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 808: Using The Integrated Temperature Sensor
0.950 0.900 0.850 0.800 0.750 0.700 0.650 0.600 0.550 −40 −20 Ambient Temperature – °C Figure 30-13. Typical Temperature Sensor Transfer Function CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 809: Using The Integrated Avcc Sense
After the RETI instruction of the interrupt service routine is executed, the highest priority CTSD16IFG pending generates another interrupt request. SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 810 If the respective interrupt enable bit CTSD16IEx is set, the selected CTSD16IFGx flag does not trigger a transfer. Any CTSD16IFGx is automatically cleared when the DMA controller accesses the corresponding CTSD16MEMx registers. CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 811: Ctsd16 Registers
0000h Section 30.3.6 CTSD16IE CTSD16 Interrupt Enable Register Read/write Word 0000h Section 30.3.7 CTSD16IV CTSD16 Interrupt Vector Read/write Word 0000h Section 30.3.8 SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 812: Ctsd16Ctl Register Description
1b = Internal reference from shared REF selected and buffered internally to CTSD16 Reserved Reserved. Always reads as 0. Reserved Reserved. Always reads as 0. CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 813: Ctsd16Cctl0 To Ctsd16Cctl6 Register Description
CTSD16 group. Groups CTSD16 channel with next higher channel. Not used for the last channel. 0b = Not grouped 1b = Grouped SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 814: Ctsd16Mem0 To Ctsd16Mem6 Register Description
Conversion Results Conversion results. This register holds the upper or lower 16-bits of the digital filter output, depending on the CTSD16LSBACC bit. CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 815: Ctsd16Inctl0 To Ctsd16Inctl6 Register Description
10000b = in+ = AD3+, in- = V REFBG eREF+ 10001b = AD4x, shorted differential inputs to V REFBG eREF+ 10010b = AD4x, shorted differential inputs to DAC0 output SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 816: Ctsd16Pre0 To Ctsd16Pre6 Register Description
• If internal reference is already settled or not used and CTSD16RRI = 0 and OARRI = 0 then the minimum preload value is the default one. CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 817: Ctsd16Ifg Register Description
CTSD16IFG4 is automatically reset when the CTSD16MEM4 register is read, or may be cleared with software. 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 818 CTSD16IFG0 is automatically reset when the CTSD16MEM0 register is read, or may be cleared with software 0b = No interrupt pending 1b = Interrupt pending CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 819: Ctsd16Ie Register Description
0b = Interrupt disabled 1b = Interrupt enabled CTSD16IE2 CTSD16 converter 2 interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 820 0b = Interrupt disabled 1b = Interrupt enabled CTSD16IE0 CTSD16 converter 0 interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled CTSD16 SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 821: Ctsd16Iv Register Description
Interrupt Priority = Lowest When an CTSD16 overflow occurs, the user must check all CTSD16CCTLx CTSD16OVIFG flags to determine which channel overflowed. SLAU208Q – June 2008 – Revised March 2018 CTSD16 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 822: Dac12_A
DAC12_A module..........................Topic Page ..................31.1 DAC12_A Introduction ..................31.2 DAC12_A Operation ....................31.3 DAC Outputs ..................31.4 DAC12_A Registers DAC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 823: Dac12_A Introduction
DAC12_A modules. Figure 31-2 shows the block diagram for a device with one DAC12_A module. SLAU208Q – June 2008 – Revised March 2018 DAC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 824: Dac12_A Block Diagram For A Device With Two Modules
DAC12DF DAC12DFJ DAC12GRP DAC12_1DAT DAC12_1DAT Updated Copyright © 2017, Texas Instruments Incorporated Figure 31-1. DAC12_A Block Diagram for a Device With Two Modules DAC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 825: Dac12_A Block Diagram For A Device With One Module
DAC12DF DAC12DFJ DAC12GRP DAC12_0DAT DAC12_0DAT Updated Copyright © 2017, Texas Instruments Incorporated Figure 31-2. DAC12_A Block Diagram For a Device With One Module SLAU208Q – June 2008 – Revised March 2018 DAC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 826: Eeref+ Eref+ Erefbg
REFBG selected. See Table 31-2 for details on which bits to set to select between the V and V signals. eREF+ REFBG DAC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 827: Dac12Srefx = {2,3} Signal Selection Requirements For Devices With A Ctsd16 Module
(0080h in 8-bit mode) results in a zero output voltage, 0000h is the mid-scale output voltage, and 07FFh (007Fh for 8-bit mode) is the full-scale voltage output (see Figure 31-4). SLAU208Q – June 2008 – Revised March 2018 DAC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 828: Dac12_A Output Amplifier Offset Calibration
The DAC12_A output voltage reaches the maximum output level before the DAC12_A data reaches the maximum code (see Figure 31-6). Full-Scale Code DAC Data Figure 31-6. Positive Offset DAC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 829: Grouping Multiple Dac12_A Modules
Latch Trigger DAC12_0 DAC12LSELx = 2 DAC12_0 DAC12LSELx > 0 AND DAC12_1 DAC12LSELx = 2 Figure 31-7. DAC12_A Group Update Example, Timer_A3 Trigger SLAU208Q – June 2008 – Revised March 2018 DAC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 830: Dac12_A Interrupts
; Task starts here RETI ; Back to main program DAC12IFG_0_HND ; Vector 2: DAC12_0 ; Task starts here RETI ; Back to main program DAC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 831: Dac Output Selection
Table 31-3. DAC Output Selection DAC12OPS DAC12AMP Pm.y Function Pn.z Function DAC output, 0 V {>1} DAC output DAC output, 0 V {>1} DAC output SLAU208Q – June 2008 – Revised March 2018 DAC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 832: Dac12_A Registers
DAC12_1 Calibration Control Read/write Word 0000h Section 31.4.11 DAC12_1CALDAT DAC12_1 Calibration Data Read/write Word 0000h Section 31.4.12 DAC12IV DAC12IV Read Word 0000h Section 31.4.13 DAC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 833: Dac12_Xctl0 Register Description
0b = If DAC12OG = 0, then DAC12 full-scale output = 3x reference voltage; if DAC12OG = 1, then DAC12 full-scale output = 2x reference voltage 1b = DAC12 full-scale output = 1x reference voltage SLAU208Q – June 2008 – Revised March 2018 DAC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 834 DAC group. Groups DAC12_x with the next higher DAC12_x. Not used for DAC12_1 on dual DAC devices. 0b = Not grouped 1b = Grouped DAC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 835: Dac12_Xctl1 Register Description
DAC data format justification. Can be modified only when DAC12ENC = 0. 0b = Data format right justified 1b = Data format left justified SLAU208Q – June 2008 – Revised March 2018 DAC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 836: Dac12_Xdat Register Description
Type Reset Description 15-4 DAC12 Data DAC data in unsigned format. Bit 15 represents the MSB. Reserved Reserved. Always reads as 0. DAC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 837: Dac12_Xdat Register Description
DAC data in twos complement format. Bit 15 represents the sign bit of the twos complement value. Reserved Reserved. Always reads as 0. SLAU208Q – June 2008 – Revised March 2018 DAC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 838: Dac12_Xdat Register Description
Type Reset Description 15-8 DAC12 Data DAC data in unsigned format. Bit 15 represents the MSB. Reserved Reserved. Always reads as 0. DAC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 839: Dac12_Xdat Register Description
DAC data in twos complement format. Bit 15 represents the sign bit of the twos complement value. Reserved Reserved. Always reads as 0. SLAU208Q – June 2008 – Revised March 2018 DAC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 840: Dac12_Xcalctl Register Description
DAC12 Calibration DAC calibration data. The DAC calibration data is represented in twos Data complement format providing a range of –128 to +127. DAC12_A SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 841: Dac12Iv Register Description
04h = Interrupt Source: DAC12 channel 1; Interrupt Flag: DAC12IFG_1; Interrupt Priority: Lowest 06h = Reserved 08h = Reserved 0Ah = Reserved 0Ch = Reserved 0Eh = Reserved SLAU208Q – June 2008 – Revised March 2018 DAC12_A Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 842: Comparator B (Comp_B)
16 channels..........................Topic Page ..................32.1 Comp_B Introduction ................... 32.2 Comp_B Operation .................... 32.3 Comp_B Registers Comparator B (Comp_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 843: Comp_B Introduction
CBRS CBOUTPOL 0001 Reference Voltage from shared Generator reference CB12 CB13 CB14 1110 CB15 1111 Figure 32-1. Comp_B Block Diagram SLAU208Q – June 2008 – Revised March 2018 Comparator B (Comp_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 844: Comp_B Operation
The CBSHORT bit shorts the Comp_B inputs. This can be used to build a simple sample-and-hold for the comparator as shown in Figure 32-2. Comparator B (Comp_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 845: Output Filter
Selecting the output filter can reduce errors associated with comparator oscillation. SLAU208Q – June 2008 – Revised March 2018 Comparator B (Comp_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 846: Reference Voltage Generator
CBOUT is 1 and Vref0 is used while CBOUT is 0. This allows the generation of a hysteresis without using external components. Comparator B (Comp_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 847: Comp_B Port Disable Register Cbctl3
(see Figure 32-6). Reference resister Rref is compared to Rmeas. SLAU208Q – June 2008 – Revised March 2018 Comparator B (Comp_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 848: Temperature Measurement System
Comparator B (Comp_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 849 –R × C × ln meas meas ref1 –R × C × ln meas meas meas = R × meas SLAU208Q – June 2008 – Revised March 2018 Comparator B (Comp_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 850: Comp_B Registers
Section 32.3.4 CBINT Comp_B interrupt register Read/write Word 0000h Section 32.3.5 CBIV Comp_B interrupt vector word Read Word 0000h Section 32.3.6 Comparator B (Comp_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 851: Cbctl0 Register Description
Reserved. Always reads as 0. CBIPSEL Channel input selected for the V+ terminal of the comparator if CBIPEN is set to SLAU208Q – June 2008 – Revised March 2018 Comparator B (Comp_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 852: Cbctl1 Register Description
Output value. This bit reflects the value of the Comp_B output. Writing this bit has no effect on the comparator output. Comparator B (Comp_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 853: Cbctl2 Register Description
+ terminal CBREF0 Reference resistor tap 0. This register defines the tap of the resistor string while CBOUT = 0. SLAU208Q – June 2008 – Revised March 2018 Comparator B (Comp_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 854: Cbctl3 Register Description
Comp_B. The bit CBPD8 disables the port of the comparator channel 8. 0b = Input buffer enabled 1b = Input buffer disabled Comparator B (Comp_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 855 Comp_B. The bit CBPD0 disables the port of the comparator channel 0. 0b = Input buffer enabled 1b = Input buffer disabled SLAU208Q – June 2008 – Revised March 2018 Comparator B (Comp_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 856: Cbint Register Description
Comp_B output interrupt flag. The bit CBIES defines the transition of the output setting this bit. 0b = No interrupt pending 1b = Output interrupt pending Comparator B (Comp_B) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 857: Cbiv Register Description
02h = Interrupt Source: CBOUT interrupt; Interrupt Flag: CBIFG; Interrupt Priority: Highest 04h = Interrupt Source: CBOUT interrupt inverted polarity; Interrupt Flag: CBIIFG; Interrupt Priority: Lowest SLAU208Q – June 2008 – Revised March 2018 Comparator B (Comp_B) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 858: Operational Amplifier (Oa)
OA Introduction ....................33.2 OA Operation ....................33.3 Ground Switches ..................33.4 OA and Power Modes ....................33.5 OA Registers Operational Amplifier (OA) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 859: Oa Introduction
The information in this chapter applies to all operational amplifiers in the family. Figure 33-1 shows the block diagram of the OA module. SLAU208Q – June 2008 – Revised March 2018 Operational Amplifier (OA) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 860: Oa Block Diagram
OARRIRDY NSW0 OAnIN0 NSW1 OAnIN1 NSW2 OAnIN2 NSW3 OAnIN3 NSW4 GSW0 GnSW0 AVSS GSW1 GnSW1 Figure 33-1. OA Block Diagram Operational Amplifier (OA) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 861: Oa Mode Select
Negative input terminal switch 4 control, NSW4, allows for an internally connected voltage follower configuration. Refer to device-specific data sheet for other internal connection options. SLAU208Q – June 2008 – Revised March 2018 Operational Amplifier (OA) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 862: Ground Switches
OA being active. Therefore, entering some of the lower-power modes, such as LPM2 through LPM4, while the module is enabled has reduced low-power benefits. Operational Amplifier (OA) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 863: Oa Registers
Read/write Byte OAnNSW_H Read/write Byte OAnGSW OAn Ground Switches Read/write Word 0000h Section 33.5.4 OAnGSW_L Read/write Byte OAnGSW_H Read/write Byte SLAU208Q – June 2008 – Revised March 2018 Operational Amplifier (OA) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 864: Oanctl0 Register Description
1b = Enabled. If OA output is shared with a digital I/O port, the digital I/O port is automatically disabled regardless of the PxSEL settings of the respective port. Operational Amplifier (OA) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 865: Oanpsw Register Description
0b = Switch open 1b = Switch closed PSW0 Positive input terminal switch 0 control. 0b = Switch open 1b = Switch closed SLAU208Q – June 2008 – Revised March 2018 Operational Amplifier (OA) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 866: Oannsw Register Description
0b = Switch open 1b = Switch closed NSW0 Negative input terminal switch 0 control. 0b = Switch open 1b = Switch closed Operational Amplifier (OA) SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 867: Oangsw Register Description
If ground switch output is shared with a digital I/O port, the digital I/O port is automatically disabled regardless of the PxSEL settings of the respective port. SLAU208Q – June 2008 – Revised March 2018 Operational Amplifier (OA) Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 868: Lcd_B Controller
The LCD_B controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapter describes the LCD_B controller..........................Topic Page ................34.1 LCD_B Controller Introduction ................34.2 LCD_B Controller Operation ....................34.3 LCD_B Registers LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 869: Lcd_B Controller Introduction
The maximum number of segment lines and memory registers available differs with device. See the device-specific data sheet for available segment pins and the maximum number of segments supported. SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 870: Lcd_B Controller Block Diagram
VLCDREFx VLCDx Regulated Charge Pump/ LCD Bias Generator Contrast Control LCDCPEN LCDCAP/R33 LCDREF/R13 LCD2B EXTBIAS Figure 34-1. LCD_B Controller Block Diagram LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 871: Lcd_B Controller Operation
LCD's requirement for framing frequency and the LCD multiplex rate and is calculated by: = 2 × mux × f Frame SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 872: Blanking The Lcd
LCDBLKMODx = 01 or 10 is selected. The memory to be displayed can be selected either manually using the LCDDISP bit or automatically with LCDBLKMODx = 11. LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 873: Lcd_B Voltage And Bias Generation
This allows the power to the resistor ladder to be turned off, eliminating current consumption when the LCD is not used. When VLCDEXT = 1, R33 serves as a V input. SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 874: Bias Generation
LCD. The LCD contrast can be controlled in software by adjusting the LCD voltage generated by the integrated charge pump using the VLCDx settings. LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 875: Lcd Voltage And Biasing Characteristics
The interrupt vector register LCDBIV is used to determine which flag requested an interrupt. SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 876 RETI ; Back to main program LCDBLKOFF_HND ; Vector 6: LCDBLKOFFIFG ... ; Task starts here RETI ; Back to main program LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 877: Static Mode
Segment is on. Resulting voltage for Segment b (COM0-SP2) Segment is off. SP = Segment Pin Figure 34-4. Example Static Waveforms SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 878: Static Lcd Example (Mab Addresses Need To Be Replaced With Lcdmx)
Parallel-Serial Conversion Sn+1 COM0 COM0 COM1 COM2 COM3 Figure 34-5. Static LCD Example (MAB addresses need to be replaced with LCDMx) LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 879 ; byte are written ...... ; Table DB a+b+c+d+e+f ; displays "0" DB b+c; ; displays "1" ...... DB ... SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 880: Mux Mode
Segment is on. SP = Segment Pin Resulting voltage for Segment b (COM1-SP2) Segment is Off. Figure 34-6. Example 2-Mux Waveforms LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 881: Mux Lcd Example (Mab Addresses Need To Be Replaced With Lcdmx)
Conversion Sn+1 COM0 COM0 COM1 COM1 COM2 COM3 Figure 34-7. 2-Mux LCD Example (MAB addresses need to be replaced with LCDMx) SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 882 ; are written ......... Table DB a+b+c+d+e+f ; displays "0" ... DB a+b+c+d+e+f+g ; displays "8" ...... DB ... ; LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 883: Mux Mode
Resulting voltage for Segment e (COM0-SP1) Segment is off. Resulting voltage for Segment d (COM0-SP2) Segment is on. Figure 34-8. Example 3-Mux Waveforms SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 884: Mux Lcd Example (Mab Addresses Need To Be Replaced With Lcdmx)
Sn+1 COM0 COM0 COM1 COM1 COM2 COM2 COM3 Figure 34-9. 3-Mux LCD Example (MAB addresses need to be replaced with LCDMx) LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 885 ; Digit n+1 (HighByte) ... Table DW a+b+c+d+e+f ; displays "0" DW b+c ; displays "1" ...... DW a+e+f+g ; displays "F" SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 886: Mux Mode
Resulting voltage for Segment e (COM1-SP1) Segment is off. Resulting voltage for Segment c (COM1-SP2) Segment is on. Figure 34-10. Example 4-Mux Waveforms LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 887: Mux Lcd Example (Mab Addresses Need To Be Replaced With Lcdmx)
COM0 COM0 COM1 COM1 COM2 COM2 COM3 COM3 Figure 34-11. 4-Mux LCD Example (MAB addresses need to be replaced with LCDMx) SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 888 DB b+c ; displays "1" ...... DB b+c+d+e+g ; displays "d" DB a+d+e+f+g ; displays "E" DB a+e+f+g ; displays "F" LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 889: Lcd_B Registers
Section 34.3.10 014h Reserved 016h Reserved 018h Reserved 01Ah Reserved 01Ch Reserved 01Eh LCDBIV LCD_B interrupt vector Read/write 0000h Section 34.3.11 SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 890: Lcd_B Memory Registers
Reserved Read/write Unchanged 03Eh Reserved Read/write Unchanged 03Fh Reserved Read/write Unchanged The LCD memory registers can also be accessed as word. LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 891: Lcd_B Blinking Memory Registers
Read/write Unchanged 05Eh Reserved Read/write Unchanged 05Fh Reserved Read/write Unchanged The LCD blinking memory registers can also be accessed as word. SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 892: Lcdbctl0 Register Description
LCD on. This bit turns the LCD_B module on or off. 0b = LCD_B module off 1b = LCD_B module on LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 893: Lcdbctl1 Register
LCD frame interrupt flag. Automatically cleared when data is written into a memory register. 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 894: Lcdbblkctl Register
LCDBMx 10b = Blinking of all segments 11b = Switching between display contents as stored in LCDMx and LCDBMx memory registers. LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 895: Lcdbmemctl Register
When returning to LCDBLKMODx = 00 the bit is cleared. 0b = Display content of LCD memory registers LCDMx 1b = Display content of LCD blinking memory registers LCDBMx SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 896: Lcdbvctl Register
= 2.77 × V 1110b = V = 2.82 × V 1111b = V = 2.87 × V Reserved Reserved. Always reads as 0. LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 897 11b = Reserved. Defaults to external reference voltage. LCD2B Bias select. LCD2B is ignored when LCDMx = 00. 0b = 1/3 bias 1b = 1/2 bias SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 898: Lcdbpctl0 Register
This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions. LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 899: Lcdbpctl2 Register
NOTE: Settings for LCDSx should be changed only while LCDON = 0. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions. SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 900: Lcdbcpctl Register
0b = LCD charge pump not automatically disabled during conversion. 1b = LCD charge pump automatically disabled during conversion. LCDCPDIS1 Reserved LCDCPDIS0 Reserved LCD_B Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 901: Lcdbiv Register
06h = Interrupt Source: Blink, segments on; Interrupt Flag: LCDBLKONIFG 08h = Interrupt Source: Frame interrupt; Interrupt Flag: LCDFRMIFG; Interrupt Priority: Lowest SLAU208Q – June 2008 – Revised March 2018 LCD_B Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 902: Lcd_C Controller
The differences between LCD_B and LCD_C are listed in Table 35-1..........................Topic Page ..................35.1 LCD_C Introduction ....................35.2 LCD_C Operation ....................35.3 LCD_C Registers LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 903: Lcd_C Introduction
The maximum number of segment lines and memory registers available differs with device. See the device-specific data sheet for available segment pins and the maximum number of segments supported. SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 904: Lcd Controller Block Diagram
VLCDREFx VLCDx Regulated Charge Pump/ LCD Bias Generator Contrast Control LCDCPEN LCDCAP/R33 LCDREF/R13 LCD2B EXTBIAS Figure 35-1. LCD Controller Block Diagram LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 905: Lcd_C Operation
LCDM2 1, 0 LCDM1 Sn+1 Figure 35-2. LCD Memory for Static and 2-Mux to 4-Mux Mode - Example for 160 Segments SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 906: Lcd Timing Generation
= 32768 Hz, LCDPREx = 011, and LCDDIVx = 10101: ACLK/VLOCLK = 32768 Hz / ((21+1) × 2 ) = 32768 Hz / 176 = 186 Hz LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 907: Blanking The Lcd
With LCDDISP = 0, the LCD memory is selected, and with LCDDISP = 1 the blinking memory is selected as display memory. Switching between the memories is synchronized to the frame boundaries. SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 908: Lcd Voltage And Bias Generation
VLCDx bits setting. When VLCDEXT = 1, V is sourced externally from the LCDCAP, pin and the internal charge pump is disabled. LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 909: Bias Generation
Figure 35-4. Bias Generation The internally generated bias voltages V2 to V4 are switched to external pins with LCDREXT = 1. SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 910: Bias Voltages And External Pins
LCDREXT = 1 or LCDEXTBIAS = 1 5-mux to 8-mux V4 ("1/3") if LCDREXT = 1 or LCDEXTBIAS = 1 V5 ("0") if R03EXT = 1 LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 911: Lcd Outputs
LCDSx bits as for all other segment pins. See the port schematic section of the device-specific data sheet for details on controlling the pin functionality. SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 912: Lcd Interrupts
The LCDFRMIFG is set at a frame boundary. It is automatically cleared when a LCD or blinking memory register is written. Setting the LCDFRMIFGIE bit enables the interrupt. LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 913 RETI ; Back to main program LCDBLKOFF_HND ; Vector 6: LCDBLKOFFIFG ... ; Task starts here RETI ; Back to main program SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 914: Static Mode
COM0 COM0 frame COM0-S0 Segment is on. −V1 COM0-S1 Segment is off. −V1 Figure 35-5. Example Static Waveforms LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 915: Mux Mode
2-mux 1/2-bias waveforms. COM0 COM0 frame COM1 COM1 COM0-S0 Segment is on. −V1 COM1-S1 Segment is off. −V1 Figure 35-6. Example 2-Mux Waveforms SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 916: Mux Mode
COM0 COM0 frame COM1 COM1 COM2 COM0-S0 Segment is on. −V1 COM1-S1 Segment is off. −V1 Figure 35-7. Example 3-Mux Waveforms LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 917: Mux Mode
COM0 frame COM1 COM1 COM2 COM3 COM0-S0 Segment is on. −V1 COM1-S1 Segment is off. −V1 Figure 35-8. Example 4-Mux Waveforms SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 918: Mux Mode
COM1 COM1 COM2 COM3 COM4 COM5 COM0-S0 Segment is on. −V1 COM1-S1 Segment is off. −V1 Figure 35-9. Example 6-Mux Waveforms LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 919: Mux Mode
COM7 COM0-S0 Segment is on. −V1 COM1-S1 Segment is off. −V1 Figure 35-10. Example 8-Mux, 1/3 Bias Waveforms (LCDLP = 0) SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 920: Example 8-Mux, 1/3 Bias Low-Power Waveforms (Lcdlp = 1)
COM0-S0 Segment is on. −V1 COM1-S1 Segment is off. −V1 Figure 35-11. Example 8-Mux, 1/3 Bias Low-Power Waveforms (LCDLP = 1) LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 921: Lcd_C Registers
Section 35.3.10 014h Reserved 016h Reserved 018h Reserved 01Ah Reserved 01Ch Reserved 01Eh LCDCIV LCD_C interrupt vector Read/write 0000h Section 35.3.11 SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 922: Lcd_C Memory Registers For Static And 2-Mux To 4-Mux Modes
The number of available memory registers on a given device depends on the number of available segment pins; see the device-specific data sheet. LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 923: Lcd Blinking Memory Registers For Static And 2-Mux To 4-Mux Modes
The number of available memory registers on a given device depends on the number of available segment pins; see the device-specific data sheet. SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 924: Lcd Memory Registers For 5-Mux To 8-Mux
The number of available memory registers on a given device depends on the number of available segment pins; see the device-specific data sheet. LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 925 Reserved 056h Reserved 057h Reserved 058h Reserved 059h Reserved 05Ah Reserved 05Bh Reserved 05Ch Reserved 05Dh Reserved 05Eh Reserved 05Fh Reserved SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 926: Lcdcctl0 Register
0b = Standard LCD waveforms on segment and common lines selected 1b = Low-power LCD waveforms on segment and common lines selected LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 927 LCD on. This bit turns the LCD_C module on or off. 0b = LCD_C module off 1b = LCD_C module on SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 928: Lcdcctl1 Register
LCD frame interrupt flag. Automatically cleared when data is written into a memory register. 0b = No interrupt pending 1b = Interrupt pending LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 929: Lcdcblkctl Register
11b = Switching between display contents as stored in LCDMx and LCDBMx memory registers. In mux mode >5 blinking is disabled. SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 930: Lcdcmemctl Register
When returning to LCDBLKMODx = 00 the bit is cleared. 0b = Display content of LCD memory registers LCDMx 1b = Display content of LCD blinking memory registers LCDBMx LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 931: Lcdcvctl Register
NOTE: Should be changed only while LCDON = 0. 0b = V is generated internally 1b = V is sourced externally SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 932 Bias select. LCD2B is ignored in static mode or mux modes ≥5. NOTE: Should be changed only while LCDON = 0. 0b = 1/3 bias 1b = 1/2 bias LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 933: Lcdcpctl0 Register
NOTE: Settings for LCDSx should be changed only while LCDON = 0. 0b = Multiplexed pins are port functions 1b = Pins are LCD functions SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 934: Lcdcpctl2 Register
NOTE: Settings for LCDSx should be changed only while LCDON = 0. 0b = Multiplexed pins are port functions 1b = Pins are LCD functions LCD_C Controller SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 935: Lcdccpctl Register
06h = Interrupt Source: Blink, segments on; Interrupt Flag: LCDBLKONIFG 08h = Interrupt Source: Frame interrupt; Interrupt Flag: LCDFRMIFG; Interrupt Priority: Lowest SLAU208Q – June 2008 – Revised March 2018 LCD_C Controller Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 936: Universal Serial Communication Interface – Uart Mode
USCI Introduction – UART Mode ................36.3 USCI Operation – UART Mode ................36.4 USCI_A UART Mode Registers Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 937: Universal Serial Communication Interface (Usci) Overview
Automatic baud-rate detection for LIN communications • SPI mode USCI_Bx modules support: • C mode • SPI mode SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 938: Usci Introduction – Uart Mode
Status flags for error detection and suppression • Status flags for address detection • Independent interrupt capability for receive and transmit Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 939: Usci_Ax Block Diagram – Uart Mode (Ucsync = 0)
Set UCTXIFG UCTXBRK UCTXADDR UCMODEx UCSPB Figure 36-1. USCI_Ax Block Diagram – UART Mode (UCSYNC = 0) SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 940: Usci Operation – Uart Mode
When an idle line is detected, the UCIDLE bit is set. Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 941: Idle-Line Format
The idle-line time must not be exceeded between address and data transmission or between data transmissions. Otherwise, the transmitted data is misinterpreted as an address. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 942: Address-Bit Multiprocessor Format
(UCTXIFG = 1). This generates a break with all bits low. UCTXBRK is automatically cleared when the start bit is generated. Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 943: Automatic Baud-Rate Detection
The latter case can be discovered by checking the received data and the UCFE bit. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 944 The data written to UCAxTXBUF is transferred to the shift register and transmitted as soon as the shift register is ready for new data. Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 945: Irda Encoding And Decoding
With parity or CRC checks, use a protocol that acknowledges received data frame and resends data if the sender does not receive an acknowledgment. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 946: Automatic Error Detection
UCAxRXBUF to detect this condition. Note that, in this case, the UCRXERR flag is not set. Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 947: Usci Receive Enable
If new data is not in UCAxTXBUF when the previous byte has transmitted, the transmitter returns to its idle state and the baud-rate generator is turned off. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 948: Uart Baud-Rate Generation
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (Start Bit) Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 949: Bitclk16 Modulation Pattern
36-2) as previously described. Table 36-3. BITCLK16 Modulation Pattern Number of BITCLK16 Clocks After Last Falling BITCLK Edge UCBRFx SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 950: Setting A Baud Rate
= Sum of ones from the corresponding row in Table 36-3 j = 0 [i] = Modulation of bit i from Table 36-2 UCBRSx Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 951: Receive Bit Timing
)(UCBRx + m [i]) bit,RX BRCLK UCBRSx [i] = Modulation of bit i from Table 36-2 UCBRSx SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 952: Typical Baud Rates And Errors
4 000 000 115200 -2.1 -2.5 4 000 000 230400 -2.1 -6.8 4 194 304 9600 -0.3 -0.3 Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 953 20 000 000 115200 -0.4 -0.8 20 000 000 230400 -1.0 -1.0 20 000 000 460800 -1.4 -3.3 SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 954: Commonly Used Baud Rates, Settings, And Errors, Ucos16 = 1
38400 20 000 000 57600 -0.7 -0.7 20 000 000 115200 -0.2 20 000 000 230400 Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 955: Using The Usci Module In Uart Mode With Low-Power Modes
Any access, read or write, of the UCAxIV register automatically resets the highest-pending interrupt flag. If another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 956: Dma Operation
(UCRXERR, UCFE, UCPE, UCOE, and UCBRK) are cleared after the read. Thus these errors might go unnoticed. Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 957: Usci_A Uart Mode Registers
USCI_Ax Interrupt Flag Read/write Byte Section 36.4.13 UCAxIV USCI_Ax Interrupt Vector Read Word 0000h Section 36.4.14 SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 958: Ucaxctl0 Register
11b = UART mode with automatic baud-rate detection UCSYNC Synchronous mode enable 0b = Asynchronous mode 1b = Synchronous mode Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 959: Ucaxctl1 Register
0b = Disabled. USCI reset released for operation. 1b = Enabled. USCI logic held in reset state. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 960: Ucaxbr0 Register
Table 36-2 shows the modulation pattern. UCOS16 Oversampling mode enabled 0b = Disabled 1b = Enabled Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 961: Ucaxstat Register
USCI busy. This bit indicates if a transmit or receive operation is in progress. 0b = USCI inactive 1b = USCI transmitting or receiving SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 962: Ucaxrxbuf Register
UCTXIFG. The MSB of UCAxTXBUF is not used for 7-bit data and is reset. Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 963: Ucaxirtctl Register
1b = IrDA transceiver delivers a low pulse when a light pulse is seen. UCIRRXFE IrDA receive filter enabled 0b = Receive filter disabled 1b = Receive filter enabled SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 964: Ucaxabctl Register
1b = Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 965: Ucaxie Register
Receive interrupt flag. UCRXIFG is set when UCAxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – UART Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 966: Ucaxiv Register
02h = Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 04h = Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest Universal Serial Communication Interface – UART Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 967: Universal Serial Communication Interface – Spi Mode
USCI Operation – SPI Mode ................37.4 USCI_A SPI Mode Registers ................37.5 USCI_B SPI Mode Registers SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 968: Universal Serial Communication Interface (Usci) Overview
Automatic baud-rate detection for LIN communications • SPI mode USCI_Bx modules support: • C mode • SPI mode Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 969: Usci Introduction – Spi Mode
Independent interrupt capability for receive and transmit • Slave operation in LPM4 Figure 37-1 shows the USCI when configured for SPI mode. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 970: Usci Block Diagram – Spi Mode
Control Set UCFE Transmit State Machine Set UCxTXIFG Figure 37-1. USCI Block Diagram – SPI Mode Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 971: Usci Operation – Spi Mode
UCxRXBUF is LSB justified and the MSB is always reset. The UCMSB bit controls the direction of the transfer and selects LSB or MSB first. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 972: Master Mode
The UCxSTE input signal is not used in 3-pin master mode. Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 973: Slave Mode
The shift operation is halted until the UCxSTE line transitions into the slave transmit active state. The UCxSTE input signal is not used in 3-pin slave mode. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 974: Spi Enable
The polarity and phase of UCxCLK are independently configured via the UCCKPL and UCCKPH control bits of the USCI. Timing for each case is shown in Figure 37-4. Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 975: Using The Spi Mode With Low-Power Modes
The receive or transmit interrupt can wake up the CPU from any low-power mode. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 976: Usci Interrupts In Spi Mode
; Task starts here RETI ; Return RXIFG_ISR ; Vector 2 ; Task starts here RETI ; Return Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 977: Usci_A Spi Mode Registers
USCI_Ax Interrupt Flag Read/write Byte Section 37.4.10 UCAxIV USCI_Ax Interrupt Vector Read Word 0000h Section 37.4.11 SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 978: Ucaxctl0 Register
11b = I C mode UCSYNC Synchronous mode enable 0b = Asynchronous mode 1b = Synchronous mode Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 979: Ucaxctl1 Register
0b = Disabled. USCI reset released for operation. 1b = Enabled. USCI logic held in reset state. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 980: Ucaxbr0 Register
Table 37-7. UCAxMCTL Register Description Field Type Reset Description Reserved Reserved. Always write as 0. Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 981: Ucaxstat Register
USCI busy. This bit indicates if a transmit or receive operation is in progress. 0b = USCI inactive 1b = USCI transmitting or receiving SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 982: Ucaxrxbuf Register
UCTXIFG. The MSB of UCAxTXBUF is not used for 7-bit data and is reset. Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 983: Ucaxie Register
Receive interrupt flag. UCRXIFG is set when UCAxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 984 02h = Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 04h = Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 985: Ucaxiv Register 37.5 Usci_B Spi Mode Registers
USCI_Bx Interrupt Flag Read/write Byte Section 37.5.10 UCBxIV USCI_Bx Interrupt Vector Read Word 0000h Section 37.5.11 SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 986: Ucbxctl0 Register
11b = I C mode UCSYNC Synchronous mode enable 0b = Asynchronous mode 1b = Synchronous mode Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 987: Ucbxctl1 Register
0b = Disabled. USCI reset released for operation. 1b = Enabled. USCI logic held in reset state. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 988: Ucbxbr0 Register
Table 37-19. UCBxMCTL Register Description Field Type Reset Description Reserved Reserved. Always write as 0. Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 989: Ucbxstat Register
USCI busy. This bit indicates if a transmit or receive operation is in progress. 0b = USCI inactive 1b = USCI transmitting or receiving SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 990: Ucbxrxbuf Register
UCTXIFG. The MSB of UCBxTXBUF is not used for 7-bit data and is reset. Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 991: Ucbxie Register
Receive interrupt flag. UCRXIFG is set when UCBxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – SPI Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 992: Ucbxiv Register
02h = Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 04h = Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest Universal Serial Communication Interface – SPI Mode SLAU208Q – June 2008 – Revised March 2018 Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 993: Universal Serial Communication Interface - I 2 C Mode
................38.3 USCI Operation – I C Mode ................38.4 USCI_B I2C Mode Registers 1015 SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – I C Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 994: Universal Serial Communication Interface (Usci) Overview
Automatic baud-rate detection for LIN communications • SPI mode USCI_Bx modules support: • C mode • SPI mode SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – I C Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 995: Usci Introduction - I C Mode
Slave operation in LPM4 Figure 38-1 shows the USCI when configured in I C mode. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – I C Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 996: Usci Operation - I C Mode
SCL are bidirectional and must be connected to a positive supply voltage using a pullup resistor. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – I C Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 997: Usci Initialization And Reset
When R/W = 1, the master receives data from a slave. The ACK bit is sent from the receiver after each byte on the ninth SCL clock. SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – I C Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 998 Data Line Stable Data Change of Data Allowed Figure 38-4. Bit Transfer on I C Bus SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – I C Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 999: C Addressing Modes
Data Any Number Number Figure 38-7. I C Module Addressing Format With Repeated START Condition SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – I C Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...
Page 1000: C Module Operating Modes
UCBxI2COA. The UCSTTIFG flag is set when address received matches the USCI slave address. 1000 SLAU208Q – June 2008 – Revised March 2018 Universal Serial Communication Interface – I C Mode Submit Documentation Feedback Copyright © 2008–2018, Texas Instruments Incorporated...

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