Nokia NSE-6 SERIES Service Manual page 74

NSE–6
System Module
Transmitter power switching timing diagram
Pout
8.3..56.7 us
TXC
TXP
0...56.7 us
TXPWR
150 us
Transmitter power switching timing diagram for normal bursts
Synthesizer clocking
Synthesizers are controlled via serial control bus, which consists of
SDATA, SCLK and SENA1 signals. These lines form a synchronous data
transfer line. SDATA is for the data bits, SCLK is 3.25 MHz clock and
SENA1 is latch enable, which stores the data into counters or registers.
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Technical Documentation
542.8 us
0...58 us
PAMS
50 us
Original 08/98