Nokia NSE-6 SERIES Service Manual page 62

NSE–6
System Module
tor. Phase detector compares this signal to reference signal, which is di-
vided with reference divider from VCTCXO output. Output of the phase
detector is connected into charge pump, which charges or discharges in-
tegrator capacitor in the loop filter depending on the phase of the mea-
sured frequency compared to reference frequency.
Loop filter filters out the pulses and generates DC to control the frequency
of UHF–VCO. Loop filter defines step response of the PLL ( settling time )
and effects to stability of the loop, that's why integrator capacitor has got
a resistor for phase compensation. Other filter components are for side-
band rejection. Dividers are controlled via serial bus. SDATA is for data,
SCLK is serial clock for the bus and SENA1 is a latch enable, which
stores new data into dividers. UHF–synthesizer is the channel synthesiz-
er, so the channel spacing is 200 kHz. 200 kHz is reference frequency
for the phase detector.
R
f ref
PHASE
f_out / M
DET.
VHF PLL is also located into SUMMA. There is 16/17 ( P/P+1 ) dual mo-
dulus prescaler, N– and A–dividers, reference divider, phase detector and
charge pump for the loop filter. VHF local signal is generated with a dis-
crete VCO–circuit. VHF PLL works in the same way as UHF–PLL. VHF–
PLL is locked on fixed frequency, so higher reference frequency is used
to decrease phase noise.
Page 3 – 50
freq.
reference
AFC–controlled VCTCXO
LP
CHARGE
PUMP
Kd
Technical Documentation
VCO
Kvco
M
M = A(P+1) + (N–A)P=
= NP+A
Original 08/98
PAMS
f_out