Table 1-22: Reference Clock Input; Table 1-23: Sync Clock Output - Tektronix AWG70001A Technical Reference

Table 1-21: Trigger input (cont.)
Characteristics
Minimum pulse width
1 kΩ selected
50 Ω selected
Trigger delay to analog output
Trigger hold off
Trigger asynchronous jitter
1 kΩ selected
50 Ω selected
Trigger synchronous jitter

Table 1-22: Reference clock input

Characteristics
Connector type
Input impedance
Input amplitude
Frequency range
Variable frequency range

Table 1-23: Sync clock output

Characteristics
Connector type
Output impedance
AWG70000A Series and AWGSYNC01 Technical Reference
Description
20 ns
20 ns
Asynchronous trigger mode: 32,480 / (2 * fclk) ±20 ns
Synchronous trigger mode: 30,880 / (2 * fclk) ±20 ns
fclk is the frequency of the DAC sampling clock
The DAC sampling clock frequency is displayed on the clock settings tab when the external
clock output is enabled.
8320/fclk ±20 ns
fclk is the frequency of the DAC sampling clock
Trigger hold off is the amount of delay required at the end of a waveform before another trigger
pulse can be processed.
The asynchronous jitter performance is directly proportional the frequency of the DAC sampling
clock. The DAC sampling clock frequency is displayed on the clock settings tab when the
external clock output is enabled.
130 ps , 26 ps for 6.25 GHz DAC sampling clock
p-p rms
90 ps , 17 ps for 12.5 GHz DAC sampling clock
p-p rms
105 ps , 24 ps s for 6.25 GHz DAC sampling clock
p-p rms
70 ps , 14 ps for 12.5 GHz DAC sampling clock
p-p rms
Clock In = 12.5 GHz: 300 fs
rms
Variable Reference In = 156.25 MHz: 400 fs
Fixed Reference In = 10 MHz: 1.7 ps rms, 23.8 ps RJ
Sample rate = 25 GS/s Trigger input impedance = 50 Ω
Description
SMA on rear panel
50 Ω (AC coupled)
–5 dBm to +5 dBm
10 MHz ±100 ppm
35 MHz to 240 MHz.
Acceptable frequency drift while the instrument is operating is ± 0.1%.
Description
SMA on rear panel
50 Ω (AC coupled)
, 4.2 ps RJ BER@10-12
p-p
s, 5.6 ps RJ
rms p-p
BER@10-12
p-p
Specifications
BER@10-12
1–15