AXIOMTEK EP812 User Manual page 49

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EP812 Pentium M All-in-One Capa Board User's Manual
DRAM Data Integrity Mode
This option sets the data integrity mode of the DRAM installed in
the system. The default setting is "Non-ECC".
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at
F0000h-FFFFFh, resulting in better system performance.
However, if any program writes to this memory area, a system
error may result. The default value is "Disabled".
Video BIOS Cacheable
This item allows you to change the Video BIOS location from
ROM to RAM. Video Shadow will increase the video speed.
Video RAM Cacheable
Selecting Enabled allows caching of the video BIOS ROM at
C0000h to C7FFFh, resulting in better video performance.
However, if any program writes to this memory area, a system
error may result. The default value is "Disabled".
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter
ROM. When this area is reserved, it cannot be cached. The user
information of peripherals that need to use this area of system
memory usually discusses their memory requirements. The
default value is "Disabled".
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to
support delay transactions cycles. Select Enabled to support
compliance with PCI specification version 2.1. The options
available are Enabled and Disabled.
AGP Aperture Size (MB)
The field sets aperture size of the graphics. The aperture is a
portion of the PCI memory address range dedicated for graphics
memory address space. Host cycles that hit the aperture range
are forwarded to the AGP without any translation. The options
available are 4M, 8M, 16M, 32M, 64M, 128M and 256M.
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Award BIOS Utility