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Atmel AT32UC3A3256S Manual

32-bit avr microcontroller

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Features

•

High Performance, Low Power 32-bit Atmel

– Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set

– Read-Modify-Write Instructions and Atomic Bit Manipulation

– Performing up to 1.51DMIPS/MHz

• Up to 126 DMIPS Running at 84MHz from Flash (1 Wait-State)

• Up to 63 DMIPS Running at 42MHz from Flash (0 Wait-State)

– Memory Protection Unit

•

Multi-Layer Bus System

– High-Performance Data Transfers on Separate Buses for Increased Performance

– 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral

Communication

– 4 generic DMA Channels for High Bandwidth Data Paths

•

Internal High-Speed Flash

– 256KBytes, 128KBytes, 64KBytes versions

– Single-Cycle Flash Access up to 36MHz

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 4 ms Page Programming Time and 8ms Full-Chip Erase Time

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

•

Internal High-Speed SRAM

– 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus

– 64KBytes (2x32KBytes with independent access) on the Multi-Layer Bus System

•

Interrupt Controller

– Autovectored Low Latency Interrupt Service with Programmable Priority

•

System Functions

– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator

– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL),

– Watchdog Timer, Real-Time Clock Timer

•

External Memories

– Support SDRAM, SRAM, NandFlash (1-bit and 4-bit ECC), Compact Flash

– Up to 66 MHz

•

External Storage device support

– MultiMediaCard (MMC V4.3), Secure-Digital (SD V2.0), SDIO V1.1

– CE-ATA V1.1, FastSD, SmartMedia, Compact Flash

– Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro

– IDE Interface

•

One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S,

AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S

– 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications

– Buffer Encryption/Decryption Capabilities

•

Universal Serial Bus (USB)

– High-Speed USB 2.0 (480Mbit/s) Device and Embedded Host

– Flexible End-Point Configuration and Management with Dedicated DMA Channels

– On-Chip Transceivers Including Pull-Ups

•

One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs.

•

Two Three-Channel 16-bit Timer/Counter (TC)

•

Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Fractionnal Baudrate Generator

®

®

AVR

Microcontroller

32-bit AVR

Microcontroller

AT32UC3A3256S

AT32UC3A3256

AT32UC3A3128S

AT32UC3A3128

AT32UC3A364S

AT32UC3A364

AT32UC3A4256S

AT32UC3A4256

AT32UC3A4128S

AT32UC3A4128

AT32UC3A464S

AT32UC3A464

32072H-AVR32–10/2012

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Summary of Contents for Atmel AT32UC3A3256S

Page 1 – Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro – IDE Interface • One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S, AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S – 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications – Buffer Encryption/Decryption Capabilities •...
Page 2 AT32UC3A3 – Support for SPI and LIN – Optionnal support for IrDA, ISO7816, Hardware Handshaking, RS485 interfaces and Modem Line • Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals • One Synchronous Serial Protocol Controller – Supports I2S and Generic Frame-Based Protocols •...
Page 3: Description
AT32UC3A3 1. Description The AT32UC3A3/A4 is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 84MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con- troller for supporting modern operating systems and real-time operating systems.
Page 4: Overview
AT32UC3A3 2. Overview Block Diagram Figure 2-1. Block Diagram AVR32UC LOCAL BUS JTAG FAST GPIO INTERFACE INTERFACE NEXUS CLASS 2+ MCKO MEMORY PROTECTION UNIT MDO[5..0] 64 KB MSEO[1..0] SRAM INSTR DATA EVTI_N INTERFACE INTERFACE EVTO_N USB_VBIAS USB_VBUS USB HS DMFS, DMHS DPFS, DPHS INTERFACE 256/128/64...
Page 5: Configuration Summary
AT32UC3A3 Configuration Summary The table below lists all AT32UC3A3/A4 memory and package configurations: Table 2-1. Configuration Summary Feature AT32UC3A3256/128/64 AT32UC3A4256/128/64 Flash 256/128/64 KB SRAM 64 KB HSB RAM 64 KB Full Nand flash only GPIO External Interrupts USART Peripheral DMA Channels Generic DMA Channels 1 MMC/SD slot MCI slots...
Page 6: Package And Pinout
AT32UC3A3 3. Package and Pinout Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multi- plexing on I/O Line section. Figure 3-1. TFBGA144 Pinout (top view) PA27 PB03 PX40 PB00 PA28 PA29 PC02 PC04 PC05 DPHS DMHS USB_VBUS...
Page 7 AT32UC3A3 Figure 3-2. LQFP144 Pinout PA21 PX22 PA22 PX41 PA23 PX45 PA24 PX42 PA20 PX14 PA19 PX11 PA18 PX44 PA17 GNDIO GNDANA VDDIO VDDANA PX03 PA25 PX02 PA26 PX34 PB05 PX04 PA00 PX01 PA01 PX05 PA05 PX58 PA03 PX59 PA04 PX00 PA06 PX07...
Page 8 AT32UC3A3 Figure 3-3. VFBGA100 Pinout (top view) PC02 PA28 PA27 PB04 PA30 PC03 PC05 DPHS DMHS USB_VBUS PB00 PB01 PB02 PA29 VDDIO VDDIO PC04 DPFS DMFS GNDPLL PA10 PB11 PA31 GNDIO PB03 PB09 PB08 GNDIO PA11 USB_VBIAS PX16/ PX12 PX10 PX13 PB10 PB07...
Page 9: Peripheral Multiplexing On I/O Lines
AT32UC3A3 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Note that GPIO 44 is physically implemented in silicon but it must be kept unused and config- ured in input mode.
Page 10 AT32UC3A3 Table 3-1. GPIO Controller Function Multiplexing GPIO function Type Supply PA30 VDDIO MCI - DATA[1] USART3 - CLK DMACA - DMAACK[0] MSI - DATA[1] PA31 VDDIO MCI - DATA[2] USART2 - RXD DMACA - DMARQ[0] MSI - DATA[2] PB00 VDDIO MCI - DATA[3] USART2 - TXD...
Page 11 AT32UC3A3 Table 3-1. GPIO Controller Function Multiplexing GPIO function Type Supply PX18 VDDIO EBI - ADDR[16] DMACA - DMAACK[1] TC0 - A2 PX19 VDDIO EBI - ADDR[15] EIC - SCAN[0] TC0 - B2 PX20 VDDIO EBI - ADDR[14] EIC - SCAN[1] TC0 - CLK0 PX21 VDDIO...
Page 12 AT32UC3A3 Table 3-1. GPIO Controller Function Multiplexing GPIO function Type Supply PX56 VDDIO EBI - ADDR[21] EIC - SCAN[2] USART2 - TXD PX57 VDDIO EBI - ADDR[20] EIC - SCAN[1] USART3 - RXD PX58 VDDIO EBI - NCS[0] EIC - SCAN[0] USART3 - TXD PX59 VDDIO...
Page 13 AT32UC3A3 3.2.4 JTAG port connections Table 3-4. JTAG Pinout TFBGA144 QFP144 VFBGA100 Pin name JTAG pin 3.2.5 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irre- spective of the GPIO configuration.
Page 14: Signal Descriptions
AT32UC3A3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-6. Signal Description List Active Signal Name Function Type Level Comments Power VDDIO I/O Power Supply Power 3.0 to 3.6V VDDANA Analog Power Supply Power 3.0 to 3.6V VDDIN Voltage Regulator Input Supply...
Page 15 AT32UC3A3 Table 3-6. Signal Description List Active Signal Name Function Type Level Comments RESET_N Reset Pin Input DMA Controller - DMACA (optional) DMAACK[1:0] DMA Acknowledge Output DMARQ[1:0] DMA Requests Input External Interrupt Controller - EIC EXTINT[7:0] External Interrupt Pins Input SCAN[7:0] Keypad Scan Pins Output...
Page 16 AT32UC3A3 Table 3-6. Signal Description List Active Signal Name Function Type Level Comments SDA10 SDRAM Address 10 Line Output SDCK SDRAM Clock Output SDCKE SDRAM Clock Enable Output SDWE SDRAM Write Enable Output MultiMedia Card Interface - MCI Multimedia Card Clock Output CMD[1:0] Multimedia Card Command...
Page 17 AT32UC3A3 Table 3-6. Signal Description List Active Signal Name Function Type Level Comments Channel 0 Line B Channel 1 Line B Channel 2 Line B CLK0 Channel 0 External Clock Input Input CLK1 Channel 1 External Clock Input Input CLK2 Channel 2 External Clock Input Input Two-wire Interface - TWI0, TWI1...
Page 18 AT32UC3A3 Table 3-6. Signal Description List Active Signal Name Function Type Level Comments DMHS USB High Speed Data - Analog DPHS USB High Speed Data + Analog Connect to the ground through a 6810 ohms (+/- 1%) resistor in parallel with a 10pf capacitor. USB_VBIAS USB VBIAS reference Analog...
Page 19: I/O Line Considerations
AT32UC3A3 I/O Line Considerations 3.4.1 JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. 3.4.2 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product.
Page 20: Power Considerations
AT32UC3A3 Power Considerations 3.5.1 Power Supplies The AT32UC3A3 has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 3.3V nominal • VDDANA: Powers the ADC. Voltage is 3.3V nominal • VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal •...
Page 21: Processor And Architecture
AT32UC3A3 4. Processor and Architecture Rev: 1.4.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual.
Page 22: The Avr32Uc Cpu
AT32UC3A3 The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced OCD system, no caches, and a Memory Protection Unit (MPU).
Page 23 AT32UC3A3 Figure 4-1. Overview of the AVR32UC CPU Power/ Reset system control AVR32UC CPU pipeline Data memory controller Instruction memory controller High High CPU Local Speed High Speed Bus master Speed Bus slave master master 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX).
Page 24 AT32UC3A3 Figure 4-2. The AVR32UC Pipeline Multiply unit Regf ile Regf ile A LU A LU unit Read w rite Pref etch unit Decode unit Load-store unit 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers.
Page 25 AT32UC3A3 The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. Instructions with Unaligned Reference Support Instruction Supported alignment ld.d Word st.d Word 4.3.6 Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if executed: •...
Page 26: Programming Model
AT32UC3A3 Programming Model 4.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 4-3. The AVR32UC Register File Supervisor INT0 INT1 INT2 INT3 Exception Secure Application Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31...
Page 27 AT32UC3A3 Figure 4-5. The Status Register Low Halfword Bit 15 Bit 0 Bit name Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2 on page Table 4-2.
Page 28 AT32UC3A3 All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction.
Page 29 AT32UC3A3 Table 4-3. System Registers (Continued) Reg # Address Name Function JAVA_LV3 Unused in AVR32UC JAVA_LV4 Unused in AVR32UC JAVA_LV5 Unused in AVR32UC JAVA_LV6 Unused in AVR32UC JAVA_LV7 Unused in AVR32UC JTBA Unused in AVR32UC JBCR Unused in AVR32UC 33-63 132-252 Reserved Reserved for future use...
Page 30: Exceptions And Interrupts
AT32UC3A3 Table 4-3. System Registers (Continued) Reg # Address Name Function MPUPSR4 MPU Privilege Select Register region 4 MPUPSR5 MPU Privilege Select Register region 5 MPUPSR6 MPU Privilege Select Register region 6 MPUPSR7 MPU Privilege Select Register region 7 MPUCRA Unused in this version of AVR32UC MPUCRB Unused in this version of AVR32UC...
Page 31 AT32UC3A3 The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 4.5.2 Exceptions and Interrupt Requests When an event other than scall or debug request is received by the core, the following actions...
Page 32 AT32UC3A3 status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability.
Page 33 AT32UC3A3 Table 4-4. Priority and Handler Addresses for Events Priority Handler Address Name Event source Stored Return Address 0x8000_0000 Reset External input Undefined Provided by OCD system OCD Stop CPU OCD system First non-completed instruction EVBA+0x00 Unrecoverable exception Internal PC of offending instruction EVBA+0x04 TLB multiple hit EVBA+0x08...
Page 34: Module Configuration
AT32UC3A3 Module Configuration All AT32UC3A3 parts implement the CPU and Architecture Revision 2. 32072H–AVR32–10/2012...
Page 35: Memories
Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32UC Techni- cal Architecture Manual. The 32-bit physical address space is mapped as follows: Table 5-1. AT32UC3A3A4 Physical Memory Map Size Size Size AT32UC3A3256S AT32UC3A3128S AT32UC3A364S Start Device AT32UC3A3256 AT32UC3A3128 AT32UC3A364...
Page 36: Peripheral Address Map
AT32UC3A3 Table 5-1. AT32UC3A3A4 Physical Memory Map Size Size Size AT32UC3A3256S AT32UC3A3128S AT32UC3A364S Start Device AT32UC3A3256 AT32UC3A3128 AT32UC3A364 Address AT32UC3A4256S AT32UC3A4128S AT32UC3A464S AT32UC3A4256 AT32UC3A4128 AT32UC3A464 HRAMC0 0xFF000000 32KByte 32KByte 32KByte HRAMC1 0xFF008000 32KByte 32KByte 32KByte HSB-PB Bridge A 0xFFFF0000 64KByte...
Page 37 AT32UC3A3 Table 5-2. Peripheral Address Mapping 0xFFFF0C00 Power Manager - PM 0xFFFF0D00 Real Time Counter - RTC 0xFFFF0D30 Watchdog Timer - WDT 0xFFFF0D80 External Interrupt Controller - EIC 0xFFFF1000 GPIO General Purpose Input/Output Controller - GPIO 0xFFFF1400 Universal Synchronous/Asynchronous USART0 Receiver/Transmitter - USART0 0xFFFF1800 Universal Synchronous/Asynchronous...
Page 38: Cpu Local Bus Mapping
AT32UC3A3 Table 5-2. Peripheral Address Mapping 0xFFFF5000 TWIS0 Two-wire Slave Interface - TWIS0 0xFFFF5400 TWIS1 Two-wire Slave Interface - TWIS1 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus.
Page 39 AT32UC3A3 Table 5-3. Local Bus Mapped GPIO Registers Local Bus Port Register Mode Address Access Output Driver Enable Register (ODER) WRITE 0x40000240 Write-only 0x40000244 Write-only CLEAR 0x40000248 Write-only TOGGLE 0x4000024C Write-only Output Value Register (OVR) WRITE 0x40000250 Write-only 0x40000254 Write-only CLEAR 0x40000258 Write-only...
Page 40: Boot Sequence
AT32UC3A3 6. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A3/A4. The behavior after power- up is controlled by the Power Manager. For specific details, refer to Section 7. ”Power Manager (PM)” on page Starting of Clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device.
Page 41: Power Manager (Pm)
AT32UC3A3 7. Power Manager (PM) Rev: 2.3.1.0 Features • Controls integrated oscillators and PLLs • Generates clocks and resets for digital logic • Supports 2 crystal oscillators 0.4-20MHz • Supports 2 PLLs 40-240MHz • Supports 32KHz ultra-low power oscillator • Integrated low-power RC oscillator •...
Page 42: Block Diagram
AT32UC3A3 Block Diagram Figure 7-1. Power Manager Block Diagram Synchronous RCSYS Synchronous clocks Clock Generator CPU, HSB, PBA, PBB O scillator 0 PLL0 PLL1 O scillator 1 G eneric Clock Generic clocks G enerator 32 KHz CLK_32 O scillator OSC /PLL Control signals O scillator Slow clock...
Page 43: Product Dependencies
AT32UC3A3 Product Dependencies 7.4.1 I/O Lines The PM provides a number of generic clock outputs, which can be connected to output pins, multiplexed with I/O lines. The user must first program the I/O controller to assign these pins to their peripheral function. If the I/O pins of the PM are not used by the application, they can be used for other purposes by the I/O controller.
Page 44 AT32UC3A3 Figure 7-2. Oscillator Connections XO UT 7.5.3 32 KHz Oscillator Operation The 32 KHz oscillator operates as described for Oscillator 0 and 1 above. The 32 KHz oscillator is used as source clock for the Real-Time Counter. The oscillator is disabled by default, but can be enabled by writing OSC32EN in OSCCTRL32. The oscillator is an ultra-low power design and remains enabled in all sleep modes except Static mode.
Page 45 AT32UC3A3 Figure 7-3. PLL with Control Logic and Filters PLLMUL Output Mask PLL clock Divider Osc0 clock LOCK Input Divider Osc1 clock PLLEN PLLOPT PLLOSC PLLDIV 7.5.4.1 Enabling the PLL PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1 as clock source.
Page 46 AT32UC3A3 The PLLn:PLLOPT field should be set to proper values according to the PLL operating fre- quency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2. The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be gen- erated on a 0 to 1 transition of these bits.
Page 47 AT32UC3A3 7.5.5.2 Selecting synchronous clock division ratio The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a pres- caler division for the CPU clock by writing CKSEL.CPUDIV to 1 and CPUSEL to the prescaling value, resulting in a CPU clock frequency: CPUSEL...
Page 48 AT32UC3A3 7.5.6.2 Mask ready flag Due to synchronization in the clock generator, there is a slight delay from a mask register is writ- ten until the new mask setting goes into effect. When clearing mask bits, this delay can usually be ignored.
Page 49 AT32UC3A3 Table 7-1. Sleep Modes Osc0,1 BOD & PBA,B PLL0,1, BOD33 & Voltage Index Sleep Mode GCLK SYSTIMER Osc32 RCSYS Bandgap Regulator Idle Stop Full power Frozen Stop Stop Full power Standby Stop Stop Stop Full power Stop Stop Stop Stop Stop Low power...
Page 50 AT32UC3A3 Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source can optionally be divided by any even integer up to 512. Each clock can be independently enabled and disabled, and is also automatically disabled along with peripheral clocks by the Sleep Controller.
Page 51 AT32UC3A3 7.5.8.4 Generic clock implementation The generic clocks are allocated to different functions as shown in Table 7-2 on page Table 7-2. Generic Clock Allocation Clock number Function GCLK0 pin GCLK1 pin GCLK2 pin GCLK3 pin GCLK_USBB GCLK_ABDAC 7.5.9 Divided PB Clocks The clock generator in the Power Manager provides divided PBA and PBB clocks for use by peripherals that require a prescaled PBx clock.
Page 52 AT32UC3A3 Figure 7-6. Reset Controller Block Diagram R C _ R C A U S E R E S E T _ N C P U , H S B , P o w e r-O n P B A , P B B D e te c to r R e s e t O C D , R T C /W D T ,...
Page 53 AT32UC3A3 Table 7-4 on page 53 lists parts of the device that are reset, depending on the reset source. Table 7-4. Effect of the Different Reset Events Power-On External Watchdog BOD33 Error Reset Reset Reset Reset Reset Reset Reset CPU/HSB/PBA/PBB (excluding Power Manager) 32 KHz oscillator RTC control register...
Page 54 AT32UC3A3 7.5.11.3 Brown-Out detector 3V3 The Brown-Out Detector 3V3 (BOD33) monitors one VDDIO supply pin and compares the sup- ply voltage to the brown-out detection 3V3 level, which is typically calibrated at 2V7. The BOD33 is enabled by default, but can be disabled by software. The Brown-Out Detector 3V3 can either generate an interrupt or a reset when the supply voltage is below the brown-out detection3V3 level.
Page 55: User Interface
AT32UC3A3 User Interface Table 7-6. PM Register Memory Map Offset Register Register Name Access Reset State 0x000 Main Clock Control MCCTRL Read/Write 0x00000000 0x0004 Clock Select CKSEL Read/Write 0x00000000 0x008 CPU Mask CPUMASK Read/Write 0x00000003 0x00C HSB Mask HSBMASK Read/Write 0x00000FFF 0x010 PBA Mask...
Page 56 AT32UC3A3 7.6.1 Main Clock Control Register Name: MCCTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 OSC1EN OSC0EN MCSEL • OSC1EN: Oscillator 1 Enable 1: Oscillator 1 is enabled 0: Oscillator 1 is disabled • OSC0EN: Oscillator 0 Enable 1: Oscillator 0 is enabled 0: Oscillator 0 is disabled •...
Page 57 AT32UC3A3 7.6.2 Clock Select Register Name: CKSEL Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 PBBDIV PBBSEL PBADIV PBASEL CPUDIV CPUSEL • PBBDIV: PBB Division Enable PBBDIV = 0: PBB clock equals main clock. (PBBSEL+1) PBBDIV = 1: PBB clock equals main clock divided by 2 •...
Page 58 AT32UC3A3 7.6.3 Clock Mask Registers Name: CPU/HSB/PBA/PBBMASK Access Type: Read/Write Offset: 0x08-0x14 Reset Value: 0x00000003/0x00000FFF/0x001FFFFF/0x000003FF MASK[31:24] MASK[23:16] MASK[15:8] MASK[7:0] • MASK: Clock Mask If bit n is written to zero, the clock for module n is stopped. If bit n is writen to one, the clock for module n is enabled according to the current power mode.
Page 59 AT32UC3A3 Table 7-7. Maskable module clocks in AT32UC3A3. CPUMASK HSBMASK PBAMASK PBBMASK SYSTIMER (compare/count registers clk) ABDAC 31:21 Note: 1. This bit must be set to one if the user wishes to debug the device with a JTAG debugger. 2. This bits must be set to one 32072H–AVR32–10/2012...
Page 60 AT32UC3A3 7.6.4 PLL Control Registers Name: PLL0,1 Access Type: Read/Write Offset: 0x20-0x24 Reset Value: 0x00000000 PLLTEST PLLCOUNT PLLMUL PLLDIV PLLOPT PLLOSC PLLEN • PLLTEST: PLL Test Reserved for internal use. Always write to 0. • PLLCOUNT: PLL Count Specifies the number of slow clock cycles before ISR.LOCKn will be set after PLLn has been written, or after PLLn has been automatically re-enabled after exiting a sleep mode.
Page 61 AT32UC3A3 • PLLEN: PLL Enable 0: PLL is disabled. 1: PLL is enabled. 32072H–AVR32–10/2012...
Page 62 AT32UC3A3 7.6.5 Oscillator 0/1 Control Registers Name: OSCCTRL0,1 Access Type: Read/Write Offset: 0x28-0x2C Reset Value: 0x00000000 STARTUP MODE • STARTUP: Oscillator Startup Time Select startup time for the oscillator. Number of RC oscillator Approximative Equivalent time STARTUP clock cycle (RCSYS = 115 kHz) 560 us 1.1 ms 2048...
Page 63 AT32UC3A3 7.6.6 32 KHz Oscillator Control Register Name: OSCCTRL32 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 STARTUP MODE OSC32EN • STARTUP: Oscillator Startup Time Select startup time for 32 KHz oscillator Number of RC oscillator Approximative Equivalent time STARTUP clock cycle (RCSYS = 115 kHz) 1.1 ms...
Page 64 AT32UC3A3 7.6.7 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x40 Reset Value: 0x00000000 BOD33DET BODDET OSC32RDY OSC1RDY OSC0RDY MSKRDY CKRDY LOCK1 LOCK0 Writing a one to a bit in this register will set the corresponding bit in IMR. Writing a zero to a bit in this register has no effect. 32072H–AVR32–10/2012...
Page 65 AT32UC3A3 7.6.8 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x44 Reset Value: 0x00000000 BOD33DET BODDET OSC32RDY OSC1RDY OSC0RDY MSKRDY CKRDY LOCK1 LOCK0 Writing a one to a bit in this register will clear the corresponding bit in IMR. Writing a zero to a bit in this register has no effect. 32072H–AVR32–10/2012...
Page 66 AT32UC3A3 7.6.9 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x48 Reset Value: 0x00000000 BOD33DET BODDET OSC32RDY OSC1RDY OSC0RDY MSKRDY CKRDY LOCK1 LOCK0 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one.
Page 67 AT32UC3A3 7.6.10 Interrupt Status Register Name: Access Type: Read-only Offset: 0x4C Reset Value: 0x00000000 BOD33DET BODDET OSC32RDY OSC1RDY OSC0RDY MSKRDY CKRDY LOCK1 LOCK0 • BOD33DET: Brown out detection BOD33 has detected that power supply is This bit is set when a 0 to 1 transition on POSCSR.BOD33DET bit is detected: going below BOD33 reference value.
Page 68 AT32UC3A3 • LOCK1: PLL1 locked PLL 1 is locked and ready to be selected as This bit is set when a 0 to 1 transition on the POSCSR.LOCK1 bit is detected: clock source. This bit is cleared when the corresponding bit in ICR is written to one. •...
Page 69 AT32UC3A3 7.6.11 Interrupt Clear Register Name: Access Type: Write-only Offset: 0x50 Reset Value: 0x00000000 BOD33DET BODDET OSC32RDY OSC1RDY OSC0RDY MSKRDY CKRDY LOCK1 LOCK0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request. 32072H–AVR32–10/2012...
Page 70 AT32UC3A3 7.6.12 Power and Oscillators Status Register Name: POSCSR Access Type: Read-only Offset: 0x54 Reset Value: 0x00000020 BOD33DET BODDET OSC32RDY OSC1RDY OSC0RDY MSKRDY CKRDY LOCK1 LOCK0 • BOD33DET: Brown out 3V3 detection 0: No BOD33 event 1: BOD33 has detected that power supply is going below BOD33 reference value. •...
Page 71 AT32UC3A3 7.6.13 Generic Clock Control Register Name: GCCTRLx Access Type: Read/Write Offset: 0x60 - 0x74 Reset Value: 0x00000000 DIV[7:0] DIVEN PLLSEL OSCSEL There is one GCCTRL register per generic clock in the design. • DIV: Division Factor • DIVEN: Divide Enable 0: The generic clock equals the undivided source clock.
Page 72 AT32UC3A3 7.6.14 RC Oscillator Calibration Register Name: RCCR Access Type: Read/Write Offset: 0xC0 Reset Value: 0x00000000 CALIB CALIB • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect. •...
Page 73 AT32UC3A3 7.6.15 Bandgap Calibration Register Name: BGCR Access Type: Read/Write Offset: 0xC4 Reset Value: 0x00000000 CALIB • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect. •...
Page 74 AT32UC3A3 7.6.16 PM Voltage Regulator Calibration Register Name: VREGCR Access Type: Read/Write Offset: 0xC8 Reset Value: 0x00000000 CALIB • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect. Calibration value for Voltage Regulator.
Page 75 AT32UC3A3 7.6.17 BOD Control Register Name: Access Type: Read/Write Offset: 0xD0 Reset Value: 0x00000000 CTRL HYST LEVEL • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect. •...
Page 76 AT32UC3A3 7.6.18 BOD33 Control Register Name: BOD33 Access Type: Read/Write Offset: 0xD4 Reset Value: 0x0000010X CTRL LEVEL • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect. •...
Page 77 AT32UC3A3 7.6.19 Reset Cause Register Name: RCAUSE Access Type: Read-only Offset: 0x140 Reset Value: 0x00000000 BOD33 OCDRST CPUERR JTAG • BOD33: Brown-out 3V3 Reset The CPU was reset due to the supply voltage 3V3 being lower than the brown-out threshold level. •...
Page 78 AT32UC3A3 7.6.20 Asynchronous Wake Up Enable Name: AWEN Access Type: Read/Write Offset: 0x144 Reset Value: USB_WAKEN • USB_WAKEN : Wake Up Enable Register Writing a zero to this bit will disable the USB wake up. Writing a one to this bit will enable the USB wake up. 32072H–AVR32–10/2012...
Page 79 AT32UC3A3 7.6.21 General Purpose Low-power Register Name: GPLP Access Type: Read/Write Offset: 0x200 Reset Value: 0x00000000 GPLP GPLP GPLP GPLP These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset will keep the content of these registers untouched.
Page 80: Real Time Counter (Rtc)
AT32UC3A3 8. Real Time Counter (RTC) Rev: 2.4.0.1 Features • 32-bit real-time counter with 16-bit prescaler • Clocked from RC oscillator or 32KHz oscillator • Long delays – Max timeout 272years • High resolution: Max count frequency 16KHz • Extremely low power consumption •...
Page 81: Functional Description
AT32UC3A3 8.4.1 Power Management The RTC remains operating in all sleep modes except Static mode. Interrupts are not available in DeepStop mode. 8.4.2 Clocks The RTC can use the system RC oscillator as clock source. This oscillator is always enabled whenever this module is active.
Page 82 AT32UC3A3 The RTC count value can be read from or written to the Value register (VAL). Due to synchroni- zation, continuous reading of the VAL register with the lowest prescaler setting will skip every other value. 8.5.1.3 RTC interrupt The RTC interrupt is enabled by writing a one to the Top Interrupt bit in the Interrupt Enable Reg- ister (IER.TOPI), and is disabled by writing a one to the Top Interrupt bit in the Interrupt Disable Register (IDR.TOPI).
Page 83: User Interface
AT32UC3A3 User Interface Table 8-1. RTC Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CTRL Read/Write 0x00010000 0x04 Value Register Read/Write 0x00000000 0x08 Top Register Read/Write 0xFFFFFFFF 0x10 Interrupt Enable Register Write-only 0x00000000 0x14 Interrupt Disable Register Write-only 0x00000000 0x18...
Page 84 AT32UC3A3 8.6.1 Control Register Name: CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00010000 CLKEN PSEL BUSY CLK32 WAKEN PCLR • CLKEN: Clock Enable 1: The clock is enabled. 0: The clock is disabled. • PSEL: Prescale Select Selects prescaler bit PSEL as source clock for the RTC. •...
Page 85 AT32UC3A3 8.6.2 Value Register Name: Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 VAL[31:24] VAL[23:16] VAL[15:8] VAL[7:0] • VAL[31:0]: RTC Value This value is incremented on every rising edge of the source clock. 32072H–AVR32–10/2012...
Page 86 AT32UC3A3 8.6.3 Top Register Name: Access Type: Read/Write Offset: 0x08 Reset Value: 0xFFFFFFFF VAL[31:24] VAL[23:16] VAL[15:8] VAL[7:0] • VAL[31:0]: RTC Top Value VAL wraps at this value. 32072H–AVR32–10/2012...
Page 87 AT32UC3A3 8.6.4 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 TOPI Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 88 AT32UC3A3 8.6.5 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 TOPI Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 89 AT32UC3A3 8.6.6 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 TOPI 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one.
Page 90 AT32UC3A3 8.6.7 Interrupt Status Register Name: Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 TOPI • TOPI: Top Interrupt This bit is set when VAL has wrapped at its top value. This bit is cleared when the corresponding bit in ICR is written to one. 32072H–AVR32–10/2012...
Page 91 AT32UC3A3 8.6.8 Interrupt Clear Register Name: Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 TOPI Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 32072H–AVR32–10/2012...
Page 92: Watchdog Timer (Wdt)
AT32UC3A3 9. Watchdog Timer (WDT) Rev: 2.4.0.1 Features • Watchdog timer counter with 32-bit prescaler • Clocked from the system RC oscillator (RCSYS) Overview The Watchdog Timer (WDT) has a prescaler generating a time-out period. This prescaler is clocked from the RC oscillator. The watchdog timer must be periodically reset by software within the time-out period, otherwise, the device is reset and starts executing from the boot vector.
Page 93: Functional Description
AT32UC3A3 Functional Description The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.EN). This also enables the system RC clock (CLK_RCSYS) for the prescaler. The Prescale Select field (PSEL) in the CTRL register selects the watchdog time-out period: (PSEL+1) The next time-out period will begin as soon as the watchdog reset has occurred and count down during the reset sequence.
Page 94 AT32UC3A3 9.6.1 Control Register Name: CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 PSEL • KEY: Write protection key This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This field always reads as zero.
Page 95 AT32UC3A3 9.6.2 Clear Register Name: Access Type: Write-only Offset: 0x04 Reset Value: 0x00000000 CLR[31:24] CLR[23:16] CLR[15:8] CLR[7:0] • CLR: Writing periodically any value to this field when the WDT is enabled, within the watchdog time-out period, will prevent a watchdog reset. This field always reads as zero.
Page 96: Interrupt Controller (Intc)
AT32UC3A3 10. Interrupt Controller (INTC) Rev: 1.0.1.5 10.1 Features • Autovectored low latency interrupt service with programmable priority – 4 priority levels for regular, maskable interrupts – One Non-Maskable Interrupt • Up to 64 groups of interrupts with up to 32 interrupt requests in each group 10.2 Overview The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an inter-...
Page 97: Product Dependencies
AT32UC3A3 Figure 10-1. INTC Block Diagram Interrupt Controller NMIREQ Masks SREG Masks I[3-0]M ValReqN GrpReqN INT_level, IPRn offset IRRn INTLEVEL Request Masking IREQ63 ValReq1 GrpReq1 IREQ34 IREQ33 INT_level, IPR1 IREQ32 AUTOVECTOR offset IRR1 IREQ31 ValReq0 GrpReq0 IREQ2 IREQ1 INT_level, IPR0 IREQ0 offset IRR0...
Page 98 AT32UC3A3 Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, gets its corresponding ValReq line asserted. Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status register, namely Interrupt Level 3 Mask (I3M) to Interrupt Level 0 Mask (I0M), and Global Inter- rupt Mask (GM).
Page 99 AT32UC3A3 pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared. 32072H–AVR32–10/2012...
Page 100: User Interface
AT32UC3A3 10.6 User Interface Table 10-1. INTC Register Memory Map Offset Register Register Name Access Reset 0x000 Interrupt Priority Register 0 IPR0 Read/Write 0x00000000 0x004 Interrupt Priority Register 1 IPR1 Read/Write 0x00000000 0x0FC Interrupt Priority Register 63 IPR63 Read/Write 0x00000000 0x100 Interrupt Request Register 0 IRR0...
Page 101 AT32UC3A3 10.6.1 Interrupt Priority Registers Name: IPR0...IPR63 Access Type: Read/Write Offset: 0x000 - 0x0FC Reset Value: 0x00000000 INTLEVEL AUTOVECTOR[13:8] AUTOVECTOR[7:0] • INTLEVEL: Interrupt Level Indicates the EVBA-relative offset of the interrupt handler of the corresponding group: 00: INT0: Lowest priority 01: INT1 10: INT2 11: INT3: Highest priority...
Page 102 AT32UC3A3 10.6.2 Interrupt Request Registers Name: IRR0...IRR63 Access Type: Read-only Offset: 0x0FF - 0x1FC Reset Value: IRR[32*x+31] IRR[32*x+30] IRR[32*x+29] IRR[32*x+28] IRR[32*x+27] IRR[32*x+26] IRR[32*x+25] IRR[32*x+24] IRR[32*x+23] IRR[32*x+22] IRR[32*x+21] IRR[32*x+20] IRR[32*x+19] IRR[32*x+18] IRR[32*x+17] IRR[32*x+16] IRR[32*x+15] IRR[32*x+14] IRR[32*x+13] IRR[32*x+12] IRR[32*x+11] IRR[32*x+10] IRR[32*x+9] IRR[32*x+8] IRR[32*x+7] IRR[32*x+6] IRR[32*x+5]...
Page 103 AT32UC3A3 10.6.3 Interrupt Cause Registers Name: ICR0...ICR3 Access Type: Read-only Offset: 0x200 - 0x20C Reset Value: CAUSE • CAUSE: Interrupt Group Causing Interrupt of Priority n ICRn identifies the group with the highest priority that has a pending interrupt of level n. This value is only defined when at least one interrupt of level n is pending.
Page 104: Interrupt Request Signal Map
AT32UC3A3 10.7 Interrupt Request Signal Map The various modules may output Interrupt request signals. These signals are routed to the Inter- rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64 groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level.
Page 105 AT32UC3A3 Table 10-2. Interrupt Request Signal Map Peripheral DMA Controller PDCA 0 Peripheral DMA Controller PDCA 1 Peripheral DMA Controller PDCA 2 Peripheral DMA Controller PDCA 3 Peripheral DMA Controller PDCA 4 Peripheral DMA Controller PDCA 5 Peripheral DMA Controller PDCA 6 Peripheral DMA Controller PDCA 7...
Page 106 AT32UC3A3 Table 10-2. Interrupt Request Signal Map DMA Controller DMACA BLOCK DMA Controller DMACA DSTT DMA Controller DMACA ERR DMA Controller DMACA SRCT DMA Controller DMACA TFR Memory Stick Interface Two-wire Slave Interface TWIS0 Two-wire Slave Interface TWIS1 Error code corrector Hamming and Reed ECCHRS Solomon 32072H–AVR32–10/2012...
Page 107: External Interrupt Controller (Eic)
AT32UC3A3 11. External Interrupt Controller (EIC) Rev: 2.4.0.0 11.1 Features • Dedicated interrupt request for each interrupt • Individually maskable interrupts • Interrupt on rising or falling edge • Interrupt on high or low level • Asynchronous interrupts for sleep modes without clock •...
Page 108: Block Diagram
AT32UC3A3 11.3 Block Diagram Figure 11-1. EIC Block Diagram L E V E L M O D E A S Y N C E D G E P o la r it y A s y n c h r o n u s I C R I E R D I S...
Page 109: Functional Description
AT32UC3A3 11.5.3 Clocks The clock for the EIC bus interface (CLK_EIC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. The filter and synchronous edge/level detector runs on a clock which is stopped in any of the sleep modes where the system RC oscillator is not running.
Page 110 AT32UC3A3 gate to the interrupt controller. However, the corresponding bit in ISR will be set, and EIC_WAKE will be set. If the CTRL.INTn bit is zero, then the corresponding bit in ISR will always be zero. Disabling an external interrupt by writing to the DIS.INTn bit will clear the corresponding bit in ISR. 11.6.2 Synchronization and Filtering of External Interrupts In synchronous mode the pin value of the EXTINTn pin is synchronized to CLK_SYNC, so...
Page 111 AT32UC3A3 11.6.3 Non-Maskable Interrupt The NMI supports the same features as the external interrupts, and is accessed through the same registers. The description in Section 11.6.1 should be followed, accessing the NMI bit instead of the INTn bits. The NMI is non-maskable within the CPU in the sense that it can interrupt any other execution mode.
Page 112 AT32UC3A3 11.6.6 Keypad scan support The External Interrupt Controller also includes support for keypad scanning. The keypad scan feature is compatible with keypads organized as rows and columns, where a row is shorted against a column when a key is pressed. The rows should be connected to the external interrupt pins with pull-ups enabled in the I/O Con- troller.
Page 113: User Interface
AT32UC3A3 11.7 User Interface Table 11-2. EIC Register Memory Map Offset Register Register Name Access Reset 0x000 Interrupt Enable Register Write-only 0x00000000 0x004 Interrupt Disable Register Write-only 0x00000000 0x008 Interrupt Mask Register Read-only 0x00000000 0x00C Interrupt Status Register Read-only 0x00000000 0x010 Interrupt Clear Register Write-only...
Page 114 AT32UC3A3 11.7.1 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in IMR. •...
Page 115 AT32UC3A3 11.7.2 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x004 Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR. •...
Page 116 AT32UC3A3 11.7.3 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x008 Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one.
Page 117 AT32UC3A3 11.7.4 Interrupt Status Register Name: Access Type: Read-only Offset: 0x00C Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: An interrupt event has not occurred 1: An interrupt event has occurred This bit is cleared by writing a one to the corresponding bit in ICR.
Page 118 AT32UC3A3 11.7.5 Interrupt Clear Register Name: Access Type: Write-only Offset: 0x010 Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in ISR. •...
Page 119 AT32UC3A3 11.7.6 Mode Register Name: MODE Access Type: Read/Write Offset: 0x014 Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The external interrupt is edge triggered. 1: The external interrupt is level triggered. •...
Page 120 AT32UC3A3 11.7.7 Edge Register Name: EDGE Access Type: Read/Write Offset: 0x018 Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The external interrupt triggers on falling edge. 1: The external interrupt triggers on rising edge. •...
Page 121 AT32UC3A3 11.7.8 Level Register Name: LEVEL Access Type: Read/Write Offset: 0x01C Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The external interrupt triggers on low level. 1: The external interrupt triggers on high level. •...
Page 122 AT32UC3A3 11.7.9 Filter Register Name: FILTER Access Type: Read/Write Offset: 0x020 Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The external interrupt is not filtered. 1: The external interrupt is filtered. •...
Page 123 AT32UC3A3 11.7.10 Test Register Name: TEST Access Type: Read/Write Offset: 0x024 Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • TESTEN: Test Enable 0: This bit disables external interrupt test mode. 1: This bit enables external interrupt test mode. •...
Page 124 AT32UC3A3 11.7.11 Asynchronous Register Name: ASYNC Access Type: Read/Write Offset: 0x028 Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The external interrupt is synchronized to CLK_SYNC. 1: The external interrupt is asynchronous. •...
Page 125 AT32UC3A3 11.7.12 Scan Register Name: SCAN Access Type: Read/Write Offset: 0x2C Reset Value: 0x0000000 PIN[2:0] PRESC[4:0] • 0: Keypad scanning is disabled 1: Keypad scanning is enabled • PRESC Prescale select for the keypad scan rate: (SCAN.PRESC+1) Scan rate = 2 The RC clock period can be found in the Electrical Characteristics section.
Page 126 AT32UC3A3 11.7.13 Enable Register Name: Access Type: Write-only Offset: 0x030 Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will enable the corresponding external interrupt. •...
Page 127 AT32UC3A3 11.7.14 Disable Register Name: Access Type: Write-only Offset: 0x034 Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will disable the corresponding external interrupt. •...
Page 128 AT32UC3A3 11.7.15 Control Register Name: CTRL Access Type: Read-only Offset: 0x038 Reset Value: 0x00000000 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • INTn: External Interrupt n 0: The corresponding external interrupt is disabled. 1: The corresponding external interrupt is enabled. •...
Page 129: Module Configuration
AT32UC3A3 11.8 Module Configuration The specific configuration for each EIC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 11-3. Module Configuration Feature Number of external interrupts, including NMI...
Page 130: Flash Controller (Flashc)
AT32UC3A3 12. Flash Controller (FLASHC) Rev: 2.2.1.3 12.1 Features • Controls flash block with dual read ports allowing staggered reads. • Supports 0 and 1 wait state bus access. • Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per clock cycle.
Page 131: Functional Description
AT32UC3A3 12.4 Functional description 12.4.1 Bus interfaces The None has two bus interfaces, one High-Speed Bus (HSB) interface for reads from the flash array and writes to the page buffer, and one Peripheral Bus (PB) interface for writing commands and control to and reading status from the controller. 12.4.2 Memory organization To maximize performance for high clock-frequency systems, None interfaces to a flash block...
Page 132 AT32UC3A3 The flash controller supports flash blocks with up to 2^21 word addresses, as displayed in Figure 12-1. Reading the memory space between address pw and 2^21-1 returns an undefined result. The User page is permanently mapped to word address 2^21. Table 12-1.
Page 133 AT32UC3A3 Figure 12-3. High Speed Mode Frequency 1 wait state 0 wait state Frequency limit for 0 wait state operation Speed mode 12.4.6 Quick Page Read A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed page.
Page 134: Flash Commands
AT32UC3A3 The page buffer is not automatically reset after a page write. The programmer should do this manually by issuing the Clear Page Buffer flash command. This can be done after a page write, or before the page buffer is loaded with data to be stored to the flash page. Example: Writing a word into word address 130 of a flash with 128 words in the page buffer.
Page 135 AT32UC3A3 If the current command writes or erases a page in a locked region, or a page protected by the BOOTPROT fuses, the command has no effect on the flash memory; however, the LOCKE flag is set in the FSR register. This flag is automatically cleared by a read access to the FSR register. 12.5.1 Write/erase page operation Flash technology requires that an erase must be done before programming.
Page 136: General-Purpose Fuse Bits
AT32UC3A3 set and the command is cancelled. If the bit LOCKE has been written to 1 in FCR, the interrupt line rises. When the command is complete, the bit FRDY bit in the Flash Status Register (FSR) is set. If an interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash control- ler is set.
Page 137 AT32UC3A3 through a dedicated Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions.: Table 12-2. General-purpose fuses with special functions General- Purpose fuse number Name Usage 15:0 LOCK Region lock bits.
Page 138: Security Bit
AT32UC3A3 To erase or write a general-purpose fuse bit, the commands Write General-Purpose Fuse Bit (WGPB) and Erase General-Purpose Fuse Bit (EGPB) are provided. Writing one of these com- mands, together with the number of the fuse to write/erase, performs the desired operation. An entire General-Purpose Fuse byte can be written at a time by using the Program GP Fuse Byte (PGPFB) instruction.
Page 139: User Interface
AT32UC3A3 12.8 User interface 12.8.1 Address map The following addresses are used by the None. All offsets are relative to the base address allo- cated to the flash controller. Table 12-4. Flash controller register mapping Reset Offset Register Name Access state Flash Control Register Flash Command Register...
Page 140 AT32UC3A3 12.8.2 Flash Control Register Name: Access Type: Read/Write Offset: 0x00 Reset value: 0x00000000 PROGE LOCKE FRDY • FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready generates an interrupt. • LOCKE: Lock Error Interrupt Enable 0: Lock Error does not generate an interrupt.
Page 141 AT32UC3A3 12.8.3 Flash Command Register Name: FCMD Access Type: Read/Write Offset: 0x04 Reset value: 0x00000000 The FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to be ignored, and the PROGE bit to be set. PAGEN [15:8] PAGEN [7:0] •...
Page 142 AT32UC3A3 Table 12-5. Set of commands Command Value Mnemonic Quick Page Read User Page QPRUP Read High Speed Enable HSEN Read High Speed Disable HSDIS • PAGEN: Page number The PAGEN field is used to address a page or fuse bit for certain operations. In order to simplify programming, the PAGEN field is automatically updated every time the page buffer is written to.
Page 143 AT32UC3A3 12.8.4 Flash Status Register Name: Access Type: Read/Write Offset: 0x08 Reset value: 0x00000000 LOCK15 LOCK14 LOCK13 LOCK12 LOCK11 LOCK10 LOCK9 LOCK8 LOCK7 LOCK6 LOCK5 LOCK4 LOCK3 LOCK2 LOCK1 LOCK0 QPRR SECURITY PROGE LOCKE FRDY • FRDY: Flash Ready Status 0: The flash controller is busy and the application must wait before running a new command.
Page 144 AT32UC3A3 • FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 12-7. Flash size Flash Size 32 KByte 64 kByte 128 kByte 256 kByte 384 kByte 512 kByte 768 kByte 1024 kByte •...
Page 145 AT32UC3A3 12.8.5 Flash General Purpose Fuse Register High Name: FGPFRHI Access Type: Read Offset: 0x0C Reset value: GPF63 GPF62 GPF61 GPF60 GPF59 GPF58 GPF57 GPF56 GPF55 GPF54 GPF53 GPF52 GPF51 GPF50 GPF49 GPF48 GPF47 GPF46 GPF45 GPF44 GPF43 GPF42 GPF41 GPF40 GPF39 GPF38...
Page 146 AT32UC3A3 12.8.6 Flash General Purpose Fuse Register Low Name: FGPFRLO Access Type: Read Offset: 0x10 Reset value: GPF31 GPF30 GPF29 GPF28 GPF27 GPF26 GPF25 GPF24 GPF23 GPF22 GPF21 GPF20 GPF19 GPF18 GPF17 GPF16 GPF15 GPF14 GPF13 GPF12 GPF11 GPF10 GPF09 GPF08 GPF07 GPF06...
Page 147: Fuses Settings
AT32UC3A3 12.9 Fuses Settings The flash block contains 32 general purpose fuses. These 32 fuses can be found in the Flash General Purpose Fuse Register Low (FGPFRLO) of the Flash Controller (FLASHC). Some of the FGPFRLO fuses have defined meanings outside the FLASHC and are described in this section.
Page 148: Serial Number In The Factory Page
AT32UC3A3 • GPF30 reserved for future use • GPF29 reserved for future use • BODEN fuses set to 0b11. BOD is disabled. • BODHYST fuse set to 0b1. The BOD hystersis is enabled. • BODLEVEL fuses set to 0b111111. This is the minimum voltage trigger level. BOD will never trigger as this level is below the POR level.
Page 149: Hsb Bus Matrix (Hmatrix)
AT32UC3A3 13. HSB Bus Matrix (HMATRIX) Rev: 2.3.0.2 13.1 Features • User Interface on peripheral bus • Configurable Number of Masters (Up to sixteen) • Configurable Number of Slaves (Up to sixteen) • One Decoder for Each Master • • Programmable Arbitration for Each Slave –...
Page 150 AT32UC3A3 At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master and fixed default master. 13.4.1.1 No Default Master At the end of the current access, if no other request is pending, the slave is disconnected from...
Page 151 AT32UC3A3 3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is man- aged differently for undefined length burst. 4.
Page 152 AT32UC3A3 the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters that perform significant bursts. •...
Page 153: User Interface
AT32UC3A3 13.5 User Interface Table 13-1. HMATRIX Register Memory Map Offset Register Name Access Reset Value 0x0000 Master Configuration Register 0 MCFG0 Read/Write 0x00000002 0x0004 Master Configuration Register 1 MCFG1 Read/Write 0x00000002 0x0008 Master Configuration Register 2 MCFG2 Read/Write 0x00000002 0x000C Master Configuration Register 3 MCFG3...
Page 154 AT32UC3A3 Table 13-1. HMATRIX Register Memory Map (Continued) Offset Register Name Access Reset Value 0x008C Priority Register B for Slave 1 PRBS1 Read/Write 0x00000000 0x0090 Priority Register A for Slave 2 PRAS2 Read/Write 0x00000000 0x0094 Priority Register B for Slave 2 PRBS2 Read/Write 0x00000000...
Page 155 AT32UC3A3 Table 13-1. HMATRIX Register Memory Map (Continued) Offset Register Name Access Reset Value 0x012C Special Function Register 7 SFR7 Read/Write – 0x0130 Special Function Register 8 SFR8 Read/Write – 0x0134 Special Function Register 9 SFR9 Read/Write – 0x0138 Special Function Register 10 SFR10 Read/Write –...
Page 156 AT32UC3A3 13.5.1 Master Configuration Registers Name: MCFG0...MCFG15 Access Type: Read/Write Offset: 0x00 - 0x3C Reset Value: 0x00000002 – – – – – – – – – – – – – – – – – – – – – – – –...
Page 157 AT32UC3A3 13.5.2 Slave Configuration Registers Name: SCFG0...SCFG15 Access Type: Read/Write Offset: 0x40 - 0x7C Reset Value: 0x00000010 – – – – – – – ARBT – – FIXED_DEFMSTR DEFMSTR_TYPE – – – – – – – – SLOT_CYCLE • ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority Arbitration •...
Page 158 AT32UC3A3 13.5.3 Priority Registers A For Slaves Name: PRAS0...PRAS15 Access Type: Read/Write Offset: Reset Value: 0x00000000 – – M7PR – – M6PR – – M5PR – – M4PR – – M3PR – – M2PR – – M1PR – – M0PR •...
Page 159 AT32UC3A3 13.5.4 Priority Registers B For Slaves Name: PRBS0...PRBS15 Access Type: Read/Write Offset: Reset Value: 0x00000000 – – M15PR – – M14PR – – M13PR – – M12PR – – M11PR – – M10PR – – M9PR – – M8PR •...
Page 160 AT32UC3A3 13.5.5 Special Function Registers Name: SFR0...SFR15 Access Type: Read/Write Offset: 0x110 - 0x115 Reset Value: • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those will be defined where they are used. 32072H–AVR32–10/2012...
Page 161: Bus Matrix Connections
AT32UC3A3 13.6 Bus Matrix Connections Accesses to unused areas returns an error result to the master requesting such an access. The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing a different memory mapping per master. The master number in the table below can be used to index the HMATRIX control registers.
Page 162 AT32UC3A3 Figure 13-1. HMATRIX Master / Slave Connections HMATRIX SLAVES CPU Data Instruction CPU SAB PDCA DMACA Master 0 DMACA Master 1 USBB 32072H–AVR32–10/2012...
Page 163: External Bus Interface (Ebi)
AT32UC3A3 14. External Bus Interface (EBI) Rev.: 1.7.0.1 14.1 Features • Optimized for application memory space support • Integrates three external memory controllers: – Static Memory Controller (SMC) – SDRAM Controller (SDRAMC) – Error Corrected Code (ECCHRS) controller • Additional logic for NAND Flash/SmartMedia and CompactFlash support –...
Page 164: Block Diagram
AT32UC3A3 14.3 Block Diagram Figure 14-1. EBI Block Diagram INTC SDRAMC_irq ECCHRS_irq HMATRIX DATA[15:0] SDRAM Controller NWE1 NWE0 Static Memory Controller NCS[5:0] ADDR[23:0] ECCHRS Controller Controller Logic SDA10 NAND Flash SDWE SmartMedia Logic SDCK registers SDCKE Compact FLash NANDOE Logic NANDWE Address Chip Select...
Page 165: I/O Lines Description
AT32UC3A3 14.4 I/O Lines Description Table 14-1. EBI I/O Lines Description Alternate Active Pin Name Name Pin Description Type Level EBI common lines DATA[15:0] Data Bus SMC dedicated lines ADDR[1] SMC Address Bus Line 1 Output ADDR[12] SMC Address Bus Line 12 Output ADDR[15] SMC Address Bus Line 15...
Page 166: Product Dependencies
AT32UC3A3 Alternate Active Pin Name Name Pin Description Type Level SDRAMC Bank 1 ADDR[17] Output ADDR[17] SMCAddress Bus Line 17 SMC/CompactFlash shared lines SMC Read Signal Output CFNOE CompactFlash CFNOE NWE0-NWE SMC Write Enable10 or Write enable NWE0 Output CFNWE CompactFlash CFNWE NCS[4] SMC Chip Select Line 4...
Page 167 AT32UC3A3 • CLK_ECCHRS Refer to Table 14-2 on page 167 to configure those clocks. Table 14-2. EBI Clocks Configuration Type of the Interfaced Device Clocks SRAM, PROM, Clocks name NandFlash type SDRAM EPROM, CompactFlash SmartMedia EEPROM, Flash CLK_EBI CLK_SDRAMC CLK_SMC CLK_ECCHRS 14.5.4 Interrupts...
Page 168: Functional Description
AT32UC3A3 Table 14-3. EBI Special Function Register Fields Description SFR6 Bit Number Bit name Description 0 = Chip Select 2 (NCS[2]) is connected to a Static Memory device. For each access to the NCS[2] memory space, all related pins act as SMC pins CS2A 1 = Chip Select 2 (NCS[2]) is connected to a NandFlash or a SmartMedia device.
Page 169 AT32UC3A3 14.6.5 CompactFlash Support The External Bus Interface integrates circuitry that interfaces to CompactFlash devices. The CompactFlash logic is driven by the SMC on the NCS[4] and/or NCS[5] address space. Writing to the HMATRIX.SFR6.CS4A and/or HMATRIX.SFR6.CS5A bits the appropriate value enables this logic.
Page 170 AT32UC3A3 ured to drive 8-bit memory devices on the corresponding NCS pin (NCS[4] or NCS[5]). The Data Bus Width (DBW) field in the SMC Mode (MODE) register of the NCS[4] and/or NCS[5] address space must be written as shown in Table 14-5 on page 170 to enable the required access type.
Page 171 AT32UC3A3 Figure 14-3. CompactFlash Read/Write Control Signals Compact Flash Logic CFNOE CFNWE CFNIORD NWR0/NWE Table 14-6. CompactFlash Mode Selection Mode Base Address CFNOE CFNWE CFNIORD Attribute Memory I/O Mode (Write operations) NRD_NOE NWR0_NWE Common Memory I/O Mode (Read operations) NRD_NOE 14.6.5.4 Multiplexing of CompactFlash signals on EBI pins Table 14-7 on page 171...
Page 172 AT32UC3A3 Table 14-8. Shared CompactFlash Interface Multiplexing Access to CompactFlash Device Pins CompactFlash Signals CFNOE NWE0 CFNWE NWE1 CFNIORD CFRNW CFRNW 14.6.5.5 Application example Figure 14-4 on page 172 illustrates an example of a CompactFlash application. CFCS0 and CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc- tion and the output enable of the buffers between the EBI and the CompactFlash Device.
Page 173 AT32UC3A3 Figure 14-5. CompactFlash Application Example without I/O mode CompactFlash Connector D[15:0] DATA[15:0] CFRNW NCS[4] _CD1 _CD2 A[10:0] ADDR[10:0] _REG ADDR[22] NWE0 _IORD NWE1 _IOWR ADDR[21] CFCE1 _CE1 CFCE2 _CE2 NWAIT _WAIT 14.6.6 SmartMedia and NAND Flash Support The EBI integrates circuitry that interfaces to SmartMedia and NAND Flash devices. The NAND Flash logic is driven by the Static Memory Controller on the NCS[2] (and/or NCS[3]) address space.
Page 174 AT32UC3A3 Figure 14-6. NAND Flash Signal Multiplexing on EBI Pins NandFlash Logic NANDOE NCS[2]/[3] NANDWE NWR0_NWE 14.6.6.1 NAND Flash signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits ADDR[22] and ADDR[21] of the EBI address bus. The user should note that any bit on the EBI address bus can also be used for this purpose.
Page 175: Application Example
AT32UC3A3 14.7 Application Example 14.7.1 Hardware Interface Table 14-9. EBI Pins and External Static Devices Connections Pins of the Interfaced Device 2 x 8-bit 8-bit Static 16-bit Static Static Device Device Pins name Devices Controller DATA[7:0] D[7:0] D[7:0] D[7:0] DATA[15:0 –...
Page 176 AT32UC3A3 Table 14-10. EBI Pins and External Devices Connections (Continued) Pins of the Interfaced Device Smart Media Compact SDRAM Flash Pins name NAND Flash Controller SDRAMC ADDR[21] – – ADDR[22] – NCS[0] – – – NCS[1] SDCS[0] – – NCS[2] –...
Page 177 AT32UC3A3 14.7.2 Connection Examples Figure 14-8 on page 177shows an example of connections between the EBI and external devices. Figure 14-8. EBI Connections to Memory Devices DATA[15:0] SDRAM SDRAM SDCK 2Mx8 2Mx8 DATA[7:0] DATA[15:8] SDCKE D[7:0] D[7:0] SDWE ADDR[0] ADDR[11:2] ADDR[11:2] A[9:0] A[9:0]...
Page 178: Static Memory Controller (Smc)
AT32UC3A3 15. Static Memory Controller (SMC) Rev. 1.0.6.5 15.1 Features • 6 chip selects available • 16-Mbytes address space per chip select • 8- or 16-bit data bus • Word, halfword, byte transfers • Byte write or byte select lines •...
Page 179: Block Diagram
AT32UC3A3 15.3 Block Diagram Figure 15-1. SMC Block Diagram (AD_MSB=23) NCS[5:0] NCS[5:0] HMatrix Chip Select NWR0/NWE NWE0 A0/NBS0 ADDR[0] NWR1/NBS1 NWE1 A1/NWR2/NBS2 ADDR[1] Controller Mux Logic Power CLK_SMC Manager A[AD_MSB:2] ADDR[AD_MSB:2] D[15:0] DATA[15:0] NWAIT NWAIT User Interface Peripheral Bus 15.4 I/O Lines Description Table 15-1.
Page 180: Functional Description
AT32UC3A3 15.5.1 I/O Lines The SMC signals pass through the External Bus Interface (EBI) module where they are multi- plexed. The user must first configure the I/O Controller to assign the EBI pins corresponding to SMC signals to their peripheral function. If the I/O lines of the EBI corresponding to SMC signals are not used by the application, they can be used for other purposes by the I/O Controller.
Page 181 AT32UC3A3 Figure 15-3. Memory Connections for Six External Devices NCS[0] - NCS[5] NCS5 Memory Enable A[AD_MSB:0] NCS4 Memory Enable D[15:0] NCS3 Memory Enable NCS2 Memory Enable NCS1 Memory Enable NCS0 Memory Enable Output Enable Write Enable A[AD_MSB:0] 8 or 16 D[15:0] or D[7:0] 15.6.3 Connection to External Devices...
Page 182 AT32UC3A3 Figure 15-5. Memory Connection for a 16-bit Data Bus D[15:0] D[15:0] A[19:2] A[18:1] A[0] NBS0 Low Byte Enable NBS1 High Byte Enable Write Enable Output Enable NCS[2] Memory Enable •Byte write access The byte write access mode supports one byte write signal per byte of the data bus and a single read signal.
Page 183 AT32UC3A3 Figure 15-6. Connection of two 8-bit Devices on a 16-bit Bus: Byte Write Option D[7:0] D[7:0] D[15:8] A[24:2] A[23:1] A[0] NWR0 Write Enable NWR1 Read Enable NCS[3] Memory Enable D[15:8] A[23:1] A[0] Write Enable Read Enable Memory Enable •Signal multiplexing Depending on the MODE.BAT bit, only the write signals or the byte select signals are used.
Page 184 AT32UC3A3 access type. NWR0 to NWR1 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines. 15.6.4.1 Read waveforms The read cycle is shown on Figure 15-7 on page 184.
Page 185 AT32UC3A3 1. NCSRDSETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCSRDPULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge. 3. NCSRDHOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.
Page 186 AT32UC3A3 Figure 15-8. No Setup, No Hold on NRD, and NCS Read Signals CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 D[15:0] NRDSETUP NRDPULSE NRDPULSE NCSRDPULSE NCSRDPULSE NCSRDPULSE NRDCYCLE NRDCYCLE NRDCYCLE • Null Pulse Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads to unpredictable behavior.
Page 187 AT32UC3A3 Figure 15-9. READMODE = 1: Data Is Sampled by SMC Before the Rising Edge of NRD CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 PACC D[15:0] Data Sampling •Read is controlled by NCS (MODE.READMODE = 0) Figure 15-10 on page 188 shows the typical read cycle of an LCD module.
Page 188 AT32UC3A3 Figure 15-10. READMODE = 0: Data Is Sampled by SMC Before the Rising Edge of NCS CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 PACC D[15:0] Data Sampling 15.6.4.3 Write waveforms The write protocol is similar to the read protocol. It is depicted in Figure 15-11 on page 189.
Page 189 AT32UC3A3 Figure 15-11. Write Cycle CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NWEPULSE NWEHOLD NWESETUP NCSWRSETUP NCSWRPULSE NCSWRHOLD NWECYCLE •Write cycle The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change.
Page 190 AT32UC3A3 •Null delay setup and hold If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 15-12 on page 190). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.
Page 191 AT32UC3A3 Figure 15-13. WRITEMODE = 1. The Write Operation Is Controlled by NWE CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 D[15:0] •Write is controlled by NCS (MODE.WRITEMODE = 0) Figure 15-14 on page 191 shows the waveforms of a write operation with MODE.WRITEMODE written to zero.
Page 192 AT32UC3A3 15.6.4.6 Coding timing parameters All timing parameters are defined for one chip select and are grouped together in one register according to their type. The Setup register (SETUP) groups the definition of all setup parameters: • NRDSETUP, NCSRDSETUP, NWESETUP, and NCSWRSETUP. The Pulse register (PULSE) groups the definition of all pulse parameters: •...
Page 193 AT32UC3A3 15.6.5 Automatic Wait States Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict. 15.6.5.1 Chip select wait states The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the deactivation of one device and the activation of the next one.
Page 194 AT32UC3A3 An early read wait state is automatically inserted if at least one of the following conditions is valid: • if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 15-16 on page 194).
Page 195 AT32UC3A3 Figure 15-17. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No Setup. CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 No hold No setup D[15:0] Read cycle Write cycle Early Read (READMODE=0 or READMODE=1) (WRITEMODE=0) Wait State 32072H–AVR32–10/2012...
Page 196 AT32UC3A3 Figure 15-18. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle. CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 Internal write controlling signal external write controlling signal(NWE) No hold Read setup=1 D[15:0] Read cycle Write cycle Early Read (READMODE=0 or READMODE=1)
Page 197 AT32UC3A3 •Slow clock mode transition A reload configuration wait state is also inserted when the slow clock mode is entered or exited, after the end of the current transfer (see Section 15.6.8). 15.6.5.4 Read to write wait state Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses.
Page 198 AT32UC3A3 Figure 15-19. TDF Period in NRD Controlled Read Access (TDFCYCLES = 2) CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 PACC D[15:0] TDF = 2 clock cycles NRD controlled read operation Figure 15-20. TDF Period in NCS Controlled Read Operation (TDFCYCLES = 3) CLK_SMC A[AD_MSB:2] NBS0, NBS1,...
Page 199 AT32UC3A3 15.6.6.2 TDF optimization enabled (MODE.TDFMODE = 1) When the MODE.TDFMODE bit is written to one (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
Page 200 AT32UC3A3 • read access followed by a write access on the same chip select. with no TDF optimization. Figure 15-22. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Two Read Accesses on Dif- ferent Chip Selects. CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 Read1 controlling...
Page 201 AT32UC3A3 Figure 15-24. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Read and Write accesses on the Same Chip Select. CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 Read1 controlling signal(NRD) Write2 setup = 1 Read1 hold = 1 Write2 controlling TDFCYCLES = 5 signal(NWE) D[15:0]...
Page 202 AT32UC3A3 The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 15-26 on page 203. Figure 15-25. Write Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2). CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 FROZEN STATE D[15:0] NWAIT...
Page 203 AT32UC3A3 Figure 15-26. Read Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2). CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 FROZEN STATE NWAIT Internally synchronized NWAIT signal Read cycle EXNWMODE = 2 (Frozen) READMODE = 0 (NCS controlled) Assertion is ignored NRDPULSE = 2, NRDHOLD = 6 NCSRDPULSE = 5, NCSRDHOLD = 3 32072H–AVR32–10/2012...
Page 204 AT32UC3A3 15.6.7.3 Ready mode In Ready mode (MODE.EXNWMODE = 3), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 15-27 on page 204 Figure...
Page 205 AT32UC3A3 Figure 15-28. NWAIT Assertion in Read Access: Ready Mode (EXNWMODE = 3). CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 Wait STATE NWAIT Internally synchronized NWAIT signal Read cycle EXNWMODE = 3 (Ready mode) READMODE = 0 (NCS_controlled) Assertion is ignored Assertion is ignored NRDPULSE = 7 NCSRDPULSE = 7...
Page 206 AT32UC3A3 15.6.7.4 NWAIT latency and read/write timings There may be a latency between the assertion of the read/write controlling signal and the asser- tion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the two cycles of resynchronization plus one cycle.
Page 207 AT32UC3A3 15.6.8 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the SMC’s Power Management Controller is asserted because CLK_SMC has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied.
Page 208 AT32UC3A3 15.6.8.2 Switching from (to) slow clock mode to (from) normal mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters. See Figure 15-31 on page 208.
Page 209 AT32UC3A3 Figure 15-32. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode Internal signal from PM CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 SLOW CLOCK MODE WRITE IDLE STATE NORMAL MODE WRITE Reload Configuration Wait State...
Page 210 AT32UC3A3 Figure 15-33. Page Mode Read Protocol (Address MSB and LSB Are Defined in Table 15-6 on page 209) CLK_SMC A[MSB] A[LSB] D[15:0] NCSRDPULSE NRDPULSE NRDPULSE The NRD and NCS signals are held low during all read transfers, whatever the programmed val- ues of the setup and hold timings in the User Interface may be.
Page 211 AT32UC3A3 15.6.9.3 Page mode restriction The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may lead to unpredictable behavior. 15.6.9.4 Sequential and non-sequential accesses If the chip select and the MSB of addresses as defined in Table 15-6 on page 209 are identical, then the current access lies in the same page as the previous one, and no page break occurs.
Page 212: User Interface
AT32UC3A3 15.7 User Interface The SMC is programmed using the registers listed in Table 15-8 on page 212. For each chip select, a set of four registers is used to program the parameters of the external device connected on it. In Table 15-8 on page 212, “CS_number”...
Page 213 AT32UC3A3 15.7.1 Setup Register Register Name: SETUP Access Type: Read/Write Offset: 0x00 + CS_number*0x10 Reset Value: 0x01010101 – – NCSRDSETUP – – NRDSETUP – – NCSWRSETUP – – NWESETUP • NCSRDSETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: 128 NCSRDSETUP 5 [ ] ×...
Page 214 AT32UC3A3 15.7.2 Pulse Register Register Name: PULSE Access Type: Read/Write Offset: 0x04 + CS_number*0x10 Reset Value: 0x01010101 – NCSRDPULSE – NRDPULSE – NCSWRPULSE – NWEPULSE • NCSRDPULSE: NCS Pulse Length in READ Access In standard read access, the NCS signal pulse length is defined as: 256 NCSRDPULSE 6 [ ] ×...
Page 215 AT32UC3A3 15.7.3 Cycle Register Register Name: CYCLE Access Type: Read/Write Offset: 0x08 + CS_number*0x10 Reset Value: 0x00030003 – – – – – – – NRDCYCLE[8] NRDCYCLE[7:0] – – – – – – – NWECYCLE[8] NWECYCLE[7:0] • NRDCYCLE[8:0]: Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle.
Page 216 AT32UC3A3 15.7.4 Mode Register Register Name: MODE Access Type: Read/Write Offset: 0x0C + CS_number*0x10 Reset Value: 0x10002103 PMEN – – – – – TDFMODE TDFCYCLES – – – – – – – – EXNWMODE READMODE – – – – WRITEMODE •...
Page 217 AT32UC3A3 • DBW: Data Bus Width Data Bus Width 8-bit bus 16-bit bus Reserved Reserved • BAT: Byte Access Type This field is used only if DBW defines a 16-bit data bus. Byte Access Type Byte select access type: Write operation is controlled using NCS, NWE, NBS0, NBS1 Read operation is controlled using NCS, NRD, NBS0, NBS1 Byte write access type: Write operation is controlled using NCS, NWR0, NWR1...
Page 218 AT32UC3A3 • READMODE: Read Mode READMODE Read Access Mode The read operation is controlled by the NCS signal. If TDF are programmed, the external bus is marked busy after the rising edge of NCS. If TDF optimization is enabled (TDFMODE = 1), TDF wait states are inserted after the setup of NCS. The read operation is controlled by the NRD signal.
Page 219: Sdram Controller (Sdramc)
AT32UC3A3 16. SDRAM Controller (SDRAMC) Rev: 2.2.0.4 16.1 Features • 128-Mbytes address space • Numerous configurations supported – 2K, 4K, 8K row address memory parts – SDRAM with two or four internal banks – SDRAM with 16-bit data path • Programming facilities –...
Page 220: Block Diagram
AT32UC3A3 16.3 Block Diagram Figure 16-1. SDRAM Controller Block Diagram S D C K S D C K S D C K E S D R A M C S D C K E C h ip S elect S D C S N C S [1] M e m o ry C o ntro lle r...
Page 221: Application Example
AT32UC3A3 Table 16-1. I/O Lines Description Name Description Type Active Level DQM[1:0] Data Mask Enable Signals Output High SDRAMC_A[12:0] Address Bus Output D[15:0] Data Bus Input/Output 16.5 Application Example 16.5.1 Hardware Interface Figure 16-2 on page 221 shows an example of SDRAM device connection using a 16-bit data bus width.
Page 222: Product Dependencies
AT32UC3A3 16.5.2.1 16-bit memory data bus width Table 16-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line BA[1:0] Row[10:0] Column[7:0] BA[1:0] Row[10:0] Column[8:0] BA[1:0] Row[10:0] Column[9:0] BA[1:0] Row[10:0] Column[10:0] Table 16-3. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns CPU Address Line BA[1:0] Row[11:0]...
Page 223: Functional Description
AT32UC3A3 16.6.3 Clocks The clock for the SDRAMC bus interface (CLK_SDRAMC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the SDRAMC before disabling the clock, to avoid freezing the SDRAMC in an undefined state.
Page 224 AT32UC3A3 quency, the TR register must be written with the value 1562 (15.625 µs x 100 MHz) or 781 (7.81 µs x 100 MHz). After initialization, the SDRAM devices are fully functional. Figure 16-3. SDRAM Device Initialization Sequence SDCKE SDCK SDRAMC_A[9:0] SDRAMC_A[12:11] SDCS...
Page 225 AT32UC3A3 Figure 16-4. Write Burst, 16-bit SDRAM Access SDCS SDCK SDRAMC_A[12:0] Row n Col a Col f Col g Col k Col l Col b Col c Col d Col e Col h Col i Col j SDWE D[15:0] 16.7.3 SDRAM Controller Read Cycle The SDRAMC allows burst access, incremental burst of unspecified length or single access.
Page 226 AT32UC3A3 Figure 16-5. Read Burst, 16-bit SDRAM Access CAS = 2 SDCS SDCK SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f SDWE D[15:0] (Input) 16.7.4 Border Management When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAMC generates a precharge command, activates the new row and initiates a read or write command.
Page 227 AT32UC3A3 Figure 16-6. Read Burst with Boundary Row Access CAS = 2 SDCS SDCK Row n SDRAMC_A[12:0] Col a Col b Col c Col d Row m Col a Col b Col c Col d Col e SDWE D[15:0] 16.7.5 SDRAM Controller Refresh Cycles An auto refresh command is used to refresh the SDRAM device.
Page 228 AT32UC3A3 Figure 16-7. Refresh Cycle Followed by a Read Access CAS = 2 SDCS SDCK Row n Col a Col c Col d Row m SDRAMC_A[12:0] SDWE D[15:0] (input) 16.7.6 Power Management Three low power modes are available: • Self refresh mode: the SDRAM executes its own auto refresh cycles without control of the SDRAMC.
Page 229 AT32UC3A3 and Drive Strength (DS) parameters must be set by writing the corresponding fields in the LPR register, and transmitted to the low power SDRAM device during initialization. After initialization, as soon as the LPR.PASR, LPR.DS, or LPR.TCSR fields are modified and self refresh mode is activated, the SDRAMC issues an Extended Load Mode Register command to the SDRAM and the Extended Mode Register of the SDRAM device is accessed automati- cally.
Page 230 AT32UC3A3 Figure 16-9. Low Power Mode Behavior CAS = 2 Low Power Mode SDCS SDCK SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f SDCKE D[15:0] (input) 16.7.6.3 Deep power-down mode This mode is selected by writing the value three to the LPR.LPCB field. When this mode is acti- vated, all internal voltage generators inside the SDRAM are stopped and all data is lost.
Page 231 AT32UC3A3 Figure 16-10. Deep Power-down Mode Behavior SDCS SDCK Row n SDRAMC_A[12:0] Col c Col d SDWE SCKE D[15:0] (Input) 32072H–AVR32–10/2012...
Page 232: User Interface
AT32UC3A3 16.8 User Interface Table 16-5. SDRAMC Register Memory Map Offset Register Register Name Access Reset 0x00 Mode Register Read/Write 0x00000000 0x04 Refresh Timer Register Read/Write 0x00000000 0x08 Configuration Register Read/Write 0x852372C0 0x0C High Speed Register Read/Write 0x00000000 0x10 Low Power Register Read/Write 0x00000000 0x14...
Page 233 AT32UC3A3 16.8.1 Mode Register Register Name: Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 MODE • MODE: Command Mode This field defines the command issued by the SDRAMC when the SDRAM device is accessed. MODE Description Normal mode. Any access to the SDRAM is decoded normally. The SDRAMC issues a “NOP”...
Page 234 AT32UC3A3 16.8.2 Refresh Timer Register Register Name: Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 COUNT[11:8] COUNT[7:0] • COUNT[11:0]: Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated.
Page 235 AT32UC3A3 16.8.3 Configuration Register Register Name: Access Type: Read/Write Offset: 0x08 Reset Value: 0x852372C0 TXSR TRAS TRCD • TXSR: Exit Self Refresh to Active Delay Reset value is eight cycles. This field defines the delay between SCKE set high and an Activate command in number of cycles. Number of cycles is between 0 and 15.
Page 236 AT32UC3A3 • CAS: CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles is managed. CAS Latency (Cycles) Reserved • NB: Number of Banks Reset value is two banks. Number of Banks •...
Page 237 AT32UC3A3 16.8.4 High Speed Register Register Name: Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 • DA: Decode Cycle Enable A decode cycle can be added on the addresses as soon as a non-sequential access is performed on the HSB bus. The addition of the decode cycle allows the SDRAMC to gain time to access the SDRAM memory.
Page 238 AT32UC3A3 16.8.5 Low Power Register Register Name: Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 TIMEOUT TCSR PASR LPCB • TIMEOUT: Time to Define when Low Power Mode Is Enabled TIMEOUT Time to Define when Low Power Mode Is Enabled The SDRAMC activates the SDRAM low power mode immediately after the end of the last transfer.
Page 239 AT32UC3A3 • LPCB: Low Power Configuration Bits LPCB Low Power Configuration Low power feature is inhibited: no power-down, self refresh or deep power-down command is issued to the SDRAM device. The SDRAMC issues a self refresh command to the SDRAM device, the SDCLK clock is deactivated and the SDCKE signal is set low.
Page 240 AT32UC3A3 16.8.6 Interrupt Enable Register Register Name: Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 241 AT32UC3A3 16.8.7 Interrupt Disable Register Register Name: Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 242 AT32UC3A3 16.8.8 Interrupt Mask Register Register Name: Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one.
Page 243 AT32UC3A3 16.8.9 Interrupt Status Register Register Name: Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 • RES: Refresh Error Status This bit is set when a refresh error is detected. This bit is cleared when the register is read. 32072H–AVR32–10/2012...
Page 244 AT32UC3A3 16.8.10 Memory Device Register Register Name: Access Type: Read/Write Offset: 0x24 Reset Value: 0x00000000 • MD: Memory Device Type Device Type SDRAM Low power SDRAM Other Reserved 32072H–AVR32–10/2012...
Page 245 AT32UC3A3 16.8.11 Version Register Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: VARIANT VERSION VERSION • Variant: Variant Number Reserved. No functionality associated. • Version: Version Number Version number of the module.No functionality associated. 32072H–AVR32–10/2012...
Page 246: Error Corrected Code Controller (Ecchrs)
AT32UC3A3 17. Error Corrected Code Controller (ECCHRS) Rev. 1.0.0.0 17.1 Features • Hardware Error Corrected Code Generation with two methods : – Hamming code detection and correction by software (ECC-H) – Reed-Solomon code detection by hardware, correction by hardware or software (ECC-RS) ™...
Page 247: Block Diagram
AT32UC3A3 17.3 Block Diagram Figure 17-1. ECCHRS Block Diagram NAND Flash Rom 1024x10 Error Evaluator Encoder RS4 GF(2 ) SmartMedia Logic Polynomial Partial Syndrome Chien Search process ECC Controller Static Memory Ctrl/ECC 1bit Algorithm Controller User Interface HECC Peripheral Bus 17.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described...
Page 248: Functional Description
AT32UC3A3 17.5 Functional Description ™ A page in NAND Flash and SmartMedia memories contains an area for main data and an addi- tional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page size corresponds to the number of words in the main area plus the number of words in the extra area used for redundancy.
Page 249 AT32UC3A3 Figure 17-2. FREEZE signal waveform Spare Zone Nand Flash page 2048B 512B 512B 512B 512B FREEZE The application can check the ECC Status Registers (SR1/SR2) for any detected errors. It is up to the application to correct any detected error for ECC-H. The application can correct any detected error or let the hardware do the correction by writing a one to the Correction Enable bit in the MD register (MD.CORRS4) for ECC-RS.
Page 250 AT32UC3A3 Figure 17-3. Parity Generation for 512/1024/2048/4096 8-bit Words byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 byte Bit 7...
Page 251 AT32UC3A3 Figure 17-4. Parity Generation for 512/1024/2048/4096 16-bit Words byte Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 byte Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10...
Page 252 AT32UC3A3 For ECC-RS, in order to perform 4-error correction per 512 bytes of 8-bit words, the codeword have to be generated by the RS4 Encoder module and stored into the NAND Flash extra area, according to the scheme shown in Figure 17-5 on page 252 Figure 17-5.
Page 253 AT32UC3A3 Figure 17-7. Error Evaluator Block Diagram α α α α α ω ω ω ω ω ω ω (α ) Λ Rom 1024x10 odd( α ) Array - Mult Error value GF(2 ) inverted @ position j ErrorLoc The Chien Search takes charge of determining if an error has occurred at symbol N according to the scheme in Figure 17-8 on page 253 Figure 17-8.
Page 254: User Interface
AT32UC3A3 17.6 User Interface Table 17-1. ECCHRS Register Memory Map Offset Register Name Access Reset 0x000 Control Register CTRL Write-only 0x00000000 0x004 Mode Register Read/write 0x00000000 0x008 Status Register 1 Read-only 0x00000000 0x00C Parity Register 0 Read-only 0x00000000 0x010 Parity Register 1 Read-only 0x00000000 0x014...
Page 255 AT32UC3A3 17.6.1 Control Register Name: Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 • RST: RESET Parity Writing a one to this bit will reset the ECC Parity registers. Writing a zero to this bit has no effect. This bit always reads as zero. 32072H–AVR32–10/2012...
Page 256 AT32UC3A3 17.6.2 Mode Register Name: Access Type: Read/Write Offset: 0x004 Reset Value: 0x00000000 CORRS4 FREEZE TYPECORREC PAGESIZE • CORRS4: Correction Enable Writing a one to this bit will enable the correction to be done after the Partial Syndrome process and allow interrupt to be sent to CPU.
Page 257 AT32UC3A3 • PAGESIZE: Page Size This table defines the page size of the NAND Flash device when using the ECC-H code (TYPECORREC = 0b0xx). Page Size Description 528 words 1056 words 2112 words 4224 words Others Reserved ™ A word has a value of 8 bits or 16 bits, depending on the NAND Flash or SmartMedia memory organization.
Page 258 AT32UC3A3 17.6.3 Status Register 1 Name: Access Type: Read-only Offset: 0x008 Reset Value: 0x000000000 MD.TYPECORREC=0b0xx, using ECC-H code MULERR7 ECCERR7 RECERR7 MULERR6 ECCERR6 RECERR6 MULERR5 ECCERR5 RECERR5 MULERR4 ECCERR4 RECERR4 MULERR3 ECCERR3 RECERR3 MULERR2 ECCERR2 RECERR2 MULERR1 ECCERR1 RECERR1 MULERR0 ECCERR0 RECERR0 •...
Page 259 AT32UC3A3 • RECERRn: Recoverable Error in the packet number n of 256/512 Bytes in the page 1: Errors detected. If MULERRn is zero, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. 0: No errors have been detected. TYPECORREC sector size Comments...
Page 260 AT32UC3A3 Bit Index (n) Sector Boundaries 2560-3071 3072-3583 3584-4095 32072H–AVR32–10/2012...
Page 261 AT32UC3A3 17.6.4 Parity Register 0 Name: Access Type: Read-only Offset: 0x00C Reset Value: 0x00000000 Using ECC-H code, one bit correction per page (MD.TYPECORREC=0b000) WORDADDR[11:4] WORDADDR[3:0] BITADDR Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area.
Page 262 AT32UC3A3 NPARITY0[3:0] WORDADD0[7:5] WORDADD0[4:0] BITADDR0 Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area. • NPARITY0: Parity N Parity calculated by the ECC-H. •...
Page 263 AT32UC3A3 Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010) NPARITY0[11:4] NPARITY0[3:0] WORDADD0[8:5] WORDADD0[4:0] BITADDR0 Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area.
Page 264 AT32UC3A3 17.6.5 Parity Register 1 Name: Access Type: Read-only Offset: 0x010 Reset Value: 0x00000000 Using ECC-H code, one bit correction per page (MD.TYPECORREC=0b000) NPARITY[15:8] NPARITY[7:0] • NPARITY: Parity N During a write, the field of this register must be written in the extra area used for redundancy (for a 512-byte page size: address 514-515).
Page 265 AT32UC3A3 Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area. • NPARITY1: Parity N Parity alculated by the ECC-H. • WORDADDR1: corrupted Word Address in the page between the 256th and the 511th byte During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected.
Page 266 AT32UC3A3 17.6.6 Status Register 2 Name: Access Type: Read-only Offset: 0x014 Reset Value: 0x00000000 MD.TYPECORREC=0b0xx, using ECC-H code MULERR15 ECCERR15 RECERR15 MULERR14 ECCERR14 RECERR14 MULERR13 ECCERR13 RECERR13 MULERR12 ECCERR12 RECERR12 MULERR11 ECCERR11 RECERR11 MULERR10 ECCERR10 RECERR10 MULERR9 ECCERR9 RECERR9 MULERR8 ECCERR8 RECERR8 •...
Page 267 AT32UC3A3 MD.TYPECORREC=0b1xx, using ECC-RS code MULERR RECERR Only one sub page of 512 bytes is corrected at a time. If several sub page are on error then it is necessary to do several time the correction process. • MULERR: Multiple error This bit is set to one when a multiple error have been detected by the ECC-RS.
Page 268 AT32UC3A3 17.6.7 Parity Register 2 - 15 Name: PR2 - PR15 Access Type: Read-only Offset: 0x018 - 0x04C Reset Value: 0x00000000 Using ECC-H code, one bit correction per sector of 256 bytes (MD.TYPECORREC=0b001) NPARITYn[10:4] NPARITYn[3:0] WORDADDn[7:5] WORDADDn[4:0] BITADDRn Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area.
Page 269 AT32UC3A3 Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010) NPARITYn[11:4] NPARITYn[3:0] WORDADDn[8:5] WORDADDn[4:0] BITADDRn Once the entire main area of a page is written with data, this register content must be stored to any free location of the spare area.
Page 270 AT32UC3A3 17.6.8 Codeword 00 - Codeword79 Name: CWPS00 - CWPS79 Access Type: Read-only Offset: 0x050 - 0x18C Reset Value: 0x00000000 Page Write: CODEWORD • CODEWORD: Once the 512 bytes of a page is written with data, this register content must be stored to any free location of the spare area. For a page of 512 bytes the entire redundancy words are made of 8 words of 10 bits.
Page 271 AT32UC3A3 • PARSYND: At the end of a page read, this field contains the Partial Syndrome S. PARSYND00-PARSYND09: this conclude all the codeword and partial syndrome word for the sub page 1 PARSYND10-PARSYND19: this conclude all the codeword and partial syndrome word for the sub page 2 PARSYND20-PARSYND29: this conclude all the codeword and partial syndrome word for the sub page 3 PARSYND30-PARSYND39: this conclude all the codeword and partial syndrome word for the sub page 4 PARSYND40-PARSYND49: this conclude all the codeword and partial syndrome word for the sub page 5...
Page 272 AT32UC3A3 17.6.9 Mask Data 0 - Mask Data 3 Name: MDATA0 -MDATA3 Access Type: Read-only Offset: 0x190 - 0x19C Reset Value: 0x00000000 MASKDATA[9:8] MASKDATA[7:0] • MASKDATA: At the end of the correction process, this field contains the mask to be XORed with the data read to perform the final correction.This XORed is under the responsibility of the software.
Page 273 AT32UC3A3 17.6.10 Address Offset 0 - Address Offset 3 Name: ADOFF0 - ADOFF3 Access Type: Read-only Offset: 0x1A0 - 0x1AC Reset Value: 0x00000000 OFFSET[9:8] OFFSET[7:0] • OFFSET: At the end of correction process, this field contains the offset address of the data read to be corrected. This field is meaningless if MD.CORRS4 is zero.
Page 274 AT32UC3A3 17.6.11 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x1B0 Reset Value: 0x00000000 ENDCOR • ENDCOR: Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 275 AT32UC3A3 17.6.12 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x1B4 Reset Value: 0x00000000 ENDCOR • ENDCOR: Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 276 AT32UC3A3 17.6.13 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x1B8 Reset Value: 0x00000000 ENDCOR • ENDCOR: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one.
Page 277 AT32UC3A3 17.6.14 Interrupt Status Register Name: Access Type: Read-only Offset: 0x1BC Reset Value: 0x00000000 ENDCOR • ENDCOR: This bit is cleared when the corresponding bit in ISCR is written to one. This bit is set when a correction process has ended. 32072H–AVR32–10/2012...
Page 278 AT32UC3A3 17.6.15 Interrupt Status Clear Register Name: ISCR Access Type: Write-only Offset: 0x1C0 Reset Value: 0x00000000 ENDCOR • ENDCOR: Writing a zero to this bit has no effect Writing a one to this bit will clear the corresponding bit in ISR and the corresponding interrupt request. 32072H–AVR32–10/2012...
Page 279 AT32UC3A3 17.6.16 Version Register Name: VERSION Access Type: Read-only Offset: 0x1FC Reset Value: 0x00000000 VARIANT VERSION[11:8] VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32072H–AVR32–10/2012...
Page 280: Module Configuration
AT32UC3A3 17.7 Module Configuration The specific configuration for the ECCHRS instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 17-2. Module clock name Module name Clock name...
Page 281: Peripheral Dma Controller (Pdca)
AT32UC3A3 18. Peripheral DMA Controller (PDCA) Rev: 1.1.0.1 18.1 Features • Multiple channels • Generates transfers between memories and peripherals such as USART and SPI • Two address pointers/counters per channel allowing double buffering • Performance monitors to measure average and maximum transfer latency 18.2 Overview The Peripheral DMA Controller (PDCA) transfers data between on-chip peripheral modules such...
Page 282: Block Diagram
AT32UC3A3 18.3 Block Diagram Figure 18-1. PDCA Block Diagram Peripheral Memory HSB to PB Bridge Peripheral High Speed Bus Matrix Peripheral Peripheral DMA Controller (PDCA) Interrupt Peripheral Controller (n-1) Handshake Interfaces 18.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below.
Page 283: Functional Description
AT32UC3A3 18.5 Functional Description 18.5.1 Basic Operation The PDCA consists of multiple independent PDCA channels, each capable of handling DMA requests in parallel. Each PDCA channels contains a set of configuration registers which must be configured to start a DMA transfer. In this section the steps necessary to configure one PDCA channel is outlined.
Page 284 AT32UC3A3 18.5.5 Peripheral Selection The Peripheral Select Register (PSR) decides which peripheral should be connected to the PDCA channel. A peripheral is selected by writing the corresponding Peripheral Identity (PID) to the PID field in the PSR register. Writing the PID will both select the direction of the transfer (memory to peripheral or peripheral to memory), which handshake interface to use, and the address of the peripheral holding register.
Page 285: Performance Monitors
AT32UC3A3 bit in the Interrupt Status Register (ISR.TERR) will be set and the DMA channel that caused the error will be stopped. In order to restart the channel, the user must program the Memory Address Register to a valid address and then write a one to the Error Clear bit in the Control Register (CR.ECLR).
Page 286: User Interface
AT32UC3A3 18.7 User Interface 18.7.1 Memory Map Overview Table 18-1. PDCA Register Memory Map Address Range Contents 0x000 - 0x03F DMA channel 0 configuration registers 0x040 - 0x07F DMA channel 1 configuration registers (0x000 - 0x03F)+m*0x040 DMA channel m configuration registers 0x800-0x830 Performance Monitor registers 0x834...
Page 287 AT32UC3A3 18.7.3 Performance Monitor Memory Map Table 18-3. PDCA Performance Monitor Registers Offset Register Register Name Access Reset 0x800 Performance Control Register PCONTROL Read/Write 0x00000000 0x804 Channel0 Read Data Cycles PRDATA0 Read-only 0x00000000 0x808 Channel0 Read Stall Cycles PRSTALL0 Read-only 0x00000000 0x80C Channel0 Read Max Latency...
Page 288 AT32UC3A3 18.7.5 Memory Address Register Name: Access Type: Read/Write Offset: 0x000 + n*0x040 Reset Value: 0x00000000 MADDR[31:24] MADDR[23:16] MADDR[15:8] MADDR[7:0] • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the PDCA.
Page 289 AT32UC3A3 18.7.6 Peripheral Select Register Name: Access Type: Read/Write Offset: 0x004 + n*0x040 Reset Value: • PID: Peripheral Identifier The Peripheral Identifier selects which peripheral should be connected to the DMA channel. Writing a PID will select both which handshake interface to use, the direction of the transfer and also the address of the Receive/Transfer Holding Register for the peripheral.
Page 290 AT32UC3A3 18.7.7 Transfer Counter Register Name: Access Type: Read/Write Offset: 0x008 + n*0x040 Reset Value: 0x00000000 TCV[15:8] TCV[7:0] • TCV: Transfer Counter Value Number of data items to be transferred by the PDCA. TCV must be programmed with the total number of transfers to be made. During transfer, TCV contains the number of remaining transfers to be done.
Page 291 AT32UC3A3 18.7.8 Memory Address Reload Register Name: MARR Access Type: Read/Write Offset: 0x00C + n*0x040 Reset Value: 0x00000000 MARV[31:24] MARV[23:16] MARV[15:8] MARV[7:0] • MARV: Memory Address Reload Value Reload Value for the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a non- zero value.
Page 292 AT32UC3A3 18.7.9 Transfer Counter Reload Register Name: TCRR Access Type: Read/Write Offset: 0x010 + n*0x040 Reset Value: 0x00000000 TCRV[15:8] TCRV[7:0] • TCRV: Transfer Counter Reload Value Reload value for the TCR register. When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value. If TCRV is zero, no more transfers will be performed for the channel.
Page 293 AT32UC3A3 18.7.10 Control Register Name: Access Type: Write-only Offset: 0x014 + n*0x040 Reset Value: 0x00000000 ECLR TDIS • ECLR: Transfer Error Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Error bit in the Status Register (SR.TERR). Clearing the SR.TERR bit will allow the channel to transmit data.
Page 294 AT32UC3A3 18.7.11 Mode Register Name: Access Type: Read/Write Offset: 0x018 + n*0x040 Reset Value: 0x00000000 SIZE • SIZE: Size of Transfer Table 18-5. Size of Transfer SIZE Size of Transfer Byte Halfword Word Reserved 32072H–AVR32–10/2012...
Page 295 AT32UC3A3 18.7.12 Status Register Name: Access Type: Read-only Offset: 0x01C + n*0x040 Reset Value: 0x00000000 • TEN: Transfer Enabled This bit is cleared when the TDIS bit in CR is written to one. This bit is set when the TEN bit in CR is written to one. 0: Transfer is disabled for the DMA channel.
Page 296 AT32UC3A3 18.7.13 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x020 + n*0x040 Reset Value: 0x00000000 TERR Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 297 AT32UC3A3 18.7.14 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x024 + n*0x040 Reset Value: 0x00000000 TERR Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 298 AT32UC3A3 18.7.15 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x028 + n*0x040 Reset Value: 0x00000000 TERR 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one.
Page 299 AT32UC3A3 18.7.16 Interrupt Status Register Name: Access Type: Read-only Offset: 0x02C + n*0x040 Reset Value: 0x00000000 TERR • TERR: Transfer Error This bit is cleared when no transfer errors have occurred since the last write to CR.ECLR. This bit is set when one or more transfer errors has occurred since reset or the last write to CR.ECLR. •...
Page 300 AT32UC3A3 18.7.17 Performance Control Register Name: PCONTROL Access Type: Read/Write Offset: 0x800 Reset Value: 0x00000000 MON1CH MON0CH CH1RES CH0RES CH1OF CH0OF CH1EN CH0EN • MON1CH: Performance Monitor Channel 1 • MON0CH: Performance Monitor Channel 0 The PDCA channel number to monitor with counter n Due to performance monitor hardware resource sharing, the two performance monitor channels should NOT be programmed to monitor the same PDCA channel.
Page 301 AT32UC3A3 18.7.18 Performance Channel 0 Read Data Cycles Name: PRDATA0 Access Type: Read-only Offset: 0x804 Reset Value: 0x00000000 DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32072H–AVR32–10/2012...
Page 302 AT32UC3A3 18.7.19 Performance Channel 0 Read Stall Cycles Name: PRSTALL0 Access Type: Read-only Offset: 0x808 Reset Value: 0x00000000 STALL[31:24] STALL[23:16] STALL[15:8] STALL[7:0] • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32072H–AVR32–10/2012...
Page 303 AT32UC3A3 18.7.20 Performance Channel 0 Read Max Latency Name: PRLAT0 Access Type: Read/Write Offset: 0x80C Reset Value: 0x00000000 LAT[15:8] LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one. 32072H–AVR32–10/2012...
Page 304 AT32UC3A3 18.7.21 Performance Channel 0 Write Data Cycles Name: PWDATA0 Access Type: Read-only Offset: 0x810 Reset Value: 0x00000000 DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32072H–AVR32–10/2012...
Page 305 AT32UC3A3 18.7.22 Performance Channel 0 Write Stall Cycles Name: PWSTALL0 Access Type: Read-only Offset: 0x814 Reset Value: 0x00000000 STALL[31:24] STALL[23:16] STALL[15:8] STALL[7:0] • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32072H–AVR32–10/2012...
Page 306 AT32UC3A3 18.7.23 Performance Channel 0 Write Max Latency Name: PWLAT0 Access Type: Read/Write Offset: 0x818 Reset Value: 0x00000000 LAT[15:8] LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one. 32072H–AVR32–10/2012...
Page 307 AT32UC3A3 18.7.24 Performance Channel 1 Read Data Cycles Name: PRDATA1 Access Type: Read-only Offset: 0x81C Reset Value: 0x00000000 DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32072H–AVR32–10/2012...
Page 308 AT32UC3A3 18.7.25 Performance Channel 1 Read Stall Cycles Name: PRSTALL1 Access Type: Read-only Offset: 0x820 Reset Value: 0x00000000 STALL[31:24] STALL[23:16] STALL[15:8] STALL[7:0] • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32072H–AVR32–10/2012...
Page 309 AT32UC3A3 18.7.26 Performance Channel 1 Read Max Latency Name: PRLAT1 Access Type: Read/Write Offset: 0x824 Reset Value: 0x00000000 LAT[15:8] LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one. 32072H–AVR32–10/2012...
Page 310 AT32UC3A3 18.7.27 Performance Channel 1 Write Data Cycles Name: PWDATA1 Access Type: Read-only Offset: 0x828 Reset Value: 0x00000000 DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32072H–AVR32–10/2012...
Page 311 AT32UC3A3 18.7.28 Performance Channel 1 Write Stall Cycles Name: PWSTALL1 Access Type: Read-only Offset: 0x82C Reset Value: 0x00000000 STALL[31:24] STALL[23:16] STALL[15:8] STALL[7:0] • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 32072H–AVR32–10/2012...
Page 312 AT32UC3A3 18.7.29 Performance Channel 1 Write Max Latency Name: PWLAT1 Access Type: Read/Write Offset: 0x830 Reset Value: 0x00000000 LAT[15:8] LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one. 32072H–AVR32–10/2012...
Page 313 AT32UC3A3 18.7.30 PDCA Version Register Name: VERSION Access Type: Read-only Offset: 0x834 Reset Value: VARIANT VERSION[11:8] VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32072H–AVR32–10/2012...
Page 314: Module Configuration
AT32UC3A3 18.8 Module Configuration The specific configuration for the PDCA instance is listed in the following tables. Table 18-6. PDCA Configuration Features PDCA Number of channels Table 18-7. Register Reset Values Register Reset Value PSRn VERSION 0x00000110 18.8.1 DMA Handshake Signals The table below defines the valid Peripheral Identifiers (PIDs).
Page 315 AT32UC3A3 Table 18-8. PDCA Handshake Signals PID Value Direction Peripheral Instance Peripheral Register SPI0 SPI1 ABDAC 32072H–AVR32–10/2012...
Page 316: Dma Controller (Dmaca)
AT32UC3A3 19. DMA Controller (DMACA) Rev: 2.0.6.6 19.1 Features • 2 HSB Master Interfaces • 4 Channels • Software and Hardware Handshaking Interfaces – 8 Hardware Handshaking Interfaces • Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer • Single-block DMA Transfer • Multi-block DMA Transfer –...
Page 317: Block Diagram
AT32UC3A3 19.3 Block Diagram Figure 19-1. DMA Controller (DMACA) Block Diagram DMA Controller HSB Slave irq_dma HSB Slave Interrupt Generator Channel 1 Channel 0 FIFO HSB Master HSB Master 19.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below.
Page 318: Functional Description
AT32UC3A3 19.5 Functional Description 19.5.1 Basic Definitions Source peripheral: Device on a System Bus layer from where the DMACA reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMACA writes the stored data from the FIFO (pre- viously read from the source peripheral).
Page 319 AT32UC3A3 Transfer hierarchy: Figure 19-2 on page 319 illustrates the hierarchy between DMACA trans- fers, block transfers, transactions (single or burst), and System Bus transfers (single or burst) for non-memory peripherals. Figure 19-3 on page 319 shows the transfer hierarchy for memory. Figure 19-2.
Page 320 AT32UC3A3 – Single transaction: The length of a single transaction is always 1 and is converted to a single System Bus transfer. – Burst transaction: The length of a burst transaction is programmed into the DMACA. The burst transaction is converted into a sequence of System Bus bursts and single transfers.
Page 321 AT32UC3A3 Gather is enabled by writing a ‘1’ to the CTLx.SRC_GATHER_EN bit. The CTLx.SINC field determines if the address is incremented, decremented or remains fixed when a gather bound- ary is reached. If the CTLx.SINC field indicates a fixed-address control throughout a DMA transfer, then the CTLx.SRC_GATHER_EN bit is ignored and the gather feature is automatically disabled.
Page 322 AT32UC3A3 Figure 19-5. Source Gather Transfer System Memory Gather Boundary A0 + 0x38 Gather Increment = 4 A0 + 0x034 A0 + 0x030 Data Stream A0 + 0x02C d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 A0 + 0x028 A0 + 0x020 Gather Boundary A0 + 0x24...
Page 323: Arbitration For Hsb Master Interface
AT32UC3A3 19.6 Arbitration for HSB Master Interface Each DMACA channel has two request lines that request ownership of a particular master bus interface: channel source and channel destination request lines. Source and destination arbitrate separately for the bus. Once a source/destination state machine gains ownership of the master bus interface and the master bus interface has owner- ship of the HSB bus, then HSB transfers can proceed between the peripheral and the DMACA.
Page 324 AT32UC3A3 Software selects between the hardware or software handshaking interface on a per-channel basis. Software handshaking is accomplished through memory-mapped registers, while hard- ware handshaking is accomplished using a dedicated handshaking interface. 19.8.1 Software Handshaking When the slave peripheral requires the DMACA to perform a DMA transaction, it communicates this request by sending an interrupt to the CPU or interrupt controller.
Page 325: Dmaca Transfer Types
AT32UC3A3 19.8.2.1 External DMA Request Definition When an external slave peripheral requires the DMACA to perform DMA transactions, it commu- nicates its request by asserting the external nDMAREQx signal. This signal is resynchronized to ensure a proper functionality (see ”External DMA Request Timing” on page 325).
Page 326 AT32UC3A3 A block descriptor (LLI) consists of following registers, SARx, DARx, LLPx, CTL. These regis- ters, along with the CFGx register, are used by the DMACA to set up and describe the block transfer. 19.9.1 Multi-block Transfers 19.9.1.1 Block Chaining Using Linked Lists In this case, the DMACA re-programs the channel registers prior to the start of each block by fetching the block descriptor for that block from system memory.
Page 327 AT32UC3A3 Table 19-1. Programming of Transfer Types and Channel Register Update Method (DMACA State Machine Table) CTLx, RELOAD RELOAD_ LLP. LLPx LLP_S_EN LLP_D_EN SARx DARx Transfer Type Update Update Update Write CTLx) CFGx) CTLx) CFGx) Method Method Method Back 1) Single Block or None, user None last transfer of...
Page 328 AT32UC3A3 blocks is a function of CTLx.LLP_S_EN, CFGx.RELOAD_SR, CTLx.LLP_D_EN, and CFGx.RELOAD_DS registers (see Figure 19-1 on page 317). Note: Both SARx and DARx updates cannot be selected to be contiguous. If this functionality is required, the size of the Block Transfer (CTLx.BLOCK_TS) must be increased. If this is at the max- Table 19-1 on page 327 imum value, use Row 10 of and setup the LLI.SARx address of the...
Page 329: 19.10 Programming A Channel
AT32UC3A3 programmed to zero in the end of block interrupt service routine that services the next-to-last block transfer. This puts the DMACA into Row 1 state. For rows 6, 8, and 10 (both CFGx.RELOAD_SR and CFGx.RELOAD_DS cleared) the user must setup the last block descriptor in memory such that both LLI.CTLx.LLP_S_EN and LLI.CTLx.LLP_D_EN are zero.
Page 330 AT32UC3A3 – ii. Set up the transfer characteristics, such as: – Transfer width for the source in the SRC_TR_WIDTH field. – Transfer width for the destination in the DST_TR_WIDTH field. – Source master layer in the SMS field where source resides. –...
Page 331 AT32UC3A3 a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires pro- gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the hardware handshaking interface to handle source/destination requests for the specific channel.
Page 332 AT32UC3A3 Figure 19-8. Multi-Block with Linked List Address for Source and Destination Address of Address of Destination Layer Source Layer Block 2 Block 2 SAR(2) DAR(2) Block 1 Block 1 SAR(1) DAR(1) Block 0 Block 0 DAR(0) SAR(0) Source Blocks Destination Blocks If the user needs to execute a DMA transfer where the source and destination address are con- tiguous but the amount of data to be transferred is greater than the maximum block size...
Page 333 AT32UC3A3 Figure 19-9. Multi-Block with Linked Address for Source and Destination Blocks are Contiguous Address of Address of Source Layer Destination Layer Block 2 DAR(3) Block 2 Block 2 SAR(3) DAR(2) Block 2 Block 1 SAR(2) DAR(1) Block 1 Block 0 SAR(1) DAR(0) Block 0...
Page 334 AT32UC3A3 Figure 19-10. DMA Transfer Flow for Source and Destination Linked List Address Channel enabled by software LLI Fetch Hardware reprograms SARx, DARx, CTLx, LLPx DMAC block transfer Source/destination status fetch Block Complete interrupt generated here Is DMAC in Row1 of DMAC State Machine Table? DMAC transfer Complete interrupt generated here...
Page 335 AT32UC3A3 a. Write the starting source address in the SARx register for channel x. b. Write the starting destination address in the DARx register for channel x. c. Program CTLx and CFGx according to Row 4 as shown in Table 19-1 on page 327.
Page 336 AT32UC3A3 should clear the reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers. This put the DMACA into Row 1 as shown in Table 19-1 on page 327. If the next block is not the last block in the DMA transfer, then the reload bits should remain enabled to keep the DMACA in Row 4.
Page 337 AT32UC3A3 Figure 19-12. DMA Transfer Flow for Source and Destination Address Auto-reloaded Channel Enabled by software Block Transfer Reload SARx, DARx, CTLx Block Complete interrupt generated here DMAC transfer Complete interrupt generated here Is DMAC in Row1 of DMAC State Machine Table? Channel Disabled by hardware CTLx.INT_EN=1...
Page 338 AT32UC3A3 3. Write the starting source address in the SARx register for channel x. Note: The values in the LLI.SARx register locations of each of the Linked List Items (LLIs) setup up in memory, although fetched during a LLI fetch, are not used. 4.
Page 339 AT32UC3A3 block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block complete ISR (interrupt service routine) should clear the CFGx.RELOAD_SR source reload bit.
Page 340 AT32UC3A3 Figure 19-14. DMA Transfer Flow for Source Address Auto-reloaded and Linked List Destina- tion Address Channel Enabled by software LLI Fetch Hardware reprograms DARx, CTLx, LLPx DMAC block transfer Source/destination status fetch Reload SARx Block Complete interrupt generated here Is DMAC in Row1 or Row5 of DMAC Transfer Complete...
Page 341 AT32UC3A3 19.10.1.5 Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 3) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMA transfer by writing a ‘1’...
Page 342 AT32UC3A3 Reg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete. If the DMACA is not in Row 1, the next step is performed. 7. The DMA transfer proceeds as follows: a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un- masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed.
Page 343 AT32UC3A3 Figure 19-16. DMA Transfer for Source Address Auto-reloaded and Contiguous Destination Address Channel Enabled by software Block Transfer Reload SARx, CTLx Block Complete interrupt generated here DMAC Transfer Complete interrupt generated here Is DMAC in Row1 of DMAC State Machine Table? Channel Disabled by hardware CTLx.INT_EN=1...
Page 344 AT32UC3A3 – v. Incrementing/decrementing or fixed address for source in SINC field. – vi. Incrementing/decrementing or fixed address for destination DINC field. 3. Write the starting destination address in the DARx register for channel x. Note: The values in the LLI.DARx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used.
Page 345 AT32UC3A3 5 of Table 19-1 on page 327. The DMACA then knows that the previous block trans- ferred was the last block in the DMA transfer. The DMACA transfer might look like that shown in Figure 19-17 on page 345 Note that the des- tination address is decrementing.
Page 346: 19.11 Disabling A Channel Prior To Transfer Completion
AT32UC3A3 Figure 19-19. DMA Transfer Flow for Source Address Auto-reloaded and Contiguous Destination Address Channel Enabled by software LLI Fetch Hardware reprograms SARx, CTLx, LLPx DMAC block transfer Source/destination status fetch Block Complete interrupt generated here Is DMAC in Row 1 of Table 4 ? DMAC Transfer Complete interrupt generated here Channel Disabled by...
Page 347 AT32UC3A3 3. The ChEnReg.CH_EN bit can then be cleared by software once the channel FIFO is empty. When CTLx.SRC_TR_WIDTH is less than CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single word of CTLx.DST_TR_WIDTH to be formed.
Page 348: 19.12 User Interface
AT32UC3A3 19.12 User Interface Table 19-2. DMA Controller Memory Map Offset Register Register Name Access Reset Value 0x000 Channel 0 Source Address Register SAR0 Read/Write 0x00000000 0x008 Channel 0 Destination Address Register DAR0 Read/Write 0x00000000 0x010 Channel 0 Linked List Pointer Register LLP0 Read/Write 0x00000000...
Page 349 AT32UC3A3 Table 19-2. DMA Controller Memory Map (Continued) Offset Register Register Name Access Reset Value 0x158 Channel 3Destination Scatter Register DSR3 Read/Write 0x00000000 0x2C0 Raw Status for IntTfr Interrupt RawTfr Read-only 0x00000000 0x2C8 Raw Status for IntBlock Interrupt RawBlock Read-only 0x00000000 0x2D0 Raw Status for IntSrcTran Interrupt...
Page 350 AT32UC3A3 19.12.1 Channel x Source Address Register Name: SARx Access Type: Read/Write Offset: 0x000 + [x * 0x58] Reset Value: 0x00000000 SADD[31:24] SADD[23:16] SADD[15:8] SADD[7:0] • SADD: Source Address of DMA transfer The starting System Bus source address is programmed by software before the DMA channel is enabled or by a LLI update before the start of the DMA transfer.
Page 351 AT32UC3A3 19.12.2 Channel x Destination Address Register Name: DARx Access Type: Read/Write Offset: 0x008 + [x * 0x58] Reset Value: 0x00000000 DADD[31:24] DADD[23:16] DADD[15:8] DADD[7:0] • DADD: Destination Address of DMA transfer The starting System Bus destination address is programmed by software before the DMA channel is enabled or by a LLI update before the start of the DMA transfer.
Page 352 AT32UC3A3 19.12.3 Linked List Pointer Register for Channel x Name: LLPx Access Type: Read/Write Offset: 0x010 + [x * 0x58] Reset Value: 0x00000000 LOC[29:22] LOC[21:14] LOC[13:6] LOC[5:0] • LOC: Address of the next LLI Starting address in memory of next LLI if block chaining is enabled. The user need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is enabled.
Page 353 AT32UC3A3 19.12.4 Control Register for Channel x Low Name: CTLxL Access Type: Read/Write Offset: 0x018 + [x * 0x58] Reset Value: 0x00304801 LLP_SRC_E LLP_DST_E DMS[1] SRC_MSIZE DST_GATHE SRC_GATHE DMS[0] TT_FC R_EN R_EN SRC_MSIZE[1:0] DEST_MSIZE SINC DINC[1] DINC[0] SRC_TR_WIDTH DST_TR_WIDTH INT_EN This register contains fields that control the DMA transfer.
Page 354 AT32UC3A3 • DMS: Destination Master Select Identifies the Master Interface layer where the destination device (peripheral or memory) resides Table 19-5. Destination Master Select HSB Master HSB master 1 HSB master 2 Other Reserved • TT_FC: Transfer Type and Flow Control The four following transfer types are supported: •...
Page 355 AT32UC3A3 SRC_MSIZE Size (items number) Other Reserved • DST_MSIZE: Destination Burst Transaction Length Number of data items, each of width CTLx.DST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. DST_MSIZE Size (items number) Other...
Page 356 AT32UC3A3 • SRT_TR_WIDTH: Source Transfer Width • DSC_TR_WIDTH: Destination Transfer Width SRC_TR_WIDTH/DST_TR_WIDTH Size (bits) Other Reserved • INT_EN: Interrupt Enable Bit If set, then all five interrupt generating sources are enabled. 32072H–AVR32–10/2012...
Page 357 AT32UC3A3 19.12.5 Control Register for Channel x High Name: CTLxH Access Type: Read/Write Offset: 0x01C + [x * 0x58] Reset Value: 0x00000002 DONE BLOCK_TS[11:8] BLOCK_TS[7:0] • DONE: Done Bit Software can poll this bit to see when a block transfer is complete •...
Page 358 AT32UC3A3 19.12.6 Configuration Register for Channel x Low Name: CFGxL Access Type: Read/Write Offset: 0x040 + [x * 0x58] • Reset Value: 0x00000C00 + [x * 0x20] RELOAD_D RELOAD_S SRC_HS_P DST_HS_PO HS_SEL_SR HS_SEL_DS FIFO_EMPT CH_SUSP CH_PRIOR • RELOAD_DST: Automatic Destination Reload The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers.
Page 359 AT32UC3A3 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware Initiated transaction requests are ignored. If the destination peripheral is memory, then this bit is ignored. • FIFO_EMPTY Indicates if there is data left in the channel's FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel.
Page 360 AT32UC3A3 19.12.7 Configuration Register for Channel x High Name: CFGxH Access Type: Read/Write Offset: 0x044 + [x * 0x58] Reset Value: 0x00000004 DEST_PER SRC_PER[3:1] SRC_PER[0] PROTCTL FIFO_MODE FCMODE • DEST_PER: Destination Hardware Handshaking Interface Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the destination of channel x if the CFGx.HS_SEL_DST field is 0.
Page 361 AT32UC3A3 • FCMODE: Flow Control Mode Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are serviced when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs. In this mode the amount of data transferred from the source is limited such that it is guaranteed to be transferred to the destination prior to block termination by the destination.
Page 362 AT32UC3A3 19.12.8 Source Gather Register for Channel x Name: SGRx Access Type: Read/Write Offset: 0x048 + [x * 0x58] Reset Value: 0x00000000 SGC[11:4] SGC[3:0] SGI[19:16] SGI[15:8] SGI[7:0] • SGC: Source Gather Count Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH between successive gather intervals. This is defined as a gather boundary.
Page 363 AT32UC3A3 19.12.9 Destination Scatter Register for Channel x Name: DSRx Access Type: Read/Write Offset: 0x050 + [x * 0x58] Reset Value: 0x00000000 DSC[11:4] DSC[3:0] DSI[19:16] DSI[15:8] DSI[7:0] • DSC: Destination Scatter Count Specifies the number of contiguous destination transfers of CTLx.DST_TR_WIDTH between successive scatter boundaries.
Page 364 AT32UC3A3 19.12.10 Interrupt Registers The following sections describe the registers pertaining to interrupts, their status, and how to clear them. For each channel, there are five types of interrupt sources: • IntTfr: DMA Transfer Complete Interrupt This interrupt is generated on DMA transfer completion to the destination peripheral. •...
Page 365 AT32UC3A3 19.12.11 Interrupt Raw Status Registers Name: RawTfr, RawBlock, RawSrcTran, RawDstTran, RawErr Access Type: Read-only Offset: 0x2C0, 0x2C8, 0x2D0, 0x2D8, 0x2E0 Reset Value: 0x00000000 RAW3 RAW2 RAW1 RAW0 • RAW[3:0]Raw interrupt for each channel Interrupt events are stored in these Raw Interrupt Status Registers before masking: RawTfr, RawBlock, RawSrcTran, RawDstTran, RawErr.
Page 366 AT32UC3A3 19.12.12 Interrupt Status Registers Name: StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr Access Type: Read-only Offset: 0x2E8, 0x2F0, 0x2F8, 0x300, 0x308 Reset Value: 0x00000000 STATUS3 STATUS2 STATUS1 STATUS0 • STATUS[3:0] All interrupt events from all channels are stored in these Interrupt Status Registers after masking: StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr.
Page 367 AT32UC3A3 19.12.13 Interrupt Mask Registers Name: MaskTfr, MaskBlock, MaskSrcTran, MaskDstTran, MaskErr Access Type: Read/Write Offset: 0x310, 0x318, 0x320, 0x328, 0x330 Reset Value: 0x00000000 INT_M_WE3 INT_M_WE2 INT_M_WE1 INT_M_WE0 INT_MASK3 INT_MASK2 INT_MASK1 INT_MASK0 The contents of the Raw Status Registers are masked with the contents of the Mask Registers: MaskTfr, MaskBlock, Mask- SrcTran, MaskDstTran, MaskErr.
Page 368 AT32UC3A3 19.12.14 Interrupt Clear Registers Name: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr Access Type: Write-only Offset: 0x338, 0x340, 0x348, 0x350, 0x358 Reset Value: 0x00000000 CLEAR3 CLEAR2 CLEAR1 CLEAR0 • CLEAR[3:0]: Interrupt Clear 0 = No effect 1 = Clear interrupt Each bit in the Raw Status and Status registers is cleared on the same cycle by writing a 1 to the corresponding location in the Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr.
Page 369 AT32UC3A3 19.12.15 Combined Interrupt Status Registers Name: StatusInt Access Type: Read-only Offset: 0x360 Reset Value: 0x00000000 DSTT SRCT BLOCK The contents of each of the five Status Registers (StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr) is OR’ed to produce a single bit per interrupt type in the Combined Status Register (StatusInt). •...
Page 370 AT32UC3A3 19.12.16 Source Software Transaction Request Register Name: ReqSrcReg Access Type: Read/write Offset: 0x368 Reset Value: 0x00000000 REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0 SRC_REQ3 SRC_REQ2 SRC_REQ1 SRC_REQ0 A bit is assigned for each channel in this register. ReqSrcReg[n] is ignored when software handshaking is not enabled for the source of channel n.
Page 371 AT32UC3A3 19.12.17 Destination Software Transaction Request Register Name: ReqDstReg Access Type: Read/write Offset: 0x370 Reset Value: 0x00000000 REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0 DST_REQ3 DST_REQ2 DST_REQ1 DST_REQ0 A bit is assigned for each channel in this register. ReqDstReg[n] is ignored when software handshaking is not enabled for the source of channel n.
Page 372 AT32UC3A3 19.12.18 Single Source Transaction Request Register Name: SglReqSrcReg Access Type: Read/write Offset: 0x378 Reset Value: 0x00000000 REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0 S_SG_REQ3 S_SG_REQ2 S_SG_REQ1 S_SG_REQ0 A bit is assigned for each channel in this register. SglReqSrcReg[n] is ignored when software handshaking is not enabled for the source of channel n.
Page 373 AT32UC3A3 19.12.19 Single Destination Transaction Request Register Name: SglReqDstReg Access Type: Read/write Offset: 0x380 Reset Value: 0x0000000 REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0 D_SG_REQ3 D_SG_REQ2 D_SG_REQ1 D_SG_REQ0 A bit is assigned for each channel in this register. SglReqDstReg[n] is ignored when software handshaking is not enabled for the source of channel n.
Page 374 AT32UC3A3 19.12.20 Last Source Transaction Request Register Name: LstSrcReg Access Type: Read/write Offset: 0x388 Reset Value: 0x0000000 LSTSRC_W LSTSRC_W LSTSRC_W LSTSRC_W LSTSRC3 LSTSRC2 LSTSRC1 LSTSRC0 A bit is assigned for each channel in this register. LstSrcReg[n] is ignored when software handshaking is not enabled for the source of channel n.
Page 375 AT32UC3A3 19.12.21 Last Destination Transaction Request Register Name: LstDstReg Access Type: Read/write Offset: 0x390 Reset Value: 0x00000000 LSTDST_WE LSTDST_WE LSTDST_WE LSTDST_WE LSTDST3 LSTDST2 LSTDST1 LSTDST0 A bit is assigned for each channel in this register. LstDstReg[n] is ignored when software handshaking is not enabled for the source of channel n.
Page 376 AT32UC3A3 19.12.22 DMA Configuration Register Name: DmaCfgReg Access Type: Read/Write Offset: 0x398 Reset Value: 0x00000000 DMA_EN • DMA_EN: DMA Controller Enable 0 = DMACA Disabled 1 = DMACA Enabled. This register is used to enable the DMACA, which must be done before any channel activity can begin. If the global channel enable bit is cleared while any channel is still active, then DmaCfgReg.DMA_EN still returns ‘1’...
Page 377 AT32UC3A3 19.12.23 DMA Channel Enable Register Name: ChEnReg Access Type: Read/Write Offset: 0x3A0 Reset Value: 0x00000000 CH_EN_WE CH_EN_WE CH_EN_WE CH_EN_WE CH_EN3 CH_EN2 CH_EN1 CH_EN0 • CH_EN_WE[11:8]: Channel Enable Write Enable The channel enable bit, CH_EN, is only written if the corresponding channel write enable bit, CH_EN_WE, is asserted on the same System Bus write transfer.
Page 378 AT32UC3A3 19.12.24 DMACA Component Id Register Low Name: DmaCompIdRegL Access Type: Read-only Offset: 0x3F8 Reset Value: 0x44571110 DMA_COMP_TYPE[31:24] DMA_COMP_TYPE[23:16] DMA_COMP_TYPE[15:8] DMA_COMP_TYPE[7:0] • DMA_COMP_TYPE DesignWare component type number = 0x44571110. This assigned unique hex value is constant and is derived from the two ASCII letters “DW” followed by a 32-bit unsigned number 32072H–AVR32–10/2012...
Page 379 AT32UC3A3 19.12.25 DMACA Component Id Register High Name: DmaCompIdRegH Access Type: Read-only Offset: 0x3FC Reset Value: 0x3230362A DMA_COMP_VERSION[31:24] DMA_COMP_VERSION[23:16] DMA_COMP_VERSION[15:8] DMA_COMP_VERSION[7:0] • DMA_COMP_VERSION: Version of the component 32072H–AVR32–10/2012...
Page 380: Module Configuration
AT32UC3A3 19.13 Module Configuration The following table defines the valid settings for the DEST_PER and SRC_PER fields in the CFGxH register. The direction is specified as observed from the DMACA. So for instance, AES - RX means this hardware handshaking interface is connected to the input of the AES modulel Table 19-6.
Page 381: General-Purpose Input/Output Controller (Gpio)
AT32UC3A3 20. General-Purpose Input/Output Controller (GPIO) Rev: 1.1.0.4 20.1 Features Each I/O line of the GPIO features: • Configurable pin-change, rising-edge or falling-edge interrupt on any I/O line • A glitch filter providing rejection of pulses shorter than one clock cycle •...
Page 382: Functional Description
AT32UC3A3 20.4.1 Module Configuration Most of the features of the GPIO are configurable for each product. The user must refer to the Package and Pinout chapter for these settings. Product specific settings includes: • Number of I/O pins. • Functions implemented on each pin •...
Page 383 AT32UC3A3 Figure 20-2. Overview of the GPIO Pad Connections ODER PUER Periph. A output enable Periph. B output enable Periph. C output enable Periph. D output enable PMR1 GPER PMR0 Periph. A output data Periph. B output data Periph. C output data Periph.
Page 384 AT32UC3A3 responding I/O line is driven by the GPIO. When the bit is written to zero, the GPIO does not drive the line. The level driven on an I/O line can be determined by writing to the Output Value Register (OVR). 20.5.1.4 Inputs The level on each I/O line can be read through the Pin Value Register (PVR).
Page 385 AT32UC3A3 20.5.3 Interrupts The GPIO can be configured to generate an interrupt when it detects an input change on an I/O line. The module can be configured to signal an interrupt whenever a pin changes value or only to trigger on rising edges or falling edges. Interrupts are enabled on a pin by writing a one to the corresponding bit in the Interrupt Enable Register (IER).
Page 386: User Interface
AT32UC3A3 20.6 User Interface The GPIO controls all the I/O pins on the AVR32 microcontroller. The pins are managed as 32- bit ports that are configurable through a PB interface. Each port has a set of configuration regis- ters. The overall memory map of the GPIO is shown below. The number of pins and hence the number of ports are product specific.
Page 387 AT32UC3A3 register offset and the port offset to the GPIO start address. One bit in each of the configuration registers corresponds to an I/O pin. Table 20-1. GPIO Register Memory Map Offset Register Function Name Access Reset value 0x00 GPIO Enable Register Read/Write GPER Read/Write...
Page 388 AT32UC3A3 Table 20-1. GPIO Register Memory Map Offset Register Function Name Access Reset value 0xB4 Interrupt Mode Register 1 IMR1S Write-Only 0xB8 Interrupt Mode Register 1 Clear IMR1C Write-Only 0xBC Interrupt Mode Register 1 Toggle IMR1T Write-Only 0xC0 Glitch Filter Enable Register Read/Write GFER Read/Write...
Page 389 AT32UC3A3 20.6.2 Enable Register Name: GPER Access Type: Read, Write, Set, Clear, Toggle Offset: 0x00, 0x04, 0x08, 0x0C Reset Value: • P0-P31: Pin Enable 0: A peripheral function controls the corresponding pin. 1: The GPIO controls the corresponding pin. 32072H–AVR32–10/2012...
Page 390 AT32UC3A3 20.6.3 Peripheral Mux Register 0 Name: PMR0 Access Type: Read, Write, Set, Clear, Toggle Offset: 0x10, 0x14, 0x18, 0x1C Reset Value: • P0-31: Peripheral Multiplexer Select bit 0 32072H–AVR32–10/2012...
Page 391 AT32UC3A3 20.6.4 Peripheral Mux Register 1 Name: PMR1 Access Type: Read, Write, Set, Clear, Toggle Offset: 0x20, 0x24, 0x28, 0x2C Reset Value: • P0-31: Peripheral Multiplexer Select bit 1 {PMR1, PMR0} Selected Peripheral Function 32072H–AVR32–10/2012...
Page 392 AT32UC3A3 20.6.5 Output Driver Enable Register Name: ODER Access Type: Read, Write, Set, Clear, Toggle Offset: 0x40, 0x44, 0x48, 0x4C Reset Value: • P0-31: Output Driver Enable 0: The output driver is disabled for the corresponding pin. 1: The output driver is enabled for the corresponding pin. 32072H–AVR32–10/2012...
Page 393 AT32UC3A3 20.6.6 Output Value Register Name: Access Type: Read, Write, Set, Clear, Toggle Offset: 0x50, 0x54, 0x58, 0x5C Reset Value: • P0-31: Output Value 0: The value to be driven on the I/O line is 0. 1: The value to be driven on the I/O line is 1. 32072H–AVR32–10/2012...
Page 394 AT32UC3A3 20.6.7 Pin Value Register Name: Access Type: Read Offset: 0x60, 0x64, 0x68, 0x6C Reset Value: • P0-31: Pin Value 0: The I/O line is at level ‘0’. 1: The I/O line is at level ‘1’. Note that the level of a pin can only be read when GPER is set or interrupt is enabled for the pin. 32072H–AVR32–10/2012...
Page 395 AT32UC3A3 20.6.8 Pull-up Enable Register Name: PUER Access Type: Read, Write, Set, Clear, Toggle Offset: 0x70, 0x74, 0x78, 0x7C Reset Value: • P0-31: Pull-up Enable 0: The internal pull-up resistor is disabled for the corresponding pin. 1: The internal pull-up resistor is enabled for the corresponding pin. 32072H–AVR32–10/2012...
Page 396 AT32UC3A3 20.6.9 Interrupt Enable Register Name: Access Type: Read, Write, Set, Clear, Toggle Offset: 0x90, 0x94, 0x98, 0x9C Reset Value: • P0-31: Interrupt Enable 0: Interrupt is disabled for the corresponding pin. 1: Interrupt is enabled for the corresponding pin. 32072H–AVR32–10/2012...
Page 397 AT32UC3A3 20.6.10 Interrupt Mode Register 0 Name: IMR0 Access Type: Read, Write, Set, Clear, Toggle Offset: 0xA0, 0xA4, 0xA8, 0xAC Reset Value: • P0-31: Interrupt Mode Bit 0 32072H–AVR32–10/2012...
Page 398 AT32UC3A3 20.6.11 Interrupt Mode Register 1 Name: IMR1 Access Type: Read, Write, Set, Clear, Toggle Offset: 0xB0, 0xB4, 0xB8, 0xBC Reset Value: • P0-31: Interrupt Mode Bit 1 {IMR1, IMR0} Interrupt Mode Pin Change Rising Edge Falling Edge Reserved 32072H–AVR32–10/2012...
Page 399 AT32UC3A3 20.6.12 Glitch Filter Enable Register Name: GFER Access Type: Read, Write, Set, Clear, Toggle Offset: 0xC0, 0xC4, 0xC8, 0xCC Reset Value: • P0-31: Glitch Filter Enable 0: Glitch filter is disabled for the corresponding pin. 1: Glitch filter is enabled for the corresponding pin. NOTE! The value of this register should only be changed when IER is ‘0’.
Page 400 AT32UC3A3 20.6.13 Interrupt Flag Register Name: Access Type: Read, Clear Offset: 0xD0, 0xD8 Reset Value: • P0-31: Interrupt Flag 1: An interrupt condition has been detected on the corresponding pin. 0: No interrupt condition has beedn detected on the corresponding pin since reset or the last time it was cleared. The number of interrupt request lines is dependant on the number of I/O pins on the MCU.
Page 401: Programming Examples
AT32UC3A3 20.7 Programming Examples 20.7.1 8-bit LED-Chaser // Set R0 to GPIO base address R0, LO(AVR32_GPIO_ADDRESS) R0, HI(AVR32_GPIO_ADDRESS) // Enable GPIO control of pin 0-8 R1, 0xFF st.w R0[AVR32_GPIO_GPERS], R1 // Set initial value of port R2, 0x01 st.w R0[AVR32_GPIO_OVRS], R2 // Set up toggle value.
Page 402 AT32UC3A3 R1, 0x0000 R1, 0x0003 st.w R0[AVR32_GPIO_ODERC], R1 // Make the GPIO control the pins st.w R0[AVR32_GPIO_GPERS], R1 // Select peripheral B on PC16-PC17 st.w R0[AVR32_GPIO_PMR0S], R1 st.w R0[AVR32_GPIO_PMR1C], R1 // Enable peripheral control st.w R0[AVR32_GPIO_GPERC], R1 32072H–AVR32–10/2012...
Page 403: Module Configuration
AT32UC3A3 20.8 Module configuration The specific configuration for each GPIO instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Sys- tem Bus Clock Connections section. Table 20-2.
Page 404: Serial Peripheral Interface (Spi)
AT32UC3A3 21. Serial Peripheral Interface (SPI) Rev: 2.1.0.3 21.1 Features • Compatible with an embedded 32-bit microcontroller • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs –...
Page 405: Block Diagram
AT32UC3A3 21.3 Block Diagram Figure 21-1. SPI Block Diagram Peripheral DMA Controller Peripheral Bus SPCK MISO CLK_SPI MOSI Spi Interface NPCS0/NSS Controller NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 21.4 Application Block Diagram Figure 21-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPCK SPCK MISO...
Page 406: I/O Lines Description
AT32UC3A3 21.5 I/O Lines Description Table 21-1. I/O Lines Description Type Pin Name Pin Description Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS...
Page 407 AT32UC3A3 21.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two bits determine the edges of the clock signal on which data is driven and sampled.
Page 408 AT32UC3A3 Figure 21-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) (to slave) *** Not Defined, but normaly LSB of previous character transmitted 21.7.3 Master Mode Operations When configured in master mode, the SPI uses the internal programmable baud rate generator...
Page 409 AT32UC3A3 In master mode, if the received data is not read fast enough compared to the transfer rhythm imposed by the write accesses in the TDR, some overrun errors may occur, even if the FIFO is enabled. To insure a perfect data integrity of received data (especially at high data rate), the mode Wait Data Read Before Transfer can be enabled in the MR register (MR.WDRBT).
Page 410 AT32UC3A3 21.7.3.2 Master mode flow diagram Figure 21-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
Page 411 AT32UC3A3 21.7.3.3 Clock generation The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255. This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud rate of CLK_SPI divided by 255. Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbid- den.
Page 412 AT32UC3A3 21.7.3.5 Peripheral selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: •...
Page 413 AT32UC3A3 to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip Select Active After Transfer bit written to one (CSRn.CSAAT) .
Page 414 AT32UC3A3 Figure 21-8. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 CSAAT = 1 and CSNAAT= 0 / 1 TDRE DLYBCT DLYBCT NPCS[0..3] DLYBCS DLYBCS PCS = A PCS = A Write TDR TDRE DLYBCT DLYBCT NPCS[0..3] DLYBCS DLYBCS PCS=A PCS = A Write TDR...
Page 415 AT32UC3A3 register (MR.MODFDIS). In systems with open-drain I/O lines, a mode fault is detected when a low level is driven by an external master on the NPCS0/NSS signal. When a mode fault is detected, the Mode Fault Error bit in the SR (SR.MODF) is set until the SR is read and the SPI is automatically disabled until re-enabled by writing a one to the SPI Enable bit in the CR register (CR.SPIEN).
Page 416 AT32UC3A3 Figure 21-9. Slave Mode Functional Block Diagram SPCK Clock SPIEN RXFIFOEN SPIENS RDRF SPIDIS OVRES CSR0 BITS NCPHA 4 - Character FIFO CPOL Shift Register MISO MOSI UNDES TDRE 32072H–AVR32–10/2012...
Page 417: User Interface
AT32UC3A3 21.8 User Interface Table 21-3. SPI Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register Write-only 0x00000000 0x04 Mode Register Read/Write 0x00000000 0x08 Receive Data Register Read-only 0x00000000 0x0C Transmit Data Register Write-only 0x00000000 0x10 Status Register Read-only 0x00000000 0x14...
Page 418 AT32UC3A3 21.8.1 Control Register Name: Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 LASTXFER FLUSHFIFO SWRST SPIDIS SPIEN • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.
Page 419 AT32UC3A3 21.8.2 Mode Register Name: Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 DLYBCS RXFIFOEN WDRBT- MODFDIS PCSDEC MSTR • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non- overlapping chip selects and solves bus contentions in case of peripherals having long data float times.
Page 420 AT32UC3A3 0: The FIFO is not used in reception (only one character can be stored in the SPI). • WDRBT: Wait Data Read Before Transfer 1: In master mode, a transfer can start only if the RDR register is empty, i.e. does not contain any unread data. This mode prevents overrun error in reception.
Page 421 AT32UC3A3 21.8.3 Receive Data Register Name: Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 RD[15:8] RD[7:0] • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. 32072H–AVR32–10/2012...
Page 422 AT32UC3A3 21.8.4 Transmit Data Register Name: Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 LASTXFER TD[15:8] TD[7:0] • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.
Page 423 AT32UC3A3 21.8.5 Status Register Name: Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 SPIENS UNDES TXEMPTY NSSR OVRES MODF TDRE RDRF • SPIENS: SPI Enable Status 1: This bit is set when the SPI is enabled. 0: This bit is cleared when the SPI is disabled. •...
Page 424 AT32UC3A3 21.8.6 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 UNDES TXEMPTY NSSR OVRES MODF TDRE RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 425 AT32UC3A3 21.8.7 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 UNDES TXEMPTY NSSR OVRES MODF TDRE RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 426 AT32UC3A3 21.8.8 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 UNDES TXEMPTY NSSR OVRES MODF TDRE RDRF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one.
Page 427 AT32UC3A3 21.8.9 Chip Select Register 0 Name: CSR0 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 DLYBCT DLYBS SCBR BITS CSAAT CSNAAT NCPHA CPOL • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.
Page 428 AT32UC3A3 • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Reserved 1110 Reserved...
Page 429 AT32UC3A3 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 32072H–AVR32–10/2012...
Page 430 AT32UC3A3 21.8.10 Chip Select Register 1 Name: CSR1 Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 DLYBCT DLYBS SCBR BITS CSAAT CSNAAT NCPHA CPOL • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.
Page 431 AT32UC3A3 • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Reserved 1110 Reserved...
Page 432 AT32UC3A3 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 32072H–AVR32–10/2012...
Page 433 AT32UC3A3 21.8.11 Chip Select Register 2 Name: CSR2 Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 DLYBCT DLYBS SCBR BITS CSAAT CSNAAT NCPHA CPOL • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.
Page 434 AT32UC3A3 • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Reserved 1110 Reserved...
Page 435 AT32UC3A3 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 32072H–AVR32–10/2012...
Page 436 AT32UC3A3 21.8.12 Chip Select Register 3 Name: CSR3 Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 DLYBCT DLYBS SCBR BITS CSAAT CSNAAT NCPHA CPOL • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.
Page 437 AT32UC3A3 • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Reserved 1110 Reserved...
Page 438 AT32UC3A3 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 32072H–AVR32–10/2012...
Page 439 AT32UC3A3 21.8.13 Write Protection Control Register Register Name: WPCR Access Type: Read-write Offset: 0xE4 Reset Value: 0x00000000 SPIWPKEY[23:16] SPIWPKEY[15:8] SPIWPKEY[7:0] SPIWPEN • SPIWPKEY: SPI Write Protection Key Password If a value is written in SPIWPEN, the value is taken into account only if SPIWPKEY is written with “SPI” (SPI written in ASCII Code, i.e.
Page 440 AT32UC3A3 21.8.14 Write Protection Status Register Register Name: WPSR Access Type: Read-only Offset: 0xE8 Reset Value: 0x00000000 SPIWPVSRC SPIWPVS • SPIWPVSRC: SPI Write Protection Violation Source This Field indicates the Peripheral Bus Offset of the register concerned by the violation (MR or CSRx) 32072H–AVR32–10/2012...
Page 441 AT32UC3A3 • SPIWPVS: SPI Write Protection Violation Status SPIWPVS value Violation Type The Write Protection has blocked a Write access to a protected register (since the last read). Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on MR, IER, IDR or CSRx).
Page 442 AT32UC3A3 21.8.15 Version Register Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: – VERSION[11:8] VERSION[7:0] • Reserved. No functionality associated. • VERSION Version number of the module. No functionality associated. 32072H–AVR32–10/2012...
Page 443: Module Configuration
AT32UC3A3 21.9 Module Configuration The specific configuration for each SPI instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager section for details. Table 21-4. Module Clock Name Module Name Clock Name...
Page 444: Two-Wire Slave Interface (Twis)
400 kbit/s, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus, I²C, or SMBus-compatible master. The TWIS is always a bus slave and can transfer sequential or sin- gle bytes.
Page 445: List Of Abbreviations
AT32UC3A3 Below, Table 22-2 lists the compatibility level of the Atmel Two-wire Slave Interface and a full SMBus compatible device. Table 22-2. Atmel TWIS Compatibility with SMBus Standard SMBus Standard Atmel TWIS Bus Timeouts Supported Address Resolution Protocol Supported Alert...
Page 446: Application Block Diagram
AT32UC3A3 22.5 Application Block Diagram Figure 22-2. Application Block Diagram Host with TWCK Interface Atmel TWI I²C LCD I²C temp. I²C RTC serial EEPROM controller sensor Slave 1 Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 22.6...
Page 447: Functional Description
AT32UC3A3 22.7.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TWIS, the TWIS will stop func- tioning and resume operation after the system wakes up from sleep mode. 22.7.3 Clocks The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager.
Page 448 These modes are described in the following chapters. Figure 22-5. Typical Application Block Diagram Host with TWCK Interface Atmel TWI I²C LCD I²C Temp. I²C RTC Serial EEPROM Controller Sensor...
Page 449 AT32UC3A3 TTOUT: Prescaled clock cycles used to time SMBUS timeout T TIMEOUT SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time T SU_DAT EXP: Specifies the clock prescaler setting used for the SMBUS timeouts. Figure 22-6. Bus Timing Diagram t HIGH t LOW t LOW...
Page 450 AT32UC3A3 In I²C mode: • The address in CR.ADR is checked for address match if CR.SMATCH is one. • The General Call address is checked for address match if CR.GCMATCH is one. In SMBus mode: • The address in CR.ADR is checked for address match if CR.SMATCH is one. •...
Page 451 AT32UC3A3 4. NBYTES is updated. If CR.CUP is one, NBYTES is incremented, otherwise NBYTES is decremented. 5. After each data byte has been transmitted, the master transmits an ACK (Acknowledge) or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the SR.NAK bit is set.
Page 452 AT32UC3A3 Figure 22-8. Slave Transmitter with Multiple Data Bytes DADR DATA n DATA n+5 DATA n+m TCOMP TXRDY STOP sent by master Write THR (Data n) Write THR (Data n+1) Write THR (Data n+m) NBYTES set to m Last data sent Figure 22-9.
Page 453 AT32UC3A3 slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse. The SR.RXRDY bit indicates that a data byte is available in the RHR. The RXRDY bit is also used as Receive Ready for the Peripheral DMA Controller receive channel.
Page 454 AT32UC3A3 3. Start the transfer by enabling the Peripheral DMA Controller to receive. 4. Wait for the Peripheral DMA Controller end-of-receive flag. 5. Disable the Peripheral DMA Controller. 22.8.6 SMBus Mode SMBus mode is enabled by writing a one to the SMBus Mode Enable (SMEN) bit in CR. SMBus mode operation is similar to I²C operation with the following exceptions: •...
Page 455 AT32UC3A3 22.8.7 Identifying Bus Events This chapter lists the different bus events, and how these affects the bits in the TWIS registers. This is intended to help writing drivers for the TWIS. Table 22-5. Bus Events Event Effect SR.THR is cleared. Slave transmitter has sent a SR.BTF is set.
Page 456 AT32UC3A3 Table 22-5. Bus Events Event Effect Data is to be received in TWCK is not stretched, read data is discarded. slave receiver mode, SR.STREN is cleared, and SR.ORUN is set. RHR is full Data is to be transmitted in TWCK is not stretched, previous contents of THR is written to bus.
Page 457: User Interface
AT32UC3A3 22.9 User Interface Table 22-6. TWIS Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register Read/Write 0x00000000 0x04 NBYTES Register NBYTES Read/Write 0x00000000 0x08 Timing Register Read/Write 0x00000000 0x0C Receive Holding Register Read-only 0x00000000 0x10 Transmit Holding Register Write-only 0x00000000 0x14...
Page 458 AT32UC3A3 22.9.1 Control Register Name: Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 TENBIT ADR[9:8] ADR[7:0] SOAM PECEN SMHH SMDA SMBALERT SWRST STREN GCMATCH SMATCH SMEN • TENBIT: Ten Bit Address Match 0: Disables Ten Bit Address Match. 1: Enables Ten Bit Address Match. •...
Page 459 AT32UC3A3 Writing a one to this bit resets the TWIS. • STREN: Clock Stretch Enable 0: Disables clock stretching if RHR/THR buffer full/empty. May cause over/underrun. 1: Enables clock stretching if RHR/THR buffer full/empty. • GCMATCH: General Call Address Match 0: Causes the TWIS not to acknowledge the General Call Address.
Page 460 AT32UC3A3 22.9.2 NBYTES Register Name: NBYTES Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 NBYTES • NBYTES: Number of Bytes to Transfer Writing to this field updates the NBYTES counter. The field can also be read to learn the progress of the transfer. NBYTES can be incremented or decremented automatically by hardware.
Page 461 AT32UC3A3 22.9.3 Timing Register Name: Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 SUDAT TTOUT TLOWS • EXP: Clock Prescaler Used to specify how to prescale the SMBus TLOWS counter. The counter is prescaled according to the following formula: CLK_TWIS ------------------------ - PRESCALED •...
Page 462 AT32UC3A3 22.9.4 Receive Holding Register Name: Access Type: Read-only Offset: 0x0C Reset Value: 0x00000000 RXDATA • RXDATA: Received Data Byte When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus. 32072H–AVR32–10/2012...
Page 463 AT32UC3A3 22.9.5 Transmit Holding Register Name: Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 TXDATA • TXDATA: Data Byte to Transmit Write data to be transferred on the TWI bus here. 32072H–AVR32–10/2012...
Page 464 AT32UC3A3 22.9.6 Packet Error Check Register Name: PECR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 • PEC: Calculated PEC Value The calculated PEC value. Updated automatically by hardware after each byte has been transferred. Reset by hardware after a STOP condition.
Page 465 AT32UC3A3 22.9.7 Status Register Name: Access Type: Read-only Offset: 0x18 Reset Value: 0x000000002 SMBDAM SMBHHM SMBALERTM BUSERR SMBPECERR SMBTOUT ORUN URUN TCOMP TXRDY RXRDY • BTF: Byte Transfer Finished This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when byte transfer has completed.
Page 466 AT32UC3A3 • SMBPECERR: SMBus PEC Error This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus PEC error has occurred. • SMBTOUT: SMBus Timeout This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus timeout has occurred.
Page 467 AT32UC3A3 22.9.8 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 SMBDAM SMBHHM SMBALERTM BUSERR SMBPECERR SMBTOUT ORUN URUN TCOMP TXRDY RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will write a one to the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 468 AT32UC3A3 22.9.9 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 SMBDAM SMBHHM SMBALERTM BUSERR SMBPECERR SMBTOUT ORUN URUN TCOMP TXRDY RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 469 AT32UC3A3 22.9.10 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x24 Reset Value: 0x00000000 SMBDAM SMBHHM SMBALERTM BUSERR SMBPECERR SMBTOUT ORUN URUN TCOMP TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one.
Page 470 AT32UC3A3 22.9.11 Status Clear Register Name: Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 SMBDAM SMBHHM SMBALERTM BUSERR SMBPECERR SMBTOUT ORUN URUN TCOMP Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 32072H–AVR32–10/2012...
Page 471 AT32UC3A3 22.9.12 Parameter Register Name: Access Type: Read-only Offset: 0x2C Reset Value: 32072H–AVR32–10/2012...
Page 472 AT32UC3A3 22.9.13 Version Register (VR) Name: Access Type: Read-only Offset: 0x30 Reset Value: VARIANT VERSION [11:8] VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32072H–AVR32–10/2012...
Page 473: Module Configuration
AT32UC3A3 22.10 Module Configuration The specific configuration for each TWIS instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 22-7. Module Clock Name Module name Clock name...
Page 474: Two-Wire Master Interface (Twim)
400 kbit/s, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus serial EEPROM and I²C compatible device such as a real time clock (RTC), dot matrix/graphic LCD controller, and temperature sensor, to name a few.
Page 475: List Of Abbreviations
AT32UC3A3 lists the compatibility level of the Atmel Two-wire Master Interface and a full SMBus Table 23-2 compatible master. Table 23-2. Atmel TWIM Compatibility with SMBus Standard SMBus Standard Atmel TWIM Bus Timeouts Supported Address Resolution Protocol Supported Alert Supported...
Page 476 AT32UC3A3 23.5 Application Block Diagram Figure 23-2. Application Block Diagram TWCK Master TWALM Atmel TWI C LCD C temp C RTC serial EEPROM controller sensor Slave 1 Slave 2 Slave 3 Slave 4 Rp: pull-up value as given by the I2C Standard 23.6...
Page 477 AT32UC3A3 23.7.3 Clocks The clock for the TWIM bus interface (CLK_TWIM) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis- able the TWIM before disabling the clock, to avoid freezing the TWIM in an undefined state. 23.7.4 The TWIM DMA handshake interface is connected to the Peripheral DMA Controller.
Page 478 AT32UC3A3 23.8 Functional Description 23.8.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 23-4).
Page 479 AT32UC3A3 23.8.2.1 Clock Generation The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK clock. CWGR must be written so that the desired TWI bus timings are generated. CWGR describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be selected through the Clock Prescaler field in CWGR (CWGR.EXP).
Page 480 AT32UC3A3 23.8.2.2 Setting up and Performing a Transfer Operation of the TWIM is mainly controlled by the Control Register (CR) and the Command Reg- ister (CMDR). TWIM status is provided in the Status Register (SR). The following list presents the main steps in a typical communication: 1.
Page 481 AT32UC3A3 TWI transfers require the slave to acknowledge each received data byte. During the acknowl- edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not acknowledge the data byte.
Page 482 AT32UC3A3 1. Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state of RHR. Software or the Peripheral DMA Controller must read any data byte present in RHR. 2. Release TWCK generating a clock that the slave uses to transmit a data byte. 3.
Page 483 AT32UC3A3 23.8.5 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space to place received data. To assure correct behavior, respect the following programming sequences: 23.8.5.1 Data Transmit with the Peripheral DMA Controller...
Page 484 AT32UC3A3 Figure 23-10. User Sends Data While the Bus is Busy TWCK STOP sent by the master START sent by the TWI DATA sent by a master DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed Bus is considered as free...
Page 485 AT32UC3A3 As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when data to transmit can be written to THR, or when received data can be read from RHR. Transfer of data to THR and from RHR can also be done automatically by DMA, see Section 23.8.5 23.8.7.1 Write Followed by Write...
Page 486 AT32UC3A3 Figure 23-12. Combining a Write and Read Transfer DATA0 DATA1 DATA2 DATA3 DADR DATA0 DATA1 DADR DATA2 DATA3 SR.IDLE TXRDY RXRDY To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3.
Page 487 AT32UC3A3 23.8.8 Ten Bit Addressing Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of CMDR.SADR must be written appropriately. Figure 23-14 Figure 23-15, the grey boxes represent signals driven by the master, the white boxes are driven by the slave.
Page 488 AT32UC3A3 23.8.9.1 Packet Error Checking Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to CMDR.PECEN enables automatic PEC handling in the current transfer. Transfers with and with- out PEC can freely be intermixed in the same system, since some slaves may not support PEC. The PEC LFSR is always updated on every bit transmitted or received, so that PEC handling on combined transfers will be correct.
Page 489 AT32UC3A3 23.8.10 Identifying Bus Events This chapter lists the different bus events, and how they affect bits in the TWIM registers. This is intended to help writing drivers for the TWIM. Table 23-5. Bus Events Event Effect Master transmitter has sent SR.THR is cleared.
Page 490 AT32UC3A3 23.9 User Interface Table 23-6. TWIM Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register Write-only 0x00000000 0x04 Clock Waveform Generator Register CWGR Read/Write 0x00000000 0x08 SMBus Timing Register SMBTR Read/Write 0x00000000 0x0C Command Register CMDR Read/Write 0x00000000 0x10...
Page 491 AT32UC3A3 23.9.1 Control Register Name: Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 STOP SWRST SMDIS SMEN MDIS • STOP: Stop the Current Transfer Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle. If there are additional pending transfers, they will have to be explicitly restarted by software after the STOP condition has been successfully sent.
Page 492 AT32UC3A3 23.9.2 Clock Waveform Generator Register Name: CWGR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 DATA STASTO HIGH • EXP: Clock Prescaler Used to specify how to prescale the TWCK clock. Counters are prescaled according to the following formula CLK_TWIM ------------------------- - PRESCALER...
Page 493 AT32UC3A3 23.9.3 SMBus Timing Register Name: SMBTR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 THMAX TLOWM TLOWS • EXP: SMBus Timeout Clock Prescaler Used to specify how to prescale the TIM and TLOWM counters in SMBTR. Counters are prescaled according to the following formula CLKTWIM ------------------------...
Page 494 AT32UC3A3 23.9.4 Command Register Name: CMDR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 ACKLAST PECEN NBYTES VALID STOP START REPSAME TENBIT SADR[9:7] SADR[6:0] READ • ACKLAST: ACK Last Master RX Byte 0: Causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed. This is the standard way of ending a master receiver transfer.
Page 495 AT32UC3A3 Write this bit to one if the command in CMDR performs a repeated start to the same slave address as addressed in the previous transfer in order to enter master receiver mode. Write this bit to zero otherwise. • TENBIT: Ten Bit Addressing Mode 0: Use 7-bit addressing mode.
Page 496 AT32UC3A3 23.9.5 Next Command Register Name: NCMDR Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 ACKLAST PECEN NBYTES VALID STOP START REPSAME TENBIT SADR[9:7] SADR[6:0] READ This register is identical to CMDR. When the VALID bit in CMDR becomes 0, the content of NCMDR is copied into CMDR, clearing the VALID bit in NCMDR.
Page 497 AT32UC3A3 23.9.6 Receive Holding Register Name: Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 RXDATA • RXDATA: Received Data When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus. 32072H–AVR32–10/2012...
Page 498 AT32UC3A3 23.9.7 Transmit Holding Register Name: Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 TXDATA • TXDATA: Data to Transmit Write data to be transferred on the TWI bus here. 32072H–AVR32–10/2012...
Page 499 AT32UC3A3 23.9.8 Status Register Name: Access Type: Read-only Offset: 0x1C Reset Value: 0x00000002 MENB STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK BUSFREE IDLE CCOMP CRDY TXRDY RXRDY • MENB: Master Interface Enable 0: Master interface is disabled. 1: Master interface is enabled. •...
Page 500 AT32UC3A3 • IDLE: Master Interface is Idle This bit is one when no command is in progress, and no command waiting to be issued. Otherwise, this bit is cleared. • CCOMP: Command Complete This bit is one when the current command has completed successfully. This bit is zero if the command failed due to conditions such as a NAK receved from slave.
Page 501 AT32UC3A3 23.9.9 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 PECERR TOUT SMBALERT ARBLST DNAK ANAK BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR 32072H–AVR32–10/2012...
Page 502 AT32UC3A3 23.9.10 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 PECERR TOUT SMBALERT ARBLST DNAK ANAK BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR 32072H–AVR32–10/2012...
Page 503 AT32UC3A3 23.9.11 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 PECERR TOUT SMBALERT ARBLST DNAK ANAK BUSFREE IDLE CCOMP CRDY TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one.
Page 504 AT32UC3A3 23.9.12 Status Clear Register Name: Access Type : Write-only Offset: 0x2C Reset Value: 0x00000000 STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK CCOMP Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 32072H–AVR32–10/2012...
Page 505 AT32UC3A3 23.9.13 Parameter Register (PR) Name: Access Type: Read-only Offset: 0x30 Reset Value: 32072H–AVR32–10/2012...
Page 506 AT32UC3A3 23.9.14 Version Register (VR) Name: Access Type: Read-only Offset: 0x34 Reset Value: VARIANT VERSION [11:8] VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32072H–AVR32–10/2012...
Page 507 AT32UC3A3 23.10 Module Configuration The specific configuration for each TWIM instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 23-7. Module Clock Name Module name Clock name...
Page 508 AT32UC3A3 24. Synchronous Serial Controller (SSC) Rev: 3.2.0.2 24.1 Features • Provides serial synchronous communication links used in audio and telecom applications • Independent receiver and transmitter, common clock divider • Interfaced with two Peripheral DMA Controller channels to reduce processor overhead •...
Page 509 AT32UC3A3 24.3 Block Diagram Figure 24-1. SSC Block Diagram High Speed Peripheral Bus Bridge Peripheral DMA Controller Peripheral TX_FRAME_SYNC TX_CLOCK TX_DATA Power CLK_SSC Manager SSC Interface Controller RX_FRAME_SYNC RX_CLOCK Interrupt Control RX_DATA SSC Interrupt 24.4 Application Block Diagram Figure 24-2. SSC Application Block Diagram Test Power Interrupt...
Page 510 AT32UC3A3 24.5 I/O Lines Description Table 24-1. I/O Lines Description Pin Name Pin Description Type RX_FRAME_SYNC Receiver Frame Synchro Input/Output RX_CLOCK Receiver Clock Input/Output RX_DATA Receiver Data Input TX_FRAME_SYNC Transmitter Frame Synchro Input/Output TX_CLOCK Transmitter Clock Input/Output TX_DATA Transmitter Data Output 24.6 Product Dependencies...
Page 511 AT32UC3A3 Figure 24-3. SSC Functional Block Diagram Transmitter Clock Output TX_CLOCK Controller TX_CLOCK Input CLK_SSC Clock Transmit Clock Frame Sync TX clock TX_FRAME_SYNC Divider Controller Controller RX clock TX_FRAME_SYNC Start TX_DATA Transmit Shift Register RX_FRAME_SYNC Selector Transmit Holding Transmit Sync TX_DMA Peripheral Register...
Page 512 AT32UC3A3 24.7.1.1 Clock divider Figure 24-4. Divided Clock Block Diagram Clock Divider CLK_SSC Divided Clock 12-bit Counter The peripheral clock divider is determined by the 12-bit Clock Divider field (its maximal value is 4095) in the Clock Mode Register (CMR.DIV), allowing a peripheral clock division by up to 8190. The divided clock is provided to both the receiver and transmitter.
Page 513 AT32UC3A3 be inverted independently by writing a one to the Transmit Clock Inversion bit in TCMR (TCMR.CKI). The transmitter can also drive the TX_CLOCK pin continuously or be limited to the actual data transfer, depending on the Transmit Clock Output Mode Selection field in the TCMR register (TCMR.CKO).
Page 514 AT32UC3A3 Figure 24-7. Receiver Clock Management RX_CLOCK Tri-state Clock Controller Output Transmitter Clock Divider Clock Data Transfer Tri-state Receiver Controller Clock 24.7.1.4 Serial clock ratio considerations The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TX_CLOCK or RX_CLOCK pins.
Page 515 AT32UC3A3 Figure 24-8. Transmitter Block Diagram CR.TXEN SR.TXEN CR.TXDIS TFMR.DATDEF TCMR.STTDLY TFMR.FSDEN TFMR.DATNB TX_FRAME_SYNC TX_DATA TFMR.MSBF RX_FRAME_SYNC Transmitter Clock Start Transmit Shift Register Selector TFMR.FSDEN TCMR.STTDLY TFMR.FSLEN TFMR.DATLEN TSHR 24.7.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission.
Page 516 AT32UC3A3 Figure 24-9. Receiver Block Diagram R X _ C L O C K T ri-sta te M U X C lo ck C o n tro lle r O u tp u t T ra n sm itte r C lo ck D ivid e r C lo ck...
Page 517 AT32UC3A3 Figure 24-10. Transmit Start Mode TX_CLOCK (Input) TX_FRAME_SYNC (Input) TX_DATA (Output) Start= Low Level on TX_FRAME_SYNC STTDLY TX_DATA (Output) Start= Falling Edge on TX_FRAME_SYNC STTDLY TX_DATA (Output) Start= High Level on TX_FRAME_SYNC STTDLY TX_DATA (Output) Start= Rising Edge on TX_FRAME_SYNC STTDLY TX_DATA (Output) Start= Level Change on TX_FRAME_SYNC...
Page 518 AT32UC3A3 24.7.5 Frame Sync The transmitter and receiver frame synchro pins, TX_FRAME_SYNC and RX_FRAME_SYNC, can be programmed to generate different kinds of frame synchronization signals. The RFMR.FSOS and TFMR.FSOS fields are used to select the required waveform. • Programmable low or high levels during data transfer are supported. •...
Page 519 AT32UC3A3 and Transmit Sync bits in the SR register (SR.RXSYN and SR.TXSYN) on frame synchro edge detection (signals RX_FRAME_SYNC/TX_FRAME_SYNC). 24.7.6 Receive Compare Modes Figure 24-12. Receive Compare Modes RX_CLOCK RX_DATA CMP0 CMP2 Ignored CMP1 CMP3 (Input) Start {FSLENHI,FSLEN} STTDLY DATLEN Up to 256 Bits (4 in This Example) 24.7.6.1...
Page 520 AT32UC3A3 Table 24-3. Data Framing Format Registers Transmitter Receiver Bit/Field Length Comment Number of words transmitted in TFMR RFMR DATNB Up to 16 frame TFMR RFMR DATLEN Up to 32 Size of word TFMR RFMR {FSLENHI,FSLEN} Up to 256 Size of Synchro data register TFMR RFMR MSBF...
Page 521 AT32UC3A3 Figure 24-15. Receive Frame Format in Continuous Mode Start = Enable Receiver RX_DATA Data Data To RHR To RHR DATLEN DATLEN Note: STTDLY is written to zero. 24.7.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by writing a one to the Loop Mode bit in RFMR register (RFMR.LOOP).
Page 522 AT32UC3A3 24.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 24-17.
Page 523 AT32UC3A3 Figure 24-19. Time Slot Application Block Diagram SCLK TX_CLOCK FSYNC TX_FRAME_SYNC CODEC First Data Out Time Slot TX_DATA Data in RX_DATA RX_FRAME_SYNC RX_CLOCK CODEC Second Time Slot Serial Data Clock (SCLK) First Time Slot Second Time Slot Frame sync (FSYNC) Dstart Dend Serial Data Out...
Page 524 AT32UC3A3 24.9 User Interface Table 24-4. SSC Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register Write-only 0x00000000 0x04 Clock Mode Register Read/Write 0x00000000 0x10 Receive Clock Mode Register RCMR Read/Write 0x00000000 0x14 Receive Frame Mode Register RFMR Read/Write 0x00000000...
Page 525 AT32UC3A3 24.9.1 Control Register Name: Access Type: Write-only Offset: 0x00 Reset value: 0x00000000 SWRST TXDIS TXEN RXDIS RXEN • SWRST: Software Reset 1: Writing a one to this bit will perform a software reset. This software reset has priority on any other bit in CR. 0: Writing a zero to this bit has no effect.
Page 526 AT32UC3A3 24.9.2 Clock Mode Register Name: Access Type: Read/Write Offset: 0x04 Reset value: 0x00000000 DIV[11:8] DIV[7:0] • DIV[11:0]: Clock Divider The divided clock equals the CLK_SSC divided by two times DIV. The maximum bit rate is CLK_SSC/2. The minimum bit rate is CLK_SSC/(2 x 4095) = CLK_SSC/8190.
Page 527 AT32UC3A3 24.9.3 Receive Clock Mode Register Name: RCMR Access Type: Read/Write Offset: 0x10 Reset value: 0x00000000 PERIOD STTDLY STOP START • PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected receive clock in order to generate a periodic Frame Sync Signal. If equal to zero, no signal is generated.
Page 528 AT32UC3A3 • START: Receive Start Selection START Receive Start Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Transmit start Detection of a low level on RX_FRAME_SYNC signal Detection of a high level on RX_FRAME_SYNC signal Detection of a falling edge on RX_FRAME_SYNC signal Detection of a rising edge on RX_FRAME_SYNC signal Detection of any level change on RX_FRAME_SYNC signal...
Page 529 AT32UC3A3 24.9.4 Receive Frame Mode Register Name: RFMR Access Type: Read/Write Offset: 0x14 Reset value: 0x00000000 FSLENHI FSEDGE FSOS FSLEN DATNB MSBF LOOP DATLEN • FSLENHI: Receive Frame Sync Length High Part The four MSB of the FSLEN field. • FSEDGE: Receive Frame Sync Edge Detection Determines which edge on Frame Sync will generate the SR.RXSYN interrupt.
Page 530 AT32UC3A3 • DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). • MSBF: Most Significant Bit First 1: The most significant bit of the data register is sampled first in the bit stream. 0: The lowest significant bit of the data register is sampled first in the bit stream.
Page 531 AT32UC3A3 24.9.5 Transmit Clock Mode Register Name: TCMR Access Type: Read/Write Offset: 0x18 Reset value: 0x00000000 PERIOD STTDLY START • PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected transmit clock in order to generate a periodic Frame Sync Signal. If equal to zero, no signal is generated.
Page 532 AT32UC3A3 • CKG: Transmit Clock Gating Selection Transmit Clock Gating None, continuous clock Transmit Clock enabled only if TX_FRAME_SYNC is low Transmit Clock enabled only if TX_FRAME_SYNC is high Reserved • CKI: Transmit Clock Inversion CKI affects only the Transmit Clock and not the output clock signal. 1: The data outputs (Data and Frame Sync signals) are shifted out on transmit clock rising edge.
Page 533 AT32UC3A3 24.9.6 Transmit Frame Mode Register Name: TFMR Access Type: Read/Write Offset: 0x1C Reset value: 0x00000000 FSLENHI FSEDGE FSDEN FSOS FSLEN DATNB MSBF DATDEF DATLEN • FSLENHI: Transmit Frame Sync Length High Part The four MSB of the FSLEN field. •...
Page 534 AT32UC3A3 The pulse length is equal to ({FSLENHI,FSLEN} + 1) transmit clock periods, i.e., the pulse length can range from 1 to 256 transmit clock periods. If {FSLENHI,FSLEN} is zero, the Transmit Frame Sync signal is generated during one transmit clock period.
Page 535 AT32UC3A3 24.9.7 Receive Holding Register Name: Access Type: Read-only Offset: 0x20 Reset value: 0x00000000 RDAT[31:24] RDAT[23:16] RDAT[15:8] RDAT[7:0] • RDAT: Receive Data Right aligned regardless of the number of data bits defined by the RFMR.DATLEN field. 32072H–AVR32–10/2012...
Page 536 AT32UC3A3 24.9.8 Transmit Holding Register Name: Access Type: Write-only Offset: 0x24 Reset value: 0x00000000 TDAT[31:24] TDAT[23:16] TDAT[15:8] TDAT[7:0] • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by the TFMR.DATLEN field. 32072H–AVR32–10/2012...
Page 537 AT32UC3A3 24.9.9 Receive Synchronization Holding Register Name: RSHR Access Type: Read-only Offset: 0x30 Reset value: 0x00000000 RSDAT[15:8] RSDAT[7:0] • RSDAT: Receive Synchronization Data 32072H–AVR32–10/2012...
Page 538 AT32UC3A3 24.9.10 Transmit Synchronization Holding Register Name: TSHR Access Type: Read/Write Offset: 0x34 Reset value: 0x00000000 TSDAT[15:8] TSDAT[7:0] • TSDAT: Transmit Synchronization Data 32072H–AVR32–10/2012...
Page 539 AT32UC3A3 24.9.11 Receive Compare 0 Register Name: RC0R Access Type: Read/Write Offset: 0x38 Reset value: 0x00000000 CP0[15:8] CP0[7:0] • CP0: Receive Compare Data 0 32072H–AVR32–10/2012...
Page 540 AT32UC3A3 24.9.12 Receive Compare 1 Register Name: RC1R Access Type: Read/Write Offset: 0x3C Reset value: 0x00000000 CP1[[15:8] CP1[7:0] • CP1: Receive Compare Data 1 32072H–AVR32–10/2012...
Page 541 AT32UC3A3 24.9.13 Status Register Name: Access Type: Read-only Offset: 0x40 Reset value: 0x000000CC RXEN TXEN RXSYN TXSYN OVRUN RXRDY TXEMPTY TXRDY • RXEN: Receive Enable This bit is set when the CR.RXEN bit is written to one. This bit is cleared when no data are being processed and the CR.RXDIS bit has been written to one. •...
Page 542 AT32UC3A3 • TXRDY: Transmit Ready This bit is set when the THR register is empty. This bit is cleared when data has been loaded in the THR register and is waiting to be loaded in the TSR register. 32072H–AVR32–10/2012...
Page 543 AT32UC3A3 24.9.14 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x44 Reset value: 0x00000000 RXSYN TXSYN – – OVRUN RXRDY – – TXEMPTY TXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 544 AT32UC3A3 24.9.15 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x48 Reset value: 0x00000000 RXSYN TXSYN – – OVRUN RXRDY – – TXEMPTY TXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 545 AT32UC3A3 24.9.16 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x4C Reset value: 0x00000000 RXSYN TXSYN – – OVRUN RXRDY – – TXEMPTY TXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one.
Page 546 AT32UC3A3 25. Universal Synchronous Asynchronous Receiver Transmitter (USART) Rev: 4.2.0.6 25.1 Features • Configurable baud rate generator • 5- to 9-bit full-duplex, synchronous and asynchronous, serial communication – 1, 1.5, or 2 stop bits in asynchronous mode, and 1 or 2 in synchronous mode –...
Page 547 AT32UC3A3 frame lengths with the time-out feature. The USART supports several operating modes, provid- ing an interface to RS485, LIN, and SPI buses, with ISO7816 T=0 and T=1 smart card slots, infrared transceivers, and modem port connections. Communication with slow and remote devices is eased by the timeguard.
Page 548 AT32UC3A3 Table 25-1. SPI Operating Mode USART SPI Slave SPI Master MOSI MISO MISO MOSI – – 25.4 I/O Lines Description Table 25-2. I/O Lines Description Name Description Type Active Level Serial Clock Transmit Serial Data or Master Out Slave In (MOSI) in SPI master mode Output or Master In Slave Out (MISO) in SPI slave mode Receive Serial Data...
Page 549 AT32UC3A3 25.5.2 Clocks The clock for the USART bus interface (CLK_USART) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis- able the USART before disabling the clock, to avoid freezing the USART in an undefined state. 25.5.3 Interrupts The USART interrupt request line is connected to the interrupt controller.
Page 550 AT32UC3A3 25.6 Functional Description 25.6.1 USART Operating Modes The USART can operate in several modes: • Normal • RS485, described in Section 25.6.5 ”RS485 Mode” on page 560 • Hardware handshaking, described in Section 25.6.6 ”Hardware Handshaking” on page 561 •...
Page 551 AT32UC3A3 4. Check that CSR.TXRDY and/or CSR.RXRDY is one before writing to THR and/or read- ing from RHR respectively 25.6.2.1 Receiver and Transmitter Control After a reset, the transceiver is disabled. The receiver/transmitter is enabled by writing a one to the Receiver Enable/Transmitter Enable bit in the Control Register (CR.RXEN/CR.TXEN) respectively.
Page 552 AT32UC3A3 Figure 25-3. Transmitter Status Baud Rate Clock Start Parity Stop Start Parity Stop Write TXRDY TXEMPTY 25.6.2.3 Asynchronous Receiver If the USART is configured in an asynchronous operating mode (MR.SYNC is zero), the receiver will oversample the RXD input line by either 8 or 16 times the Baud Rate Clock, as selected by the Oversampling Mode bit (MR.OVER).
Page 553 AT32UC3A3 Figure 25-5. Asynchronous Mode Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock Start Detection samples samples samples samples samples samples samples samples samples samples Parity Stop 25.6.2.4 Synchronous Receiver In synchronous mode (MR.SYNC is one), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock, as illustrated in Figure 25-6.
Page 554 AT32UC3A3 Interrupt Mask Register (IMR.RXRDY) is set. If CSR.RXRDY is already set, RHR will be over- written and the Overrun Error bit (CSR.OVRE) is set. An interrupt request is generated if the Overrun Error bit in IMR is set. Reading RHR will clear CSR.RXRDY, and writing a one to the Reset Status bit in the Control Register (CR.RSTSTA) will clear CSR.OVRE.
Page 555 AT32UC3A3 25.6.3.2 Multidrop Mode If MR.PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates data and address characters. Data has the parity bit zero and addresses have a one. By writing a one to the Send Address bit (CR.SENDA) the user will cause the next character written to THR to be transmitted as an address.
Page 556 AT32UC3A3 25.6.3.4 Receiver Time-out The Time-out Value field in the Receiver Time-out Register (RTOR.TO) enables handling of vari- able-length frames by detection of selectable idle durations on the RXD line. The value written to TO is loaded to a decremental counter, and unless it is zero, a time-out will occur when the amount of inactive bit periods matches the initial counter value.
Page 557 AT32UC3A3 25.6.3.5 Framing Error The receiver is capable of detecting framing errors. A framing error has occurred if a stop bit reads as zero. This can occur if the transmitter and receiver are not synchronized. A framing error is reported by CSR.FRAME as soon as the error is detected, at the middle of the stop bit. An interrupt request is generated if the Framing Error bit in the Interrupt Mask Register (IMR.FRAME) is set.
Page 558 AT32UC3A3 25.6.3.7 Receive Break A break condition is assumed when incoming data, parity, and stop bits are zero. This corre- sponds to a framing error, but CSR.FRAME will remain zero while the Break Received/End of Break bit (CSR.RXBRK) is set. An interrupt request is generated if the Breadk Received/End of Break bit in the Interrupt Mask Register is set (IMR.RXBRK).
Page 559 AT32UC3A3 This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is the fastest clock available, and that MR.OVER is one. 25.6.4.2 Baud Rate Calculation Example Table 25-7 shows calculations based on the CD field to obtain 38400 baud from different source clock frequencies.
Page 560 AT32UC3A3 the Fractional Part field in BRGR (BRGR.FP), and is activated by giving it a non-zero value. The resolution is one eighth of CD. The resulting baud rate is calculated using the following formula: SelectedClock BaudRate ------------------------------------------------------------------- - ⎛ ⎛ ⎞...
Page 561 AT32UC3A3 Figure 25-15. Typical Connection to a RS485 Bus USART Differential If a timeguard has been configured the RTS pin will remain high for the duration specified in TG, as shown in Figure 25-16. Figure 25-16. Example of RTS Drive with Timeguard Enabled TG = 4 Baud Rate Clock...
Page 562 AT32UC3A3 Writing 0x2 to the MR.MODE field configures the USART to operate in hardware handshaking mode. The receiver will drive its RTS pin high when disabled or when the Reception Buffer Full bit (CSR.RXBUFF) is set by the Buffer Full signal from the Peripheral DMA controller. If the receiver RTS pin is high, the transmitter CTS pin will also be high and only the active character transmissions will be completed.
Page 563 AT32UC3A3 Table 25-8. Circuit References USART Pin V.24 CCITT Direction From terminal to modem From terminal to modem From terminal to modem The DTR pin is controlled by the DTR enable and disable bits in CR (CR.DTREN and CR.DTRDIS). Writing a one to CR.DTRDIS drives DTR high, and writing a one to CR.DTREN drives DTR low.
Page 564 AT32UC3A3 • B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor • f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 25-9.
Page 565 AT32UC3A3 Figure 25-21. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on CLK ISO7816 I/O Line on TXD 1 ETU 25.6.8.3 Protocol T=0 In T=0 protocol, a character is made up of one start bit, eight data bits, one parity bit, and a two bit period guard time.
Page 566 AT32UC3A3 25.6.8.7 Transmit Character Repetition The USART can be configured to automatically re-send a character if it receives a NACK. Writ- ing a non-zero value to MR.MAX_ITERATION will enable and determine the number of consecutive re-transmissions. If the number of unsuccessful re-transmissions equals MAX_ITERATION, the iteration bit (CSR.ITER) is set.
Page 567 AT32UC3A3 25.6.9.1 IrDA Modulation The RZI modulation scheme is used, where a zero is represented by a light pulse 3/16 of a bit period, and no pulse to represent a one. Some examples of signal pulse duration are shown in Table 25-12.
Page 568 AT32UC3A3 Table 25-13. IrDA Baud Rate Error (Continued) Peripheral Clock Baud Rate Baud Rate Error Pulse Time 3 686 400 38 400 0.00% 4.88 20 000 000 38 400 1.38% 4.88 32 768 000 38 400 0.63% 4.88 40 000 000 38 400 0.16% 4.88...
Page 569 AT32UC3A3 25.6.10.1 Modes of Operation Changing LIN mode after initial configuration must be followed by a transceiver software reset in order to avoid unpredictable behavior. 25.6.10.2 Receiver and Transmitter Control See Section “25.6.2.1” on page 551. 25.6.10.3 Baud Rate Configuration The LIN nodes baud rate is configured in the Baud Rate Generator Register (BRGR), See Sec- tion “25.6.4.1”...
Page 570 AT32UC3A3 Figure 25-28. Header Reception Baud Rate Clock Start Stop Start Stop Break Field Break ID0 ID1 ID2 Delimiter 13 dominant bits (at 0) Synch Byte = 0x55 1 recessive bit (at 1) LINID US_LINIR Write US_CR With RSTSTA=1 See also ”Slave Node Configuration”...
Page 571 AT32UC3A3 • The theoretical slave node clock frequency; nominal clock frequency (F • The baud rate • The oversampling mode (OVER=0 => 16x, or OVER=1 => 8x) The following formula is used to calculate synchronization deviation, where F is the real SLAVE slave node clock frequency, and F is the difference between F...
Page 572 AT32UC3A3 enabled by default, and can be disabled by writing a one to the Parity Disable bit in the LIN Mode register (LINMR.PARDIS). • LINMR.PARDIS=0: During header transmission, the parity bits are computed and in the shift register they replace bits 6 and 7 from LINIR.IDCHR. During header reception, the parity bits are checked and can generate a LIN Identifier Parity Error (see Section 25.6.10.13).
Page 573 AT32UC3A3 • LINMR.DLM=1: the response data length is defined by the Identifier (LINIR.IDCHR) bits according to the table below. Table 25-14. Response Data Length if DLM = 1 LINIR.IDCHR[5] LINIR.IDCHR[4] Response Data Length [bytes] 25.6.10.11 Checksum The last frame field is the checksum. It is configured by the Checksum Type (LINMR.CHKTYP), and the Checksum Disable (LINMR.CHKDIS) bits.
Page 574 AT32UC3A3 The minimum frame slot size is determined by TFrame_Maximum, and calculated below (all val- ues in bit periods): • THeader_Nominal = 34 • TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1) Note: The term “+1” leads to an integer result for TFrame_Max (LIN Specification 1.3) If the Checksum is sent (CHKDIS=0): •...
Page 575 AT32UC3A3 • Write a one to CR.TXEN and CR.RXEN to enable both transmitter and receiver • Wait until CSR.TXRDY is one • Send the header by writing to LINIR.IDCHR The following procedure depends on the LINMR.NACT setting: • Case 1: LINMR.NACT is 0x0 (PUBLISH, the USART transmits the response) –...
Page 576 AT32UC3A3 Figure 25-34. Master Node Configuration, LINMR.NACT is 0x1 (SUBSCRIBE) Frame slot = TFrame_Maximum Frame Inter- frame Response space space Header Data3 Response Break Synch Protected Data 1 Data N-1 Data N Checksum Identifier TXRDY FSDIS=1 FSDIS=0 RXRDY Write LINIR Read Data 1 Data N-2...
Page 577 AT32UC3A3 The different LINMR.NACT settings result in the same procedure as for the master node, see page 574. Figure 25-36. Slave Node Configuration, LINMR.NACT is 0x0 (PUBLISH) Break Synch Protected Data 1 Data N-1 Data N Checksum Identifier TXRDY RXRDY LINIDRX Read LINID...
Page 578 AT32UC3A3 CSR.RXRDY bits to trigger one byte writes or reads. It always writes to THR, and it always reads RHR. 25.6.12.1 Master Node Configuration The Peripheral DMA Controller Mode bit (LINMR.PDCM) allows the user to select configuration: • LINMR.PDCM=0: LIN configuration must be written to LINMR, it is not stored in the write buffer.
Page 579 AT32UC3A3 Figure 25-40. Master Node with Peripheral DMA Controller (LINMR.PDCM=1) WRITE BUFFER WRITE BUFFER NACT NACT PARDIS PARDIS CHKDIS CHKDIS CHKTYP CHKTYP FSDIS FSDIS NODE ACTION = SUBSCRIBE NODE ACTION = PUBLISH Peripheral Peripheral IDENTIFIER IDENTIFIER USART LIN Peripheral DMA USART LIN Peripheral DMA READ BUFFER...
Page 580 AT32UC3A3 According to LIN 1.3, the wakeup request should be generated with the character 0x80 in order to impose eight successive dominant bits. According to LIN 2.0, the wakeup request is issued by forcing the bus into the dominant state for 250µs to 5ms.
Page 581 AT32UC3A3 25.6.15.2 Baud Rate The baud rate generator operates as described in ”Baud Rate in Synchronous and SPI Mode” on page 560, with the following requirements: In SPI Master Mode: • External clock CLK must not be selected as clock (the Clock Selection field (MR.USCLKS) must not equal 0x3).
Page 582 AT32UC3A3 Figure 25-42. SPI Transfer Format (CPHA=1, 8 bits per transfer) CLK cycle (for reference) C LK (C POL= 0) C LK (CPO L= 1) M O SI M SB SPI M aster ->TXD SPI Slave ->RXD M ISO SPI M aster ->RXD M SB SPI Slave ->TXD SPI M aster ->RTS...
Page 583 AT32UC3A3 In SPI slave mode, a low level on NSS for at least one bit period will allow the slave to initiate a transmission or reception. The Underrun Error bit (CSR.UNRE) is set if a character must be sent while THR is empty, and TXD will be high during character transmission, as if 0xFF was being sent.
Page 584 AT32UC3A3 Figure 25-45. Preamble Patterns, Default Polarity Assumed Manchester encoded DATA data 8 bit width "ALL_ONE" Preamble Manchester encoded DATA data 8 bit width "ALL_ZERO" Preamble Manchester encoded DATA data 8 bit width "ZERO_ONE" Preamble Manchester encoded DATA data 8 bit width "ONE_ZERO" Preamble The Start Frame Delimiter Selector bit (MR.ONEBIT) configures the Manchester start bit pattern following the preamble.
Page 585 AT32UC3A3 Figure 25-46. Start Frame Delimiter Preamble Length is set to 0 Manchester encoded DATA data One bit start frame delimiter Manchester DATA encoded data Command Sync start frame delimiter Manchester encoded DATA data Data Sync start frame delimiter Manchester Drift Compensation The Drift Compensation bit (MAN.DRIFT) enables a hardware drift compensation and recovery system that allows for sub-optimal clock drifts without further user intervention.
Page 586 AT32UC3A3 The Manchester endec uses the same Start Frame Delimiter Selector (MR.ONEBIT) for both encoder and decoder. If ONEBIT is one, only a Manchester encoded zero will be accepted as a valid start frame delimiter. If ONEBIT is zero, a data or command sync pattern will be expected. The Received Sync bit in the Receive Holding Register (RHR.RXSYNH) will be zero if the last character received is a data sync, and a one if it is a command sync.
Page 587 AT32UC3A3 Figure 25-50. Manchester Error Preamble Length is set to 4 Elementary character bit time Manchester encoded data Entering USART character area sampling points Preamble subpacket Manchester and Start Frame Delimiter Coding Error were successfully detected decoded 25.6.16.3 Radio Interface: Manchester Endec Application This section describes low data rate, full duplex, dual frequency, RF systems integrated with a Manchester endec, that support ASK and/or FSK modulation schemes.
Page 588 AT32UC3A3 Figure 25-52. ASK Modulator Output NRZ stream Manchester encoded data default polarity unipolar output ASK Modulator Output Uptstream Frequency F0 Figure 25-53. FSK Modulator Output NRZ stream Manchester encoded data default polarity unipolar output FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 25.6.17 Test Modes...
Page 589 AT32UC3A3 Figure 25-55. Automatic Echo Mode Configuration Receiver Transmitter 25.6.17.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 25-56. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state.
Page 590 AT32UC3A3 PARE FRAME OVRE – – RXBRK TXRDY RXRDY The USART has the following interrupt sources: • LINSNRE: LIN Slave Not Responding Error – A LIN Slave Not Responding Error has been detected • LINCE: LIN Checksum Error – A LIN Checksum Error has been detected •...
Page 591 AT32UC3A3 – There has been a time-out since the last Start Time-out command. • PARE: Parity Error – Either at least one parity error has been detected, or the parity bit is a one in multidrop mode, since the last RSTSTA. •...
Page 592 AT32UC3A3 • ”Manchester Configuration Register” on page 614 32072H–AVR32–10/2012...
Page 593 AT32UC3A3 25.7 User Interface Table 25-17. USART Register Memory Map Offset Register Name Access Reset 0x00 Control Register Write-only 0x00000000 0x04 Mode Register Read-write 0x00000000 0x08 Interrupt Enable Register Write-only 0x00000000 0x0C Interrupt Disable Register Write-only 0x00000000 0x010 Interrupt Mask Register Read-only 0x00000000 0x14...
Page 594 AT32UC3A3 25.7.1 Control Register Name: Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 – – – – – – – – – – LINWKUP LINABT RTSDIS/RCS RTSEN/FCS DTRDIS DTREN RETTO RSTNACK RSTIT SENDA STTTO STPBRK STTBRK RSTSTA TXDIS TXEN RXDIS RXEN RSTTX RSTRX...
Page 595 AT32UC3A3 • SENDA: Send Address Writing a zero to this bit has no effect. Writing a one to this bit will in multidrop mode send the next character written to THR as an address. • STTTO: Start Time-out Writing a zero to this bit has no effect. Writing a one to this bit will abort any current time-out count down, and trigger a new count down when the next character has been received.
Page 596 AT32UC3A3 25.7.2 Mode Register Name: Access Type: Read-write Offset: 0x04 Reset Value: 0x00000000 ONEBIT MODSYNC FILTER – MAX_ITERATION – VAR_SYNC DSNACK INACK OVER CLKO MODE9 MSBF/CPOL CHMODE NBSTOP SYNC/CPHA CHRL USCLKS MODE This register can only be written if write protection is disabled in the “Write Protect Mode Register”...
Page 597 AT32UC3A3 • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • MSBF/CPOL: Bit Order or SPI Clock Polarity If USART does not operate in SPI Mode: MSBF=0: Least Significant Bit is sent/received first. MSBF=1: Most Significant Bit is sent/received first. If USART operates in SPI Mode, CPOL is used with CPHA to produce the required clock/data relationship between devices.
Page 598 AT32UC3A3 CPHA = 1: Data is captured on the leading edge of CLK and changed on the following edge of CLK. • CHRL: Character Length. Table 25-21. CHRL Character Length 5 bits 6 bits 7 bits 8 bits • USCLKS: Clock Selection Table 25-22.
Page 599 AT32UC3A3 25.7.3 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x08 Reset Value: 0x00000000 – – LINSNRE LINCE LINIPE LINISFE LINBE MANEA – – – MANE CTSIC DCDIC DSRIC RIIC LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT PARE FRAME OVRE –...
Page 600 AT32UC3A3 25.7.4 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 – – LINSNRE LINCE LINIPE LINISFE LINBE MANEA – – – MANE CTSIC DCDIC DSRIC RIIC LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT PARE FRAME OVRE –...
Page 601 AT32UC3A3 25.7.5 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 – – LINSNRE LINCE LINIPE LINISFE LINBE MANEA – – – MANE CTSIC DCDIC DSRIC RIIC LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT PARE FRAME OVRE –...
Page 602 AT32UC3A3 25.7.6 Channel Status Register Name: Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 – – LINSNRE LINCE LINIPE LINISFE LINBE MANERR CTSIC DCDIC DSRIC RIIC LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT PARE FRAME OVRE – – RXBRK TXRDY RXRDY •...
Page 603 AT32UC3A3 1: DSR is high. • RI: Image of RI Input 0: RI is low. 1: RI is high. • CTSIC: Clear to Send Input Change Flag 0: No change has been detected on the CTS pin since the last CSR read. 1: At least one change has been detected on the CTS pin since the last CSR read.
Page 604 AT32UC3A3 • PARE: Parity Error 0: Either no parity error has been detected, or the parity bit is a zero in multidrop mode, since the last RSTSTA. 1: Either at least one parity error has been detected, or the parity bit is a one in multidrop mode, since the last RSTSTA. This bit is cleared by writing a one to CR.RSTSTA.
Page 605 AT32UC3A3 25.7.7 Receiver Holding Register Name: Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 – – – – – – – – – – – – – – – – RXSYNH – – – – – – RXCHR[8] RXCHR[7:0] Reading this register will clear the CSR.RXRDY bit. •...
Page 606 AT32UC3A3 25.7.8 Transmitter Holding Register Name: Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 – – – – – – – – – – – – – – – – TXSYNH – – – – – – TXCHR[8] TXCHR[7:0] • TXSYNH: Sync Field to be transmitted 0: If MR.VARSYNC is one, the next character sent is encoded as data, and the start frame delimiter is a data sync.
Page 607 AT32UC3A3 25.7.9 Baud Rate Generator Register Name: BRGR Access Type: Read-write Offset: 0x20 Reset Value: 0x00000000 – – – – – – – – – – – – – CD[15:8] CD[7:0] This register can only be written if write protection is disabled in the “Write Protect Mode Register”...
Page 608 AT32UC3A3 Table 25-26. Baud Rate in ISO7816 Mode Baud Rate Baud Rate Clock Disabled Selected Clock 1 to 65535 Baud Rate ------------------------------------------------ - ⋅ FI_DI_RATIO CD 32072H–AVR32–10/2012...
Page 609 AT32UC3A3 25.7.10 Receiver Time-out Register Name: RTOR Access Type: Read-write Offset: 0x24 Reset Value: 0x00000000 – – – – – – – – – – – – – – – TO[16] TO[15:8] TO[7:0] This register can only be written if write protection is disabled in the “Write Protect Mode Register”...
Page 610 AT32UC3A3 25.7.11 Transmitter Timeguard Register Name: TTGR Access Type: Read-write Offset: 0x28 Reset Value: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – This register can only be written if write protection is disabled in the “Write Protect Mode Register”...
Page 611 AT32UC3A3 25.7.12 FI DI Ratio Register Name: FIDI Access Type: Read-write Offset: 0x40 Reset Value: 0x00000174 – – – – – – – – – – – – – – – – – – – – – FI_DI_RATIO[10:8] FI_DI_RATIO[7:0] This register can only be written if write protection is disabled in the “Write Protect Mode Register”...
Page 612 AT32UC3A3 25.7.13 Number of Errors Register Name: Access Type: Read-only Offset: 0x44 Reset Value: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – NB_ERRORS •...
Page 613 AT32UC3A3 25.7.14 IrDA Filter Register Name: Access Type: Read-write Offset: 0x4C Reset Value: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – IRDA_FILTER This register can only be written if write protection is disabled in the “Write Protect Mode Register”...
Page 614 AT32UC3A3 25.7.15 Manchester Configuration Register Name: Access Type: Read-write Offset: 0x50 Reset Value: 0x30011004 – DRIFT RX_MPOL – – RX_PP – – – – RX_PL – – – TX_MPOL – – TX_PP – – – – TX_PL This register can only be written if write protection is disabled in the “Write Protect Mode Register”...
Page 615 AT32UC3A3 • TX_PP: Transmitter Preamble Pattern Table 25-28. TX_PP Preamble Pattern default polarity assumed (TX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO • TX_PL: Transmitter Preamble Length 0: The transmitter preamble pattern generation is disabled. 1 - 15: The preamble length is TX_PL bit periods. 32072H–AVR32–10/2012...
Page 616 AT32UC3A3 25.7.16 LIN Mode Register Name: LINMR Access Type: Read-write Offset: 0x54 Reset Value: 0x00000000 – – – – – – – – – – – – – – – PDCM WKUPTYP FSDIS CHKTYP CHKDIS PARDIS NACT • PDCM: Peripheral DMA Controller Mode 0: The LIN mode register is not written by the Peripheral DMA Controller.
Page 617 AT32UC3A3 Table 25-29. SUBSCRIBE: The USART receives the response. IGNORE: The USART does not transmit and does not receive the response. Reserved 32072H–AVR32–10/2012...
Page 618 AT32UC3A3 25.7.17 LIN Identifier Register Name: LINIR Access Type: Read-write or Read-only Offset: 0x58 Reset Value: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – –...
Page 619 AT32UC3A3 25.7.18 Write Protect Mode Register Register Name: WPMR Access Type: Read-write Offset: 0xE4 Reset Value: Table 25-17 WPKEY[23:16] WPKEY[15:8] WPKEY[7:0] WPEN • WPKEY: Write Protect KEY Has to be written to 0x555341 (“USA” in ASCII) in order to successfully write WPEN. This bit always reads as zero. Writing the correct key to this field clears WPSR.WPVSRC and WPSR.WPVS.
Page 620 AT32UC3A3 25.7.19 Write Protect Status Register Register Name: WPSR Access Type: Read-only Offset: 0xE8 Reset Value: Table 25-17 WPVSRC[15:8] WPVSRC[7:0] WPVS • WPVSRC: Write Protect Violation Source If WPVS is one, this field indicates which write-protected register was unsuccessfully written to, either by address offset or code. •...
Page 621 AT32UC3A3 25.7.20 Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: VERSION[11:8] VERSION[7:0] • MFN Reserved. No functionality associated. • VERSION Version of the module. No functionality associated. 32072H–AVR32–10/2012...
Page 622 AT32UC3A3 26.1 Module Configuration The specific configuration for each USART instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Sys- tem Bus Clock Connections section. Table 26-1.
Page 623 AT32UC3A3 26.1.2 Register Reset Values Table 26-4. Register Reset Values Register Reset Value VERSION 0x00000420 32072H–AVR32–10/2012...
Page 624 AT32UC3A3 27. Hi-Speed USB Interface (USBB) Rev: 3.2.0.18 27.1 Features • Compatible with the USB 2.0 specification • Supports High (480Mbit/s), Full (12Mbit/s) and Low (1.5Mbit/s) speed Device and Embedded Host • eight pipes/endpoints • 2368bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints •...
Page 625 AT32UC3A3 Table 27-2. Example of Configuration of Pipes/Endpoints Using the Whole DPRAM Pipe/Endpoint Mnemonic Size Nb. Banks PEP1 512 bytes PEP2 512 bytes PEP3 256 bytes 27.3 Block Diagram The USBB provides a hardware device to interface a USB link to a data flow stored in a dual-port RAM (DPRAM).
Page 626 AT32UC3A3 27.4 Application Block Diagram Depending on the USB operating mode (device-only, reduced-host modes) and the power source (bus-powered or self-powered), there are different typical hardware implementations. 27.4.1 Device Mode 27.4.1.1 Bus-Powered device Figure 27-2. Bus-Powered Device Application Block Diagram 3.3 V Regulator USB_VBUS...
Page 627 AT32UC3A3 27.4.1.2 Self-Powered device Figure 27-3. Self-powered Device Application Block Diagram USB_VBUS Connector VBus USB_ID Controller USB_VBOF 2.0 Core DMFS ohms ohms DPFS UTMI DMHS DPHS 27.4.2 Host Mode Figure 27-4. Host Application Block Diagram 5V DC/DC Generator USB_VBUS Connector VBus USB_ID Controller...
Page 628 AT32UC3A3 27.5 I/O Lines Description Table 27-3. I/O Lines Description PIn Name Pin Description Type Active Level USB_VBOF USB VBus On/Off: Bus Power Control Port Output VBUSPO USB_VBUS VBus: Bus Power Measurement Port Input DMFS FS Data -: Full-Speed Differential Data Line - Port Input/Output DPFS FS Data +: Full-Speed Differential Data Line + Port...
Page 629 AT32UC3A3 27.6 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 27.6.1 I/O Lines The USB_VBOF and USB_ID pins are multiplexed with I/O Controller lines and may also be multiplexed with lines of other peripherals.
Page 630 AT32UC3A3 27.7 Functional Description 27.7.1 USB General Operation 27.7.1.1 Introduction After a hardware reset, the USBB is disabled. When enabled, the USBB runs either in device mode or in host mode according to the ID detection. If the USB_ID pin is not connected to ground, the USB_ID Pin State bit in the General Status register (USBSTA.ID) is set (the internal pull-up resistor of the USB_ID pin must be enabled by the I/O Controller) and device mode is engaged.
Page 631 AT32UC3A3 After writing a one to USBCON.USBE, the USBB enters the Device or the Host mode (according to the ID detection) in idle state. The USBB can be disabled at any time by writing a zero to USBCON.USBE. In fact, writing a zero to USBCON.USBE acts as a hardware reset, except that the OTGPADE, VBUSPO, FRZCLK, UIDE, UIMOD and, LS bits are not reset.
Page 632 AT32UC3A3 Figure 27-6. Interrupt System USBSTA.IDTI USBCON.IDTE USBSTA.VBUSTI USBCON.VBUSTE USBSTA.SRPI UESTAX.TXINI USBCON.SRPE UECONX.TXINE USBSTA.VBERRI UESTAX.RXOUTI USB General USBCON.VBERRE UECONX.RXOUTE Interrupt USBSTA.BCERRI UESTAX.RXSTPI USBCON.BCERRE UECONX.RXSTPE USBSTA.ROLEEXI UESTAX.UNDERFI USBCON.ROLEEXE UECONX.UNDERFE USBSTA.HNPERRI UESTAX.NAKOUTI USBCON.HNPERRE UECONX.NAKOUTE USBSTA.STOI UESTAX.HBISOINERRI USBCON.STOE UECONX.HBISOINERRE UESTAX.NAKINI UECONX.NAKINE UESTAX.HBISOFLUSHI UECONX.HBISOFLUSHE USB Device UESTAX.OVERFI Endpoint X...
Page 633 AT32UC3A3 The processing general interrupts are: • The ID Transition Interrupt (IDTI) • The VBus Transition Interrupt (VBUSTI) • The Role Exchange Interrupt (ROLEEXI) The exception general interrupts are: • The VBus Error Interrupt (VBERRI) • The B-Connection Error Interrupt (BCERRI) •...
Page 634 AT32UC3A3 Moreover, when FRZCLK is written to one, only the asynchronous interrupt sources may trigger the USB interrupt: • The ID Transition Interrupt (IDTI) • The VBus Transition Interrupt (VBUSTI) • The Wake-up Interrupt (WAKEUP) • The Host Wake-up Interrupt (HWUPI) •USB Suspend mode In peripheral mode, the Suspend Interrupt bit in the Device Global Interrupt register (UDINT.SUSP)indicates that the USB line is in the suspend mode.
Page 635 AT32UC3A3 To free its memory, the user shall write a zero to the UECFGn.ALLOC bit. The n+1 pipe/end- point memory window then slides down and its data is lost. Note that the following pipe/endpoint memory windows (from n+2) does not slide. Figure 27-7 on page 635 illustrates the allocation and reorganization of the DPRAM in a typical example.
Page 636 AT32UC3A3 FIFO size (i.e. the DPRAM size), so the value of CFGOK does not consider memory allocation conflicts. 27.7.1.7 Pad Suspend Figure 27-8 on page 636 shows the pad behavior. Figure 27-8. Pad Behavior USBE = 1 & DETACH = 0 &...
Page 637 AT32UC3A3 Moreover, the pad goes to the Idle state if the macro is disabled or if the DETACH bit is written to one. It returns to the Active state when USBE is written to one and DETACH is written to zero. 27.7.1.8 Plug-In detection The USB connection is detected from the USB_VBUS pad.
Page 638 AT32UC3A3 Figure 27-11. ID Detection Input Block Diagram USB_ID IDTI USBSTA UIMOD USBSTA USBCON UIDE USBCON I/O Controller The USB mode (device or host) can be either detected from the USB_ID pin or software selected by writing to the UIMOD bit, according to the UIDE bit. This allows the USB_ID pin to be used as a general purpose I/O pin even when the USB interface is enabled.
Page 639 AT32UC3A3 27.7.2 USB Device Operation 27.7.2.1 Introduction In device mode, the USBB supports hi- full- and low-speed data transfers. In addition to the default control endpoint, seven endpoints are provided, which can be config- ured with the types isochronous, bulk or interrupt, as described in .Table 27-1 on page 624.
Page 640 AT32UC3A3 • The default control endpoint is reset (see Section 27.7.2.4 for more details). • The data toggle sequence of the default control endpoint is cleared. • At the end of the reset process, the End of Reset (EORST) bit in UDINT interrupt is set. •...
Page 641 AT32UC3A3 Figure 27-13. Endpoint Activation Algorithm Endpoint Activation Enable the endpoint. EPENn = 1 Configure the endpoint: UECFGn - type EPTYPE - direction EPDIR - size EPSIZE EPBK - number of banks ALLOC Allocate the configured DPRAM banks. CFGOK == Test if the endpoint configuration is correct.
Page 642 AT32UC3A3 27.7.2.7 Suspend and wake-up When an idle USB bus state has been detected for 3 ms, the controller set the Suspend (SUSP) interrupt bit in UDINT. The user may then write a one to the FRZCLK bit to reduce power con- sumption.
Page 643 AT32UC3A3 •Special considerations for control endpoints If a SETUP packet is received into a control endpoint for which a STALL is requested, the Received SETUP Interrupt (RXSTPI) bit in UESTAn is set and STALLRQ and STALLEDI are cleared. The SETUP has to be ACKed. This management simplifies the enumeration process management.
Page 644 AT32UC3A3 Figure 27-14. Control Write SETUP DATA STATUS USB Bus SETUP RXSTPI RXOUTI TXINI •Control read Figure 27-15 on page 644 shows a control read transaction. The USBB has to manage the simultaneous write requests from the CPU and the USB host. Figure 27-15.
Page 645 AT32UC3A3 27.7.2.12 Management of IN endpoints •Overview IN packets are sent by the USB device controller upon IN requests from the host. All the data can be written which acknowledges or not the bank when it is full. The endpoint must be configured first. The TXINI bit is set at the same time as FIFOCON when the current bank is free.
Page 646 AT32UC3A3 Figure 27-17. Example of an IN Endpoint with 2 Data Banks DATA DATA (bank 0) (bank 1) TXINI write data to CPU FIFOCON write data to CPU write data to CPU BANK0 BANK 0 BANK 1 •Detailed description The data is written, following the next flow: •...
Page 647 AT32UC3A3 Figure 27-18. Abort Algorithm Endpoint Abort Disable the TXINI interrupt. TXINEC = 1 Abort is based on the fact NBUSYBK that no bank is busy, i.e., == 0? that nothing has to be sent Kill the last written bank. EPRSTn = 1 KILLBKS = 1 Wait for the end of the...
Page 648 AT32UC3A3 Figure 27-19. Example of an OUT Endpoint with one Data Bank DATA DATA (bank 0) (bank 0) RXOUTI read data from CPU read data from CPU FIFOCON BANK 0 BANK 0 Figure 27-20. Example of an OUT Endpoint with two Data Banks DATA DATA (bank 1)
Page 649 AT32UC3A3 responds to the OUT/DATA transaction with an ACK handshake when the endpoint accepted the data successfully and has room for another data payload (the second bank is free). 27.7.2.14 Underflow This error exists only for isochronous IN/OUT endpoints. It set the Underflow Interrupt (UNDERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Underflow Interrupt Enable (UNDERFE) bit is one.
Page 650 AT32UC3A3 For instance, if NBTRANS is three (three transactions per micro-frame), if only the first IN token (among 3) is well received by the USBB, then the two last banks will be discarded. 27.7.2.18 CRC error This error exists only for isochronous OUT endpoints. It set the CRC Error Interrupt (CRCERRI) bit in UESTAn, what triggers an EPnINT interrupt if the CRC Error Interrupt Enable (CRCERRE) bit is one.
Page 651 AT32UC3A3 • The NAKed OUT Interrupt (NAKOUTI) • The High-bandwidth isochronous IN error Interrupt (HBISOINERRI) if the high-bandwidth isochronous feature is supported by the device (see the UFEATURES register for this) • The NAKed IN Interrupt (NAKINI) • The High-bandwidth isochronous IN Flush error Interrupt (HBISOFLUSHI) if the high- bandwidth isochronous feature is supported by the device (see the UFEATURES register for this) •...
Page 652 AT32UC3A3 27.7.3 USB Host Operation 27.7.3.1 Description of pipes For the USBB in host mode, the term “pipe” is used instead of “endpoint” (used in device mode). A host pipe corresponds to a device endpoint, as described by the Figure 27-21 on page 652 from the USB specification.
Page 653 AT32UC3A3 sumption. The USB pad should be in the Idle state. Once a device is connected, the macro enters the Ready state, what does not require the USB clock to be activated. The controller enters the Suspend state when the USB bus is in a “Suspend” state, i.e., when the host mode does not generate the “Start of Frame (SOF)”.
Page 654 AT32UC3A3 27.7.3.6 Pipe activation The pipe is maintained inactive and reset (see Section 27.7.3.5 for more details) as long as it is disabled (PENn is zero). The Data Toggle Sequence field (DTSEQ) is also reset. The algorithm represented on Figure 27-23 on page 654 must be followed in order to activate a pipe.
Page 655 AT32UC3A3 When the host controller sends an USB reset, the UHADDRPn field is reset by hardware and the following host requests will be performed using the default device address 0. 27.7.3.8 Remote wake-up The controller host mode enters the Suspend state when the UHCON.SOFE bit is written to zero.
Page 656 AT32UC3A3 RXINI shall be cleared by software (by writing a one to the Received IN Data Interrupt Clear bit in the Pipe n Control Clear register(UPCONnCLR.RXINIC)) to acknowledge the interrupt, what has no effect on the pipe FIFO. The user then reads from the FIFO (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn- DATA)”...
Page 657 AT32UC3A3 The Transmitted OUT Data Interrupt (TXOUTI) bit in UPSTAn is set at the same time as FIFO- CON when the current bank is free. This triggers a PnINT interrupt if the Transmitted OUT Data Interrupt Enable (TXOUTE) bit in UPCONn is one. TXOUTI shall be cleared by software (by writing a one to the Transmitted OUT Data Interrupt Clear (TXOUTIC) bit in UPCONnCLR) to acknowledge the interrupt, what has no effect on the pipe FIFO.
Page 658 AT32UC3A3 Figure 27-27. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay DATA DATA (bank 0) (bank 1) TXOUTI write data to CPU write data to CPU write data to CPU FIFOCON BANK 0 BANK 1 BANK0 Figure 27-28.
Page 659 AT32UC3A3 • The USB Reset Sent Interrupt (RSTI) • The Downstream Resume Sent Interrupt (RSMEDI) • The Upstream Resume Received Interrupt (RXRSMI) • The Host Start of Frame Interrupt (HSOFI) • The Host Wake-Up Interrupt (HWUPI) • The Pipe n Interrupt (PnINT) •...
Page 660 AT32UC3A3 27.7.4 USB DMA Operation 27.7.4.1 Introduction USB packets of any length may be transferred when required by the USBB. These transfers always feature sequential addressing. These two characteristics mean that in case of high USBB throughput, both HSB ports will benefit from “incrementing burst of unspecified length” since the average access latency of HSB slaves can then be reduced.
Page 661 AT32UC3A3 Figure 27-29. Example of DMA Chained List Transfer Descriptor USB DMA Channel X Registers (Current Transfer Descriptor) Next Descriptor Address Transfer Descriptor HSB Address Next Descriptor Address Next Descriptor Address Control HSB Address Transfer Descriptor HSB Address Control Next Descriptor Address Control HSB Address Status...
Page 662 AT32UC3A3 •Single-block transfer programming example for OUT transfer : The following sequence may be used: • Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching for this endpoint in the UECFGn register to handle multiple OUT packet. •...
Page 663 AT32UC3A3 •Programming example for multi-block dma transfer : run and link at end of buffer The idea is to run first a single block transfer followed automatically by a linked list of DMA. The following sequence may be used: • Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching for this endpoint in the UECFGn register to handle multiple OUT packet.
Page 664 AT32UC3A3 • Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items : channel next descriptor address, channel destination address and channel control. The last descriptor should be programmed according to row 2 as shown in Figure 27-6 on page 714.
Page 665 AT32UC3A3 27.8 User Interface Table 27-4. USBB Register Memory Map Offset Register Name Access Reset Value 0x0000 Device General Control Register UDCON Read/Write 0x00000100 0x0004 Device Global Interrupt Register UDINT Read-Only 0x00000000 0x0008 Device Global Interrupt Clear Register UDINTCLR Write-Only 0x00000000 0x000C Device Global Interrupt Set Register...
Page 666 AT32UC3A3 Table 27-4. USBB Register Memory Map Offset Register Name Access Reset Value 0x0198 Endpoint 2 Status Set Register UESTA2SET Write-Only 0x00000000 0x019C Endpoint 3 Status Set Register UESTA3SET Write-Only 0x00000000 0x01A0 Endpoint 4 Status Set Register UESTA4SET Write-Only 0x00000000 0x01A4 Endpoint 5 Status Set Register UESTA5SET...
Page 667 AT32UC3A3 Table 27-4. USBB Register Memory Map Offset Register Name Access Reset Value UDDMA1 0x031C Device DMA Channel 1 Status Register Read/Write 0x00000000 STATUS Device DMA Channel 2 Next Descriptor UDDMA2 0x0320 Read/Write 0x00000000 Address Register NEXTDESC UDDMA2 0x0324 Device DMA Channel 2 HSB Address Register Read/Write 0x00000000 ADDR...
Page 668 AT32UC3A3 Table 27-4. USBB Register Memory Map Offset Register Name Access Reset Value UDDMA7 0x0374 Device DMA Channel 7 HSB Address Register Read/Write 0x00000000 ADDR UDDMA7 0x0378 Device DMA Channel 7 Control Register Read/Write 0x00000000 CONTROL UDDMA7 0x037C Device DMA Channel 7Status Register Read/Write 0x00000000 STATUS...
Page 669 AT32UC3A3 Table 27-4. USBB Register Memory Map Offset Register Name Access Reset Value 0x0570 Pipe 4 Status Clear Register UPSTA4CLR Write-Only 0x00000000 0x0574 Pipe 5 Status Clear Register UPSTA5CLR Write-Only 0x00000000 0x0578 Pipe 6 Status Clear Register UPSTA6CLR Write-Only 0x00000000 0x057C Pipe 7 Status Clear Register UPSTA7CLR...
Page 670 AT32UC3A3 Table 27-4. USBB Register Memory Map Offset Register Name Access Reset Value 0x0650 Pipe 0 IN Request Register UPINRQ0 Read/Write 0x00000000 0x0654 Pipe 1 IN Request Register UPINRQ1 Read/Write 0x00000000 0x0658 Pipe 2 IN Request Register UPINRQ2 Read/Write 0x00000000 0x065C Pipe 3 IN Request Register UPINRQ3...
Page 671 AT32UC3A3 Table 27-4. USBB Register Memory Map Offset Register Name Access Reset Value Host DMA Channel 4 Next Descriptor Address UHDMA4 0x0740 Read/Write 0x00000000 Register NEXTDESC UHDMA4 0x0744 Host DMA Channel 4 HSB Address Register Read/Write 0x00000000 ADDR UHDMA4 0x0748 Host DMA Channel 4 Control Register Read/Write 0x00000000...
Page 672 AT32UC3A3 Table 27-5. USB HSB Memory Map Offset Register Name Access Reset Value 0x00000 - Pipe/Endpoint 0 FIFO Data Register Read/Write Undefined 0x0FFFC FIFO0DATA 0x10000 - Pipe/Endpoint 1 FIFO Data Register Read/Write Undefined 0x1FFFC FIFO1DATA 0x20000 - Pipe/Endpoint 2 FIFO Data Register Read/Write Undefined 0x2FFFC...
Page 673 AT32UC3A3 27.8.1 USB General Registers 27.8.1.1 General Control Register Name: USBCON Access Type: Read/Write Offset: 0x0800 Reset Value: 0x03004000 UIMOD UIDE UNLOCK TIMPAGE TIMVALUE USBE FRZCLK VBUSPO OTGPADE VBUSHWC STOE ROLEEXE BCERRE VBERRE VBUSTE IDTE • UIMOD: USBB Mode This bit has no effect when UIDE is one (USB_ID input pin activated). 0: The module is in USB host mode.
Page 674 AT32UC3A3 This bit can be written even if FRZCLK is one. • FRZCLK: Freeze USB Clock 1: The clock input are disabled (the resume detection is still active).This reduces power consumption. Unless explicitly stated, all registers then become read-only. 0: The clock inputs are enabled. This bit can be written even if USBE is zero.
Page 675 AT32UC3A3 27.8.1.2 General Status Register Register Name: USBSTA Access Type: Read-Only Offset: 0x0804 Reset Value: 0x00000400 CLKUSABLE SPEED VBUS VBUSRQ STOI ROLEEXI BCERRI VBERRI VBUSTI IDTI • CLKUSABLE: UTMI Clock Usable This bit is set when the UTMI 30MHz is usable. This bit is cleared when the UTMI 30MHz is not usable.
Page 676 AT32UC3A3 • STOI: Suspend Time-Out Interrupt This bit is set when a time-out error (more than 200ms) has been detected after a suspend. This triggers a USB interrupt if STOE is one. This bit is cleared when the UBSTACLR.STOIC bit is written to one. This bit shall only be used in host mode.
Page 677 AT32UC3A3 27.8.1.3 General Status Clear Register Register Name: USBSTACLR Access Type: Write-Only Offset: 0x0808 Read Value: 0x00000000 VBUSRQC STOIC ROLEEXIC BCERRIC VBERRIC VBUSTIC IDTIC Writing a one to a bit in this register will clear the corresponding bit in UBSTA. Writing a zero to a bit in this register has no effect.
Page 678 AT32UC3A3 27.8.1.4 General Status Set Register Register Name: USBSTASET Access Type: Write-Only Offset: 0x080C Read Value: 0x00000000 VBUSRQS STOIS ROLEEXIS BCERRIS VBERRIS VBUSTIS IDTIS Writing a one to a bit in this register will set the corresponding bit in UBSTA, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect.
Page 679 AT32UC3A3 27.8.1.5 Version Register Register Name: UVERS Access Type: Read-Only Offset: 0x0818 Read Value: VARIANT VERSION[11:8] VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32072H–AVR32–10/2012...
Page 680 AT32UC3A3 27.8.1.6 Features Register Register Name: UFEATURES Access Type: Read-Only Offset: 0x081C Read Value: ENHBISO7 ENHBISO6 ENHBISO5 ENHBISO4 ENHBISO3 ENHBISO2 ENHBISO1 DATABUS BYTEWRITE FIFOMAXSIZE DMAFIFOWORDDEPTH DPRAM DMABUFFE DMACHANNELNBR EPTNBRMAX RSIZE • ENHBISOn: High Bandwidth Isochronous Feature for Endpoint n 1: The high bandwidth isochronous is supported. 0: The high bandwidth isochronous is not supported.
Page 681 AT32UC3A3 • DMAFIFOWORDDEPTH: DMA FIFO Depth in Words This field indicates the DMA FIFO depth controller in words: DMAFIFOWORDDEPTH DMA FIFO Depth in Words • DMABUFFERSIZE: DMA Buffer Size 1: The DMA buffer size is 24bits. 0: The DMA buffer size is 16bits. •...
Page 682 AT32UC3A3 27.8.1.7 Address Size Register Register Name: UADDRSIZE Access Type: Read-Only Offset: 0x0820 Read Value: UADDRSIZE[31:24] UADDRSIZE[23:16] UADDRSIZE[15:8] UADDRSIZE[7:0] • UADDRSIZE: IP PB Address Size This field indicates the size of the PB address space reserved for the USBB IP interface. 32072H–AVR32–10/2012...
Page 683 AT32UC3A3 27.8.1.8 Name Register 1 Register Name: UNAME1 Access Type: Read-Only Offset: 0x0824 Read Value: UNAME1[31:24] UNAME1[23:16] UNAME1[15:8] UNAME1[7:0] • UNAME1: IP Name Part One This field indicates the first part of the ASCII-encoded name of the USBB IP. 32072H–AVR32–10/2012...
Page 684 AT32UC3A3 27.8.1.9 Name Register 2 Register Name: UNAME2 Access Type: Read-Only Offset: 0x0828 Read Value: UNAME2[31:24] UNAME2[23:16] UNAME2[15:8] UNAME2[7:0] • UNAME2: IP Name Part Two This field indicates the second part of the ASCII-encoded name of the USBB IP. 32072H–AVR32–10/2012...
Page 685 AT32UC3A3 27.8.1.10 Finite State Machine Status Register Register Name: USBFSM Access Type: Read-Only Offset: 0x082C Read Value: 0x00000009 DRDSTATE • DRDSTATE This field indicates the state of the USBB. DRDSTATE Description a_idle state: this is the start state for A-devices (when the ID pin is 0) a_wait_vrise: In this state, the A-device waits for the voltage on VBus to rise above the A- device VBus Valid threshold (4.4 V).
Page 686 AT32UC3A3 DRDSTATE Description b_wait_acon: In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. b_host: In this state, the B-device acts as the Host. b_srp_init: In this state, the B-device attempts to start a session using the SRP protocol. 32072H–AVR32–10/2012...
Page 687 AT32UC3A3 27.8.2 USB Device Registers 27.8.2.1 Device General Control Register Register Name: UDCON Access Type: Read/Write Offset: 0x0000 Reset Value: 0x00000100 OPMODE2 TSTPCKT TSTK TSTJ SPDCONF RMWKUP DETACH ADDEN UADD • OPMODE2: Specific Operational mode 1: The UTMI transceiver is in the «disable bit stuffing and NRZI encoding» operational mode for test purpose. 0: The UTMI transceiver is in normal operation mode.
Page 688 AT32UC3A3 • SPDCONF: Speed Configuration This field contains the peripheral speed. SPDCONF Speed Normal mode: the peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. reserved, do not use this configuration reserved, do not use this configuration Full-speed: the peripheral remains in full-speed mode whatever is the host speed capability.
Page 689 AT32UC3A3 27.8.2.2 Device Global Interrupt Register Register Name: UDINT Access Type: Read-Only Offset: 0x0004 Reset Value: 0x00000000 DMA7INT DMA6INT DMA5INT DMA4INT DMA3INT DMA2INT DMA1INT EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT UPRSM EORSM WAKEUP EORST MSOF SUSP • DMAnINT: DMA Channel n Interrupt This bit is set when an interrupt is triggered by the DMA channel n.
Page 690 AT32UC3A3 • SOF: Start of Frame Interrupt This bit is set when a USB “Start of Frame” PID (SOF) has been detected (every 1 ms). This triggers a USB interrupt if SOFE is one. The FNUM field is updated. In High-speed mode, the MFNUM field is cleared. This bit is cleared when the UDINTCLR.SOFC bit is written to one to acknowledge the interrupt.
Page 691 AT32UC3A3 27.8.2.3 Device Global Interrupt Clear Register Register Name: UDINTCLR Access Type: Write-Only Offset: 0x0008 Read Value: 0x00000000 UPRSMC EORSMC WAKEUPC EORSTC SOFC MSOFC SUSPC Writing a one to a bit in this register will clear the corresponding bit in UDINT. Writing a zero to a bit in this register has no effect.
Page 692 AT32UC3A3 27.8.2.4 Device Global Interrupt Set Register Register Name: UDINTSET Access Type: Write-Only Offset: 0x000C Read Value: 0x00000000 DMA7INTS DMA6INTS DMA5INTS DMA4INTS DMA3INTS DMA2INTS DMA1INTS UPRSMS EORSMS WAKEUPS EORSTS SOFS MSOFS SUSPS Writing a one to a bit in this register will set the corresponding bit in UDINT, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect.
Page 693 AT32UC3A3 27.8.2.5 Device Global Interrupt Enable Register Register Name: UDINTE Access Type: Read-Only Offset: 0x0010 Reset Value: 0x00000000 DMA7INTE DMA6INTE DMA5INTE DMA4INTE DMA3INTE DMA2INTE DMA1INTE EP7INTE EP6INTE EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE EP0INTE UPRSME EORSME WAKEUPE EORSTE SOFE MSOFE SUSPE 1: The corresponding interrupt is enabled.
Page 694 AT32UC3A3 27.8.2.6 Device Global Interrupt Enable Clear Register Register Name: UDINTECLR Access Type: Write-Only Offset: 0x0014 Read Value: 0x00000000 DMA7INTEC DMA6INTEC DMA5INTEC DMA4INTEC DMA3INTEC DMA2INTEC DMA1INTEC EP7INTEC EP6INTEC EP5INTEC EP4INTEC EP3INTEC EP2INTEC EP1INTEC EP0INTEC UPRSMEC EORSMEC WAKEUPEC EORSTEC SOFEC MSOFEC SUSPEC Writing a one to a bit in this register will clear the corresponding bit in UDINTE.
Page 695 AT32UC3A3 27.8.2.7 Device Global Interrupt Enable Set Register Register Name: UDINTESET Access Type: Write-Only Offset: 0x0018 Read Value: 0x00000000 DMA7INTES DMA6INTES DMA5INTES DMA4INTES DMA3INTES DMA2INTES DMA1INTES EP7INTES EP6INTES EP5INTES EP4INTES EP3INTES EP2INTES EP1INTES EP0INTES UPRSMES EORSMES WAKEUPES EORSTES SOFES MSOFES SUSPES Writing a one to a bit in this register will set the corresponding bit in UDINTE.
Page 696 AT32UC3A3 27.8.2.8 Endpoint Enable/Reset Register Register Name: UERST Access Type: Read/Write Offset: 0x001C Reset Value: 0x00000000 EPRST7 EPRST6 EPRST5 EPRST4 EPRST3 EPRST2 EPRST1 EPRST0 EPEN7 EPEN6 EPEN5 EPEN4 EPEN3 EPEN2 EPEN1 EPEN0 • EPRSTn: Endpoint n Reset Writing a one to this bit will reset the endpoint n FIFO prior to any other operation, upon hardware reset or when a USB bus reset has been received.
Page 697 AT32UC3A3 27.8.2.9 Device Frame Number Register Register Name: UDFNUM Access Type: Read-Only Offset: 0x0020 Reset Value: 0x00000000 FNCERR FNUM[10:5] FNUM[4:0] MFNUM • FNCERR: Frame Number CRC Error This bit is set when a corrupted frame number (or micro-frame number) is received. This bit and the SOF (or MSOF) interrupt bit are updated at the same time.
Page 698 AT32UC3A3 27.8.2.10 Endpoint n Configuration Register Register Name: UECFGn, n in [0..7] Access Type: Read/Write Offset: 0x0100 + (n * 0x04) Reset Value: 0x00000000 NBTRANS EPTYPE AUTOSW EPDIR EPSIZE EPBK ALLOC • NBTRANS: Number of transaction per microframe for isochronous endpoint This field shall be written to the number of transaction per microframe to perform high-bandwidth isochronous transfer This field can be written only for endpoint that have this capability (see UFEATURES register, ENHBISOn bit).
Page 699 AT32UC3A3 • AUTOSW: Automatic Switch This bit is cleared upon receiving a USB reset. 1: The automatic bank switching is enabled. 0: The automatic bank switching is disabled. • EPDIR: Endpoint Direction This bit is cleared upon receiving a USB reset. 1: The endpoint direction is IN (nor for control endpoints).
Page 700 AT32UC3A3 27.8.2.11 Endpoint n Status Register Register Name: UESTAn, n in [0..7] Access Type: Read-Only 0x0100 Offset: 0x0130 + (n * 0x04) Reset Value: 0x00000100 BYCT BYCT CFGOK CTRLDIR RWALL CURRBK NBUSYBK DTSEQ ERRORTRANS SHORT STALLEDI/ NAKINI/ NAKOUTI/ RXSTPI/ OVERFI RXOUTI TXINI PACKET...
Page 701 AT32UC3A3 • CURRBK: Current Bank This bit is set for non-control endpoints, to indicate the current bank: CURRBK Current Bank Bank0 Bank1 (see Table 27-1 on page 624). Bank2 if supported Reserved This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit. •...
Page 702 AT32UC3A3 For OUT transfers, this value indicates the last data toggle sequence received on the current bank. By default DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence should be Data0.
Page 703 AT32UC3A3 An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then automatically sent by the USBB. An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not fast enough.
Page 704 AT32UC3A3 27.8.2.12 Endpoint n Status Clear Register Register Name: UESTAnCLR, n in [0..7] Access Type: Write-Only Offset: 0x0160 + (n * 0x04) Read Value: 0x00000000 SHORT STALLEDIC/ NAKINIC/ NAKOUTIC/ RXSTPIC/ OVERFIC RXOUTIC TXINIC PACKETC CRCERRIC UNDERFIC HBISOFLUSHIC HBISOINERRIC Writing a one to a bit in this register will clear the corresponding bit in UESTA. Writing a zero to a bit in this register has no effect.
Page 705 AT32UC3A3 27.8.2.13 Endpoint n Status Set Register Register Name: UESTAnSET, n in [0..7] Access Type: Write-Only Offset: 0x0190 + (n * 0x04) Read Value: 0x00000000 NBUSYBKS SHORT STALLEDIS/ NAKINIS/ NAKOUTIS/ RXSTPIS/ OVERFIS RXOUTIS TXINIS PACKETS CRCERRIS UNDERFIS HBISOFLUSHIS HBISOINERRIS Writing a one to a bit in this register will set the corresponding bit in UESTA, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect.
Page 706 AT32UC3A3 27.8.2.14 Endpoint n Control Register Register Name: UECONn, n in [0..7] Access Type: Read-Only Offset: 0x01C0 + (n * 0x04) Reset Value: 0x00000000 STALLRQ RSTDT NYETDIS EPDISHDMA FIFOCON KILLBK NBUSYBKE DATAXE MDATAE ERRORTRANSE SHORT STALLEDE/ NAKINE/ NAKOUTE/ RXSTPE/ OVERFE RXOUTE TXINE PACKETE...
Page 707 AT32UC3A3 • FIFOCON: FIFO Control For control endpoints: The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints. When read, their value is always 0. For IN endpoints: This bit is set when the current bank is free, at the same time as TXINI. This bit is cleared (by writing a one to the FIFOCONC bit) to send the FIFO data and to switch to the next bank.
Page 708 AT32UC3A3 This bit is cleared when the HBISOFLUSHEC bit disable the HBISOFLUSHI interrupt. Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device. • NAKOUTE: NAKed OUT Interrupt Enable This bit is set when the NAKOUTES bit is written to one. This will enable the NAKed OUT interrupt (NAKOUTI). This bit is cleared when the NAKOUTEC bit is written to one.
Page 709 AT32UC3A3 27.8.2.15 Endpoint n Control Clear Register Register Name: UECONnCLR, n in [0..7] Access Type: Write-Only Offset: 0x0220 + (n * 0x04) Read Value: 0x00000000 STALLRQC NYETDISC EPDISHDMAC FIFOCONC NBUSYBKEC DATAXEC MDATEC ERRORTRANSEC SHORT STALLEDEC/ NAKINEC/ NAKOUTEC/ RXSTPEC/ OVERFEC RXOUTEC TXINEC PACKETEC CRCERREC...
Page 710 AT32UC3A3 27.8.2.16 Endpoint n Control Set Register Register Name: UECONnSET, n in [0..7] Access Type: Write-Only Offset: 0x01F0 + (n * 0x04) Read Value: 0x00000000 STALLRQS RSTDTS NYETDISS EPDISHDMAS KILLBKS DATAXES MDATES NBUSYBKES ERRORTRANSES SHORT STALLEDES/ NAKINES/ NAKOUTES/ RXSTPES/ OVERFES RXOUTES TXINES PACKETES...
Page 711 AT32UC3A3 27.8.2.17 Device DMA Channel n Next Descriptor Address Register Register Name: UDDMAnNEXTDESC, n in [1..7] Access Type: Read/Write Offset: 0x0310 + (n - 1) * 0x10 Reset Value: 0x00000000 NXTDESCADDR[31:24] NXTDESCADDR[23:16] NXTDESCADDR[15:8] NXTDESCADDR[7:4] • NXTDESCADDR: Next Descriptor Address This field contains the bits 31:4 of the 16-byte aligned address of the next channel descriptor to be processed. This field is written either or by descriptor loading.
Page 712 AT32UC3A3 27.8.2.18 Device DMA Channel n HSB Address Register Register Name: UDDMAnADDR, n in [1..7] Access Type: Read/Write Offset: 0x0314 + (n - 1) * 0x10 Reset Value: 0x00000000 HSBADDR[31:24] HSBADDR[23:16] HSBADDR[15:8] HSBADDR[7:0] • HSBADDR: HSB Address This field determines the HSB bus current address of a channel transfer. The address written to the HSB address bus is HSBADDR rounded down to the nearest word-aligned address, i.e., HSBADDR[1:0] is considered as 0b00 since only word accesses are performed.
Page 713 AT32UC3A3 27.8.2.19 Device DMA Channel n Control Register Register Name: UDDMAnCONTROL, n in [1..7] Access Type: Read/Write Offset: 0x0318 + (n - 1) * 0x10 Reset Value: 0x00000000 CHBYTELENGTH[15:8] CHBYTELENGTH[7:0] LDNXTCH BUFFCLOSE EOTIRQEN DMAENDEN CHEN BURSTLOCKEN DESCLDIRQEN EOBUFFIRQEN INEN DESCEN •...
Page 714 AT32UC3A3 • BUFFCLOSEINEN: Buffer Close Input Enable For Bulk and Interrupt endpoint, writing a one to this bit will automatically close the current DMA transfer at the end of the USB OUT data transfer (received short packet). For Full-speed Isochronous, it does not make sense, so BUFFCLOSEINEN should be left to zero. For high-speed OUT isochronous, it may make sense.
Page 715 AT32UC3A3 27.8.2.20 Device DMA Channel n Status Register Register Name: UDDMAnSTATUS, n in [1..7] Access Type: Read/Write Offset: 0x031C + (n - 1) * 0x10 Reset Value: 0x00000000 CHBYTECNT[15:8] CHBYTECNT[7:0] DESCLD EOCHBUFF EOTSTA CHACTIVE CHEN • CHBYTECNT: Channel Byte Count This field contains the current number of bytes still to be transferred for this buffer.
Page 716 AT32UC3A3 0: the DMA channel no longer transfers data, and may load the next descriptor if the UDDMAnCONTROL.LDNXTCHDESCEN bit is zero. 1: the DMA channel is currently enabled and transfers data upon request. If a channel request is currently serviced when the UDDMAnCONTROL.CHEN bit is written to zero, the DMA FIFO buffer is drained until it is empty, then this status bit is cleared.
Page 717 AT32UC3A3 27.8.3 USB Host Registers 27.8.3.1 Host General Control Register Register Name: UHCON Access Type: Read/Write Offset: 0x0400 Reset Value: 0x00000000 SPDCONF RESUME RESET SOFE • SPDCONF: Speed Configuration This field contains the host speed capability. SPDCONF Speed Normal mode: the host start in full-speed mode and perform a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable.
Page 718 AT32UC3A3 27.8.3.2 Host Global Interrupt Register Register Name: UHINT Access Type: Read-Only Offset: 0x0404 Reset Value: 0x00000000 DMA7INT DMA6INT DMA5INT DMA4INT DMA3INT DMA2INT DMA1INT P7INT P6INT P5INT P4INT P3INT P2INT P1INT P0INT HWUPI HSOFI RXRSMI RSMEDI RSTI DDISCI DCONNI • DMAnINT: DMA Channel n Interrupt This bit is set when an interrupt is triggered by the DMA channel n.
Page 719 AT32UC3A3 • DDISCI: Device Disconnection Interrupt This bit is set when the device has been removed from the USB bus. This bit is cleared when the DDISCIC bit is written to one. • DCONNI: Device Connection Interrupt This bit is set when a new device has been connected to the USB bus. This bit is cleared when the DCONNIC bit is written to one.
Page 720 AT32UC3A3 27.8.3.3 Host Global Interrupt Clear Register Register Name: UHINTCLR Access Type: Write-Only Offset: 0x0408 Read Value: 0x00000000 HWUPIC HSOFIC RXRSMIC RSMEDIC RSTIC DDISCIC DCONNIC Writing a one to a bit in this register will clear the corresponding bit in UHINT. Writing a zero to a bit in this register has no effect.
Page 721 AT32UC3A3 27.8.3.4 Host Global Interrupt Set Register Register Name: UHINTSET Access Type: Write-Only Offset: 0x040C Read Value: 0x00000000 DMA7INTS DMA6INTS DMA5INTS DMA4INTS DMA3INTS DMA2INTS DMA1INTS HWUPIS HSOFIS RXRSMIS RSMEDIS RSTIS DDISCIS DCONNIS Writing a one to a bit in this register will set the corresponding bit in UHINT, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect.
Page 722 AT32UC3A3 27.8.3.5 Host Global Interrupt Enable Register Register Name: UHINTE Access Type: Read-Only Offset: 0x0410 Reset Value: 0x00000000 DMA7INTE DMA6INTE DMA5INTE DMA4INTE DMA3INTE DMA2INTE DMA1INTE P7INTE P6INTE P5INTE P4INTE P3INTE P2INTE P1INTE P0INTE HWUPIE HSOFIE RXRSMIE RSMEDIE RSTIE DDISCIE DCONNIE •...
Page 723 AT32UC3A3 27.8.3.6 Host Global Interrupt Enable Clear Register Register Name: UHINTECLR Access Type: Write-Only Offset: 0x0414 Read Value: 0x00000000 DMA7INTEC DMA6INTEC DMA5INTEC DMA4INTEC DMA3INTEC DMA2INTEC DMA1INTEC P7INTEC P6INTEC P5INTEC P4INTEC P3INTEC P2INTEC P1INTEC P0INTEC HWUPIEC HSOFIEC RXRSMIEC RSMEDIEC RSTIEC DDISCIEC DCONNIEC Writing a one to a bit in this register will clear the corresponding bit in UHINTE.
Page 724 AT32UC3A3 27.8.3.7 Host Global Interrupt Enable Set Register Register Name: UHINTESET Access Type: Write-Only Offset: 0x0418 Read Value: 0x00000000 DMA7INTES DMA6INTES DMA5INTES DMA4INTES DMA3INTES DMA2INTES DMA1INTES P7INTES P6INTES P5INTES P4INTES P3INTES P2INTES P1INTES P0INTES HWUPIES HSOFIES RXRSMIES RSMEDIES RSTIES DDISCIES DCONNIES Writing a one to a bit in this register will set the corresponding bit in UHINT.
Page 725 AT32UC3A3 27.8.3.8 Host Frame Number Register Register Name: UHFNUM Access Type: Read/Write Offset: 0x0420 Reset Value: 0x00000000 FLENHIGH FNUM[10:5] FNUM[4:0] MFNUM • FLENHIGH: Frame Length In Full speed mode, this field contains the 8 high-order bits of the 16-bit internal frame counter (at 30MHz, counter length is 30000 to ensure a SOF generation every 1 ms).
Page 726 AT32UC3A3 27.8.3.9 Host Address 1 Register Register Name: UHADDR1 Access Type: Read/Write Offset: 0x0424 Reset Value: 0x00000000 UHADDRP3 UHADDRP2 UHADDRP1 UHADDRP0 • UHADDRP3: USB Host Address This field contains the address of the Pipe3 of the USB Device. This field is cleared when a USB reset is requested. •...
Page 727 AT32UC3A3 27.8.3.10 Host Address 2 Register Register Name: UHADDR2 Access Type: Read/Write Offset: 0x0428 Reset Value: 0x00000000 UHADDRP7 UHADDRP6 UHADDRP5 UHADDRP4 • UHADDRP7: USB Host Address This field contains the address of the Pipe7 of the USB Device. This field is cleared when a USB reset is requested. •...
Page 728 AT32UC3A3 27.8.3.11 Pipe Enable/Reset Register Register Name: UPRST Access Type: Read/Write Offset: 0x0041C Reset Value: 0x00000000 PRST7 PRST6 PRST5 PRST4 PRST3 PRST2 PRST1 PRST0 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0 • PRSTn: Pipe n Reset Writing a one to this bit will reset the Pipe n FIFO. This resets the endpoint n registers (UPCFGn, UPSTAn, UPCONn) but not the endpoint configuration (ALLOC, PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ).
Page 729 AT32UC3A3 27.8.3.12 Pipe n Configuration Register Register Name: UPCFGn, n in [0..7] Access Type: Read/Write Offset: 0x0500 + (n * 0x04) Reset Value: 0x00000000 INTFRQ/BINTERVAL PINGEN PEPNUM PTYPE AUTOSW PTOKEN PSIZE ALLOC • INTFRQ: Pipe Interrupt Request Frequency This field contains the maximum value in millisecond of the polling period for an Interrupt Pipe. This value has no effect for a non-Interrupt Pipe.
Page 730 AT32UC3A3 PTYPE Pipe Type Isochronous Bulk Interrupt This field is cleared upon sending a USB reset. • AUTOSW: Automatic Switch This bit is cleared upon sending a USB reset. 1: The automatic bank switching is enabled. 0: The automatic bank switching is disabled. •...
Page 731 AT32UC3A3 • ALLOC: Pipe Memory Allocate Writing a one to this bit will allocate the pipe memory. Writing a zero to this bit will free the pipe memory. This bit is cleared when a USB Reset is requested. Refer to the DPRAM Management chapter for more details. 32072H–AVR32–10/2012...
Page 732 AT32UC3A3 27.8.3.13 Pipe n Status Register Register Name: UPSTAn, n in [0..7] Access Type: Read-Only Offset: 0x0530 + (n * 0x04) Reset Value: 0x00000000 PBYCT[10:4] PBYCT[3:0] CFGOK RWALL CURRBK NBUSYBK DTSEQ SHORT RXSTALLDI/ TXSTPI/ OVERFI NAKEDI PERRI TXOUTI RXINI PACKETI CRCERRI UNDERFI •...
Page 733 AT32UC3A3 CURRBK Current Bank Bank1 (see Table 27-1 on page 624). Bank2 if supported Reserved This field may be updated 1 clock cycle after the RWALL bit changes, so the user shall not poll this field as an interrupt bit. •...
Page 734 AT32UC3A3 This bit is cleared when the NAKEDIC bit written to one. • PERRI: Pipe Error Interrupt This bit is set when an error occurs on the current bank of the pipe. This triggers an interrupt if the PERRE bit is set. Refers to the UPERRn register to determine the source of the error.
Page 735 AT32UC3A3 27.8.3.14 Pipe n Status Clear Register Register Name: UPSTAnCLR, n in [0..7] Access Type: Write-Only Offset: 0x0560 + (n * 0x04) Read Value: 0x00000000 RXSTALLDI SHORT TXSTPIC/ OVERFIC NAKEDIC TXOUTIC RXINIC PACKETIC UNDERFIC CRCERRIC Writing a one to a bit in this register will clear the corresponding bit in UPSTAn. Writing a zero to a bit in this register has no effect.
Page 736 AT32UC3A3 27.8.3.15 Pipe n Status Set Register Register Name: UPSTAnSET, n in [0..7] Access Type: Write-Only Offset: 0x0590 + (n * 0x04) Read Value: 0x00000000 NBUSYBKS SHORT TXSTPIS/ RXSTALLDIS OVERFIS NAKEDIS PERRIS TXOUTIS RXINIS PACKETIS CRCERRIS UNDERFIS Writing a one to a bit in this register will set the corresponding bit in UPSTAn, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect.
Page 737 AT32UC3A3 27.8.3.16 Pipe n Control Register Register Name: UPCONn, n in [0..7] Access Type: Read-Only Offset: 0x05C0 + (n * 0x04) Reset Value: 0x00000000 RSTDT PFREEZE PDISHDMA FIFOCON NBUSYBKE SHORT RXSTALLDE/ TXSTPE/ OVERFIE NAKEDE PERRE TXOUTE RXINE PACKETIE CRCERRE UNDERFIE •...
Page 738 AT32UC3A3 • RXSTALLDE: Received STALLed Interrupt Enable This bit is set when the RXSTALLDES bit is written to one. This will enable the Transmitted IN Data interrupt (RXSTALLDE). This bit is cleared when the RXSTALLDEC bit is written to one. This will disable the Transmitted IN Data interrupt (RXSTALLDE).
Page 739 AT32UC3A3 27.8.3.17 Pipe n Control Clear Register Register Name: UPCONnCLR, n in [0..7] Access Type: Write-Only Offset: 0x0620 + (n * 0x04) Read Value: 0x00000000 PFREEZEC PDISHDMAC FIFOCONC NBUSYBKEC SHORT TXSTPEC/ RXSTALLDEC OVERFIEC NAKEDEC PERREC TXOUTEC RXINEC CRCERREC UNDERFIEC PACKETIEC Writing a one to a bit in this register will clear the corresponding bit in UPCONn.
Page 740 AT32UC3A3 27.8.3.18 Pipe n Control Set Register Register Name: UPCONnSET, n in [0..7] Access Type: Write-Only Offset: 0x05F0 + (n * 0x04) Read Value: 0x00000000 RSTDTS PFREEZES PDISHDMAS NBUSYBKES SHORT TXSTPES/ RXSTALLDES OVERFIES NAKEDES PERRES TXOUTES RXINES CRCERRES UNDERFIES PACKETIES Writing a one to a bit in this register will set the corresponding bit in UPCONn.
Page 741 AT32UC3A3 27.8.3.19 Pipe n IN Request Register Register Name: UPINRQn, n in [0..7] Access Type: Read/Write Offset: 0x0650 + (n * 0x04) Reset Value: 0x00000000 INMODE INRQ • INMODE: IN Request Mode Writing a one to this bit will allow the USBB to perform infinite IN requests when the Pipe is not frozen. Writing a zero to this bit will perform a pre-defined number of IN requests.
Page 742 AT32UC3A3 27.8.3.20 Pipe n Error Register Register Name: UPERRn, n in [0..7] Access Type: Read/Write Offset: 0x0680 + (n * 0x04) Reset Value: 0x00000000 COUNTER CRC16 TIMEOUT DATAPID DATATGL • COUNTER: Error Counter This field is incremented each time an error occurs (CRC16, TIMEOUT, PID, DATAPID or DATATGL). This field is cleared when receiving a good usb packet without any error.
Page 743 AT32UC3A3 27.8.3.21 Host DMA Channel n Next Descriptor Address Register Register Name: UHDMAnNEXTDESC, n in [1..7] Access Type: Read/Write Offset: 0x0710 + (n - 1) * 0x10 Reset Value: 0x00000000 NXTDESCADDR[31:24] NXTDESCADDR[23:16] NXTDESCADDR[15:8] NXTDESCADDR[7:4] Same as Section 27.8.2.17. 32072H–AVR32–10/2012...
Page 744 AT32UC3A3 27.8.3.22 Host DMA Channel n HSB Address Register Register Name: UHDMAnADDR, n in [1..7] Access Type: Read/Write Offset: 0x0714 + (n - 1) * 0x10 Reset Value: 0x00000000 HSBADDR[31:24] HSBADDR[23:16] HSBADDR[15:8] HSBADDR[7:0] Same as Section 27.8.2.18. 32072H–AVR32–10/2012...
Page 745 AT32UC3A3 27.8.3.23 USB Host DMA Channel n Control Register Register Name: UHDMAnCONTROL, n in [1..7] Access Type: Read/Write Offset: 0x0718 + (n - 1) * 0x10 Reset Value: 0x00000000 CHBYTELENGTH[15:8] CHBYTELENGTH[7:0] BURSTLOC DESCLD EOBUFF BUFFCLOSE LDNXTCHD EOTIRQEN DMAENDEN CHEN IRQEN IRQEN INEN ESCEN...
Page 746 AT32UC3A3 27.8.3.24 USB Host DMA Channel n Status Register Register Name: UHDMAnSTATUS, n in [1..7] Access Type: Read/Write Offset: 0x071C + (n - 1) * 0x10 Reset Value: 0x00000000 CHBYTECNT[15:8] CHBYTECNT[7:0] DESCLD EOCHBUFFS EOTSTA CHACTIVE CHEN Same as Section 27.8.2.20. 32072H–AVR32–10/2012...
Page 747 AT32UC3A3 27.8.4 USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA) The application has access to the physical DPRAM reserved for the Endpoint/Pipe through a 64KB virtual address space. The application can access anywhere in the virtual 64KB segment (linearly or fixedly) as the DPRAM Fifo address increment is fully handled by hardware. Byte, half-word and word access are supported.
Page 748 AT32UC3A3 27.9 Module Configuration The specific configuration for the USBB instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 27-7. Module Clock Name Module name Clock name...
Page 749 AT32UC3A3 28. Timer/Counter (TC) Rev: 2.2.3.3 28.1 Features • Three 16-bit Timer Counter channels • A wide range of functions including: – Frequency measurement – Event counting – Interval measurement – Pulse generation – Delay timing – Pulse width modulation –...
Page 750 AT32UC3A3 28.3 Block Diagram Figure 28-1. TC Block Diagram TIMER_CLOCK1 Contr oller CLK0 TCLK0 CLK1 TIMER_CLOCK2 TIOA1 CLK2 TIOA2 Timer/Counter TIMER_CLOCK3 TIOA Channel 0 TCLK1 TIOA0 TIOB TIMER_CLOCK4 TCLK2 TIOB0 TIMER_CLOCK5 TC0XC0S SYNC INT0 TCLK0 TCLK1 Timer/Counter TIOA Channel 1 TIOA0 TIOA1 TIOB...
Page 751 AT32UC3A3 28.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning and resume operation after the system wakes up from sleep mode. 28.5.3 Clocks The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager.
Page 752 AT32UC3A3 28.6.1.3 Clock selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals A0, A1 or A2 for chaining by writing to the BMR register. See Figure 28-2 on page 752.
Page 753 AT32UC3A3 • The clock can be enabled or disabled by the user by writing to the Counter Clock Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter Clock Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS).
Page 754 AT32UC3A3 28.6.1.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: •...
Page 755 AT32UC3A3 28.6.2.2 Trigger conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trig- ger can be defined. The TIOA or TIOB External Trigger Selection bit in CMRn (CMRn.ABETRG) selects TIOA or TIOB input signal as an external trigger. The External Trigger Edge Selection bit in CMRn (CMRn.ETREDG) defines the edge (rising, falling or both) detected to generate an external trig- ger.
Page 756 AT32UC3A3 Figure 28-4. Capture Mode CPCS LOVRS COVFS LDRBS LDRAS ETRGS 32072H–AVR32–10/2012...
Page 757 AT32UC3A3 28.6.3 Waveform Operating Mode Waveform operating mode is entered by writing a one to the CMRn.WAVE bit. In Waveform operating mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one- shot or repetitive pulses.
Page 758 AT32UC3A3 Figure 28-5. Waveform Mode CPCS CPBS CPAS COVFS ETRGS 32072H–AVR32–10/2012...
Page 759 AT32UC3A3 28.6.3.2 WAVSEL = 0 When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and the cycle continues. See Figure 28-6 on page 759.
Page 760 AT32UC3A3 Figure 28-7. WAVSEL= 0 With Trigger Counter cleared by compare match with 0xFFFF Counter Value 0xFFFF Counter cleared by trigger Time Waveform Examples TIOB TIOA 28.6.3.3 WAVSEL = 2 When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC, then automatically reset on a RC Compare.
Page 761 AT32UC3A3 Figure 28-8. WAVSEL = 2 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Time Waveform Examples TIOB TIOA Figure 28-9. WAVSEL = 2 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger Time Waveform Examples...
Page 762 AT32UC3A3 A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 28-11 on page 762.
Page 763 AT32UC3A3 28.6.3.5 WAVSEL = 3 When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See Figure 28-12 on page 763.
Page 764 AT32UC3A3 Figure 28-13. WAVSEL = 3 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC Counter decremented by trigger Counter incremented by trigger Time Waveform Examples TIOB TIOA 28.6.3.6 External event/trigger conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB.
Page 765 AT32UC3A3 • RB Compare Effect on TIOB (CMRn.BCPB) • RC Compare Effect on TIOA (CMRn.ACPC) • RA Compare Effect on TIOA (CMRn.ACPA) 32072H–AVR32–10/2012...
Page 766 AT32UC3A3 28.7 User Interface Table 28-3. TC Register Memory Map Offset Register Register Name Access Reset 0x00 Channel 0 Control Register CCR0 Write-only 0x00000000 0x04 Channel 0 Mode Register CMR0 Read/Write 0x00000000 0x10 Channel 0 Counter Value Read-only 0x00000000 0x14 Channel 0 Register A Read/Write 0x00000000...
Page 767 AT32UC3A3 Notes: 1. Read-only if CMRn.WAVE is zero. 2. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 32072H–AVR32–10/2012...
Page 768 AT32UC3A3 28.7.1 Channel Control Register Name: Access Type: Write-only Offset: 0x00 + n * 0x40 Reset Value: 0x00000000 SWTRG CLKDIS CLKEN • SWTRG: Software Trigger Command 1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started. 0: Writing a zero to this bit has no effect.
Page 769 AT32UC3A3 28.7.2 Channel Mode Register: Capture Mode Name: Access Type: Read/Write Offset: 0x04 + n * 0x40 Reset Value: 0x00000000 LDRB LDRA WAVE CPCTRG ABETRG ETRGEDG LDBDIS LDBSTOP BURST CLKI TCCLKS • LDRB: RB Loading Selection LDRB Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA •...
Page 770 AT32UC3A3 0: TIOB is used as an external trigger. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge none rising edge falling edge each edge • LDBDIS: Counter Clock Disable with RB Loading 1: Counter clock is disabled when RB loading occurs. 0: Counter clock is not disabled when RB loading occurs.
Page 771 AT32UC3A3 28.7.3 Channel Mode Register: Waveform Mode Name: Access Type: Read/Write Offset: 0x04 + n * 0x40 Reset Value: 0x00000000 BSWTRG BEEVT BCPC BCPB ASWTRG AEEVT ACPC ACPA WAVE WAVSEL ENETRG EEVT EEVTEDG CPCDIS CPCSTOP BURST CLKI TCCLKS • BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect none...
Page 772 AT32UC3A3 • BCPC: RC Compare Effect on TIOB BCPC Effect none clear toggle • BCPB: RB Compare Effect on TIOB BCPB Effect none clear toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect none clear toggle • AEEVT: External Event Effect on TIOA AEEVT Effect none...
Page 773 AT32UC3A3 • ACPA: RA Compare Effect on TIOA ACPA Effect none clear toggle • WAVE 1: Waveform mode is enabled. 0: Waveform mode is disabled (Capture mode is enabled). • WAVSEL: Waveform Selection WAVSEL Effect UP mode without automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare...
Page 774 AT32UC3A3 • CPCSTOP: Counter Clock Stopped with RC Compare 1: Counter clock is stopped when counter reaches RC. 0: Counter clock is not stopped when counter reaches RC. • BURST: Burst Signal Selection BURST Burst Signal Selection The clock is not gated by an external signal. XC0 is ANDed with the selected clock.
Page 775 AT32UC3A3 28.7.4 Channel Counter Value Register Name: Access Type: Read-only Offset: 0x10 + n * 0x40 Reset Value: 0x00000000 CV[15:8] CV[7:0] • CV: Counter Value CV contains the counter value in real time. 32072H–AVR32–10/2012...
Page 776 AT32UC3A3 28.7.5 Channel Register A Name: Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x14 + n * 0X40 Reset Value: 0x00000000 RA[15:8] RA[7:0] • RA: Register A RA contains the Register A value in real time. 32072H–AVR32–10/2012...
Page 777 AT32UC3A3 28.7.6 Channel Register B Name: Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x18 + n * 0x40 Reset Value: 0x00000000 RB[15:8] RB[7:0] • RB: Register B RB contains the Register B value in real time. 32072H–AVR32–10/2012...
Page 778 AT32UC3A3 28.7.7 Channel Register C Name: Access Type: Read/Write Offset: 0x1C + n * 0x40 Reset Value: 0x00000000 RC[15:8] RC[7:0] • RC: Register C RC contains the Register C value in real time. 32072H–AVR32–10/2012...
Page 779 AT32UC3A3 28.7.8 Channel Status Register Name: Access Type: Read-only Offset: 0x20 + n * 0x40 Reset Value: 0x00000000 MTIOB MTIOA CLKSTA ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts. •...
Page 780 AT32UC3A3 • CPBS: RB Compare Status 1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • CPAS: RA Compare Status 1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read.
Page 781 AT32UC3A3 28.7.9 Channel Interrupt Enable Register Name: Access Type: Write-only Offset: 0x24 + n * 0x40 Reset Value: 0x00000000 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 782 AT32UC3A3 28.7.10 Channel Interrupt Disable Register Name: Access Type: Write-only Offset: 0x28 + n * 0x40 Reset Value: 0x00000000 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 783 AT32UC3A3 28.7.11 Channel Interrupt Mask Register Name: Access Type: Read-only Offset: 0x2C + n * 0x40 Reset Value: 0x00000000 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one.
Page 784 AT32UC3A3 28.7.12 Block Control Register Name: Access Type: Write-only Offset: 0xC0 Reset Value: 0x00000000 SYNC • SYNC: Synchro Command 1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 0: Writing a zero to this bit has no effect.
Page 785 AT32UC3A3 28.7.13 Block Mode Register Name: Access Type: Read/Write Offset: 0xC4 Reset Value: 0x00000000 TC2XC2S TC1XC1S TC0XC0S • TC2XC2S: External Clock Signal 2 Selection TC2XC2S Signal Connected to XC2 TCLK2 none TIOA0 TIOA1 • TC1XC1S: External Clock Signal 1 Selection TC1XC1S Signal Connected to XC1 TCLK1...
Page 786 AT32UC3A3 • TC0XC0S: External Clock Signal 0 Selection TC0XC0S Signal Connected to XC0 TCLK0 none TIOA1 TIOA2 32072H–AVR32–10/2012...
Page 787 AT32UC3A3 28.7.14 Features Register Name: FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: BRPBHSB UPDNIMPL CTRSIZE • BRPBHSB: Bridge type is PB to HSB 1: Bridge type is PB to HSB. 0: Bridge type is not PB to HSB. • UPDNIMPL: Up/down is implemented 1: Up/down counter capability is implemented.
Page 788 AT32UC3A3 28.7.15 Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: VARIANT VERSION[11:8] VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 32072H–AVR32–10/2012...
Page 789 AT32UC3A3 28.8 Module Configuration The specific configuration for each TC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 28-4. Module Clock Name Module name Clock name...
Page 790 AT32UC3A3 29. Analog-to-Digital Converter (ADC) Rev: 2.0.0.1 29.1 Features • Integrated multiplexer offering up to eight independent analog inputs • Individual enable and disable of each channel • Hardware or software trigger – External trigger pin – Timer counter outputs (corresponding TIOA trigger) •...
Page 791 AT32UC3A3 29.3 Block Diagram Figure 29-1. ADC Block Diagram Timer Counter Channels Trigger ADC Interrupt TRIGGER Selection Interrupt Control Controller Logic VDDANA VREF High Speed Bus (HSB) Peripheral Dedicated Controller Analog Inputs User Peripheral Bridge Interface Successive Approximation Register Analog-to-Digital Analog Inputs Peripheral Bus Converter...
Page 792 AT32UC3A3 29.5.2 Power Management In sleep mode, the ADC clock is automatically stopped after each conversion. As the logic is small and the ADC cell can be put into sleep mode, the Power Manager has no effect on the ADC behavior. 29.5.3 Clocks The clock for the ADC bus interface (CLK_ADC) is generated by the Power Manager.
Page 793 AT32UC3A3 as zero. The two highest bits of the Last Data Converted field in the Last Converted Data Regis- ter (LCDR.LDATA) will be read as zero too. Moreover, when a Peripheral DMA channel is connected to the ADC, a 10-bit resolution sets the transfer request size to 16-bit.
Page 794 AT32UC3A3 If the CDR register is not read before further incoming data is converted, the corresponding Overrun Error bit in the SR register (SR.OVREn) is set. In the same way, new data converted when DRDY is high sets the General Overrun Error bit in the SR register (SR.GOVRE).
Page 795 AT32UC3A3 29.6.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing a one to the START bit in the Control Register (CR.START). The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (TRIGGER).
Page 796 AT32UC3A3 29.6.7 ADC Timings Each ADC has its own minimal startup time that is defined through the Start Up Time field in the Mode Register (MR.STARTUP). This startup time is given in the Electrical Characteristics chapter. In the same way, a minimal sample and hold time is necessary for the ADC to guarantee the best converted final value between two channels selection.
Page 797 AT32UC3A3 29.7 User Interface Table 29-2. ADC Register Memory Map Offset Register Name Access Reset State 0x00 Control Register Write-only 0x00000000 0x04 Mode Register Read/Write 0x00000000 0x10 Channel Enable Register CHER Write-only 0x00000000 0x14 Channel Disable Register CHDR Write-only 0x00000000 0x18 Channel Status Register CHSR...
Page 798 AT32UC3A3 29.7.1 Control Register Name: Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
Page 799 AT32UC3A3 29.7.2 Mode Register Name: Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 – – – – SHTIM – STARTUP PRESCAL – – SLEEP LOWRES TRGSEL TRGEN • SHTIM: Sample & Hold Time Sample & Hold Time = (SHTIM+3) / ADCClock •...
Page 800 AT32UC3A3 29.7.3 Channel Enable Register Name: CHER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – • CHn: Channel n Enable Writing a one to these bits will set the corresponding bit in CHSR.
Page 801 AT32UC3A3 29.7.4 Channel Disable Register Name: CHDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – • CHn: Channel n Disable Writing a one to these bits will clear the corresponding bit in CHSR.
Page 802 AT32UC3A3 29.7.5 Channel Status Register Name: CHSR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – • CHn: Channel n Status These bits are set when the corresponding bits in CHER is written to one.
Page 803 AT32UC3A3 29.7.6 Status Register Name: Access Type: Read-only Offset: 0x1C Reset Value: 0x000C0000 – – – – – – – – – – – – RXBUFF ENDRX GOVRE DRDY OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2...
Page 804 AT32UC3A3 29.7.7 Last Converted Data Register Name: LCDR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – LDATA[9:8] LDATA[7:0] •...
Page 805 AT32UC3A3 29.7.8 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 – – – – – – – – – – – – RXBUFF ENDRX GOVRE DRDY OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0 EOC7 EOC6 EOC5 EOC4 EOC3...
Page 806 AT32UC3A3 29.7.9 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 – – – – – – – – – – – – RXBUFF ENDRX GOVRE DRDY OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0 EOC7 EOC6 EOC5 EOC4 EOC3...
Page 807 AT32UC3A3 29.7.10 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x2C Reset Value: 0x00000000 – – – – – – – – – – – – RXBUFF ENDRX GOVRE DRDY OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0 EOC7 EOC6 EOC5 EOC4 EOC3...
Page 808 AT32UC3A3 29.7.11 Channel Data Register Name: CDRx Access Type: Read-only Offset: 0x2C-0x4C Reset Value: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – DATA[9:8] DATA[7:0] • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
Page 809 AT32UC3A3 29.7.12 Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: – – – – – – – – – – – – – VARIANT – – – – VERSION[11:8] VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. •...
Page 810 AT32UC3A3 29.8 Module Configuration The specific configuration for the ADC instance is listed in the following tables. Table 29-3. Module configuration Feature ADC_NUM_CHANNELS Internal Trigger 0 TIOA Ouput A of the Timer Counter 0 Channel 0 Internal Trigger 1 TIOB Ouput B of the Timer Counter 0 Channel 0 Internal Trigger 2 TIOA Ouput A of the Timer Counter 0 Channel 1 Internal Trigger 3...
Page 811 AT32UC3A3 30. HSB Bus Performance Monitor (BUSMON) Rev 1.0.0.0 30.1 Features • Allows performance monitoring of High Speed Bus master interfaces – Up to 4 masters can be monitored – Peripheral Bus access to monitor registers • The following is monitored –...
Page 812 AT32UC3A3 30.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 30.4.1 Clocks The clock for the BUSMON bus interface (CLK_BUSMON) is generated by the Power Manager. This clock is enabled at reset and can be disabled in the Power Manager. It is recommended to disable the BUSMON before disabling the clock, to avoid freezing the BUSMON in an undefined state.
Page 813 AT32UC3A3 30.6 User interface Table 30-1. BUSMON Register Memory Map Offset Register Register Name Access Reset 0x00 Control register CONTROL Read/Write 0x00000000 0x10 Channel0 Data Cycles register DATA0 Read 0x00000000 0x14 Channel0 Stall Cycles register STALL0 Read 0x00000000 0x18 Channel0 Max Initiation Latency register LAT0 Read 0x00000000...
Page 814 AT32UC3A3 30.6.1 Control Register Name: CONTROL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 CH3RES CH2RES CH1RES CH0RES CH3OF CH2OF CH1OF CH0OF CH3EN CH2EN CH1EN CH0EN • CHnRES: Channel Counter Reset Writting a one to this bit will reset the counter in the channel n. Writting a zero to this bit has no effect.
Page 815 AT32UC3A3 30.6.2 Channel n Data Cycles Register Name: DATAn Access Type: Read-Only Offset: 0x10 + n*0x10 Reset Value: 0x00000000 DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] • DATA: Data cycles counted since the last reset. 32072H–AVR32–10/2012...
Page 816 AT32UC3A3 30.6.3 Channel n Stall Cycles Register Name: STALLn Access Type: Read-Only Offset: 0x14 + n*0x10 Reset Value: 0x00000000 STALL[31:24] STALL[23:16] STALL[15:8] STALL[7:0] • STALL: Stall cycles counted since the last reset. 32072H–AVR32–10/2012...
Page 817 AT32UC3A3 30.6.4 Channel n Max Transfer Initiation Cycles Register Name: LATn Access Type: Read-Only Offset: 0x18 + n*0x10 Reset Value: 0x00000000 LAT[31:24] LAT[23:16] LAT[15:8] LAT[7:0] • LAT: This field is cleared whenever the DATA or STALL register is reset. Maximum transfer initiation cycles counted since the last reset. This counter is saturating.
Page 818 AT32UC3A3 30.6.5 Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0x50 Reset Value: CH3IMPL CH2IMPL CH1IMPL CH0IMPL • CHnIMP: Channel Implementation 1: The corresponding channel is implemented. 0: The corresponding channel is not implemented. 32072H–AVR32–10/2012...
Page 819 AT32UC3A3 30.6.6 Version Register Name: VERSION Access Type: Read-only Offset: 0x54 Reset Value: VARIANT VERSION[11:8] VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 32072H–AVR32–10/2012...
Page 820 AT32UC3A3 30.7 Module Configuration Table 30-2. Register Reset Values Register Reset Value VERSION 0x00000100 PARAMETER 0x0000000F 32072H–AVR32–10/2012...
Page 821 AT32UC3A3 31. MultiMedia Card Interface (MCI) Rev. 4.1.0.0 31.1 Features • Compatible with Multimedia Card specification version 4.3 • Compatible with SD Memory Card specification version 2.0 • Compatible with SDIO specification version 1.1 • Compatible with CE-ATA specification 1.1 •...
Page 822 AT32UC3A3 31.3 Block Diagram Figure 31-1. MCI Block Diagram Peripheral Bus Brigde DMA Controller Peripheral MCI Interface controller DATA Power CLK_MCI Manager Interrupt Control MCI Interrupt Figure 31-2. Application Block Diagram Application Layer Ex: File System, Audio, Security, etc Physical Layer MCI Interface 1 2 3 4 5 6 2 3 4 5...
Page 823 AT32UC3A3 31.4 I/O Lines Description Table 31-1. I/O Lines Description Pin Name Pin Description Type Comments Input/Output/ CMD[1:0] Command/Response CMD of a MMC or SDCard/SDIO PP/OD Clock Input/Output CLK of a MMC or SD Card/SDIO DAT[0..7] of a MMC DATA[7:0] Data 0..7 of Slot A Input/Output/PP DAT[0..3] of a SD Card/SDIO...
Page 824 AT32UC3A3 The MultiMedia Card communication is based on a 13-pin serial bus interface. It has three com- munication lines and four supply lines. Table 31-2. Bus Topology MCI Pin Name Number Name Type Description (Slot z) DAT[3] I/O/PP Data DATAz[3] I/O/PP/OD Command/response CMDz...
Page 825 AT32UC3A3 The SD Memory Card bus includes the signals listed in Table 31-3 on page 825. Table 31-3. SD Memory Card Bus Signals MCI Pin Name Number Name Type Description (Slot z) CD/DAT[3] I/O/PP Card detect/ Data line Bit 3 DATAz[3] Command/response CMDz...
Page 826 AT32UC3A3 Figure 31-8. Mixing MultiMedia and SD Memory Cards with Two Slots DATA[7:0] CMD[0] 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1213 8 1213 8 1213 8 MMC1 MMC2 MMC3 DATA[11:8] SDCARD...
Page 827 AT32UC3A3 The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. Refer also to Table 31-5 on page 828. MultiMediaCard bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token.
Page 828 AT32UC3A3 The command ALL_SEND_CID and the fields and values for CMDR register are described in Table 31-5 on page 828 Table 31-6 on page 828. Table 31-5. ALL_SEND_CID Command Description Command CMD Index Type Argument Resp Abbreviation Description Asks all cards to send their CID CMD2 [31:0] stuff bits...
Page 829 AT32UC3A3 Figure 31-9. Command/Response Functional Flow Diagram Set the command argument ARGR = Argument Set the command CMD = Command Read the SR register Wait for SR.CMDRY bit set to one SR.CMDRDY Check error bits in the Status error bits? SR register Read response if required RETURN ERROR...
Page 830 AT32UC3A3 Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): • Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received.
Page 831 AT32UC3A3 Figure 31-10. Read Functional Flow Diagram Send SELECT/DESELECT_CARD Command to select the card Send SET_BLOCKLEN command Read with DMA Write a zero in the DMA.DMAEN bit Write a one in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field Write the BlockLenght in the MR.BLKLEN field Write the block count in the BLKR.BCNT field (if necessary)
Page 832 AT32UC3A3 In write operation, the Padding Value bit in the MR register (MR.PADV) is used to define the padding value when writing non-multiple block size. When the MR.PADV is zero, then 0x00 value is used when padding data, otherwise 0xFF is used. Write a one in the DMA Hardware Handshaking Enable bit in the DMA Configuration Register (DMA.DMAEN) enables DMA transfer.
Page 833 AT32UC3A3 Figure 31-11. Write Functional Flow Diagram Send SELECT/DESELECT_CARD Command to select the card Send SET_BLOCKLEN command Write using DMA Write a zero in the DMA.DMAEN bit Write a one in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field Write the BlockLenght in the MR.BLKLEN field Write the block count in the BLKR.BCNT field (if necessary)
Page 834 AT32UC3A3 The following flowchart shows how to manage a multiple write block transfer with the DMA Con- troller (see Figure 31-12 on page 835). Polling or interrupt method can be used to wait for the end of write according to the contents of the IMR register. 32072H–AVR32–10/2012...
Page 835 AT32UC3A3 Figure 31-12. Multiple Write Functional Flow Diagram Send SELECT/DESELECT_CARD Command to select the card Send SET_BLOCKLEN command Write a zero in the DMA.DMAEN bit Write the block lenght in the MR.BLKLEN field Write the block count in the BLKR.BCNT field (if necessary) Configure the DMA channel X write the Data Adress in the DMA Controller...
Page 836 AT32UC3A3 31.6.4.1 WRITE_SINGLE_BLOCK operation using DMA Controller 1. Wait until the current command execution has successfully terminated. c. Check that the Transfer Done bit in the SR register (SR.XFRDONE) is set 2. Write the block length in the card. This value defines the value block_lenght. 3.
Page 837 AT32UC3A3 31.6.4.4 READ_MULTIPLE_BLOCK 1. Wait until the current command execution has successfully terminated. a. Check that the SR.CMDRDY and the SR.NOTBUSY are set. 2. Write the block length in the card. This value defines the value block_lenght. 3. Write the MR.BLKLEN with block_lenght value. 4.
Page 838 AT32UC3A3 An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share access to the SD bus. In order to allow the sharing of access to the host among multiple devices, SDIO and combo cards can implement the optional concept of suspend/resume (Refer to the SDIO Specification for more details).
Page 839 AT32UC3A3 CMDR register (CMDR.SPCMD) must be set to three to issue the CE-ATA completion Signal Disable Command. 31.6.6.4 CE-ATA Error Recovery Several methods of ATA command failure may occur, including: • No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60). •...
Page 840 AT32UC3A3 6. When Data transfer is completed, host processor shall terminate the boot stream by writing the MCI_CMDR register with SPCMD field set to BOOTEND. 31.6.7.2 Boot Procedure, dma mode 1. Configure MCI2 data bus width programming SDCBUS Field in the MCI_SDCR regis- ter.
Page 841 AT32UC3A3 31.6.8.3 Write Access During a write access, the SR.XFRDONE bit behaves as shown in Figure 31-14 on page 841. Figure 31-14. SR.XFRDONE During a Write Access CMD line MCI writeCMD Card response The CMDRDY flag is released 8 t lafter the end of the card response.
Page 842 AT32UC3A3 Table 31-7. MCI Register Memory Map Offset Register Name Access Reset 0x044 Interrupt Enable Register Write-only 0x00000000 0x048 Interrupt Disable Register Write-only 0x00000000 0x04C Interrupt Mask Register Read-only 0x00000000 0x050 DMA Configuration Register Read-write 0x00000000 0x054 Configuration Register Read-write 0x00000000 0x0E4 Write Protection Mode Register...
Page 843 AT32UC3A3 31.7.1 Control Register Name: Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 SWRST IOWAITDIS IOWAITEN PWSDIS PWSEN MCIDIS MCIEN • SWRST: Software Reset Writing a one to this bit will reset the MCI interface. Writing a zero to this bit has no effect. •...
Page 844 AT32UC3A3 31.7.2 Mode Register Name: Access Type: Read-write Offset: 0x004 Reset Value: 0x00000000 BLKLEN[15:8] BLKLEN[7:0] PADV FBYTE WRPROOF RDPROOF PWSDIV CLKDIV • BLKLEN[15:0]: Data Block Length This field determines the size of the data block. This field is also accessible in the BLKR register. If FBYTE bit is zero, the BLKEN[1:0] field must be written to 0b00 Notes: 1.
Page 845 AT32UC3A3 • PWSDIV: Power Saving Divider (PWSDIV) Multimedia Card Interface clock is divided by 2 + 1 when entering Power Saving Mode. Warning: This value must be different from zero before enabling the Power Save Mode in the CR register (CR.PWSEN). •...
Page 846 AT32UC3A3 31.7.3 Data Time-out Register Name: DTOR Access Type: Read/Write Offset: 0x008 Reset Value: 0x00000000 DTOMUL DTOCYC These two fields determine the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers. It is equal to (DTOCYC x Multiplier). If the data time-out defined by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error bit in the SR register (SR.DTOE) is set.
Page 847 AT32UC3A3 31.7.4 SDCard/SDIO Register Name: SDCR Access Type: Read/Write Offset: 0x00C Reset Value: 0x00000000 SDCBUS – – – – SDCSEL • SDCBUS: SDCard/SDIO Bus Width SDCBUS BUS WIDTH 1 bit Reserved 4 bits 8 bits • SDCSEL: SDCard/SDIO Slot SDCSEL SDCard/SDIO Slot Slot A is selected.
Page 848 AT32UC3A3 31.7.5 Argument Register Name: ARGR Access Type: Read/Write Offset: 0x010 Reset Value: 0x00000000 ARG[31:24] ARG[23:16] ARG[15:8] ARG[7:0] • ARG[31:0]: Command Argument this field contains the argument field of the command. 32072H–AVR32–10/2012...
Page 849 AT32UC3A3 31.7.6 Command Register Name: CMDR Access Type: Write-only Offset: 0x014 Reset Value: 0x00000000 BOOTACK ATACS IOSPCMD TRTYP TRDIR TRCMD MAXLAT OPDCMD SPCMD RSPTYP CMDNB This register is write-protected while SR.CMDRDY is zero. If an interrupt command is sent, this register is only writable by an interrupt response (SPCMD field).
Page 850 AT32UC3A3 • TRTYP: Transfer Type TRTYP Transfer Type MMC/SDCard Single Block MMC/SDCard Multiple Block MMC Stream Reserved SDIO Byte SDIO Block others Reserved • TRDIR: Transfer Direction Writing a zero to this bit will configure the transfer direction as write transfer. Writing a one to this bit will configure the transfer direction as read transfer.
Page 851 AT32UC3A3 • RSPTYP: Response Type Response Type No response. 48-bit response. 136-bit response. R1b response type • CMDNB: Command Number The Command Number to transmit. 32072H–AVR32–10/2012...
Page 852 AT32UC3A3 31.7.7 Block Register Name: BLKR Access Type: Read/Write Offset: 0x018 Reset Value: 0x00000000 BLKLEN[15:8] BLKLEN[7:0] BCNT[15:8] BCNT[7:0] • BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the MR register. If MR.FBYTE bit is zero, the BLKEN[17:16] field must be written to 0b00 Notes: 1.
Page 853 AT32UC3A3 31.7.8 Completion Signal Time-out Register Name: CSTOR Access Type: Read-write Offset: 0x01C Reset Value: 0x00000000 CSTOMUL CSTOCYC These two fields determines the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers. Its value is calculated by (CSTOCYC x Multiplier). These two fields also determine the maximum number of CLK_MCI cycles that the MCI waits between the end of the data transfer and the assertion of the completion signal.
Page 854 AT32UC3A3 31.7.9 Response Register n Name: RSPRn Access Type: Read-only Offset: 0x020 + 0*0x04 Reset Value: 0x00000000 RSP[31:24] RSP[23:16] RSP[15:8] RSP[7:0] • RSP[31:0]: Response The response register can be read by N access(es) at the same RSPRn or at consecutive addresses (0x20 + n*0x04). N depends on the size of the response.
Page 855 AT32UC3A3 31.7.10 Receive Data Register Name: Access Type: Read-only Offset: 0x030 Reset Value: 0x00000000 DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] • DATA[31:0]: Data to Read The last data received. 32072H–AVR32–10/2012...
Page 856 AT32UC3A3 31.7.11 Transmit Data Register Name: Access Type: Write-only Offset: 0x034 Reset Value: 0x00000000 DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] • DATA[31:0]: Data to Write The data to send. 32072H–AVR32–10/2012...
Page 857 AT32UC3A3 31.7.12 Status Register Name: Access Type: Read-only Offset: 0x040 Reset Value: 0x0C000025 UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE TXBUFE RXBUFF CSRCV SDIOWAIT SDIOIRQB SDIOIRQA ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY...
Page 858 AT32UC3A3 • CSTOE: Completion Signal Time-out Error This bit is set when the completion signal time-out defined by the CSTOR.CSTOCYC field and the CSTOR.CSTOMUL field is reached. This bit is cleared when reading the SR register. • DTOE: Data Time-out Error This bit is set when the data time-out defined by the DTOR.DTOCYC field and the DTOR.DTOMUL field is reached.
Page 859 AT32UC3A3 A block write operation uses a simple busy signalling of the write operation duration on the data (DAT[0]) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line (DAT[0]) to LOW.
Page 860 AT32UC3A3 31.7.13 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x044 Reset Value: 0x00000000 UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE TXBUFF RXBUFF CSRCV SDIOWAIT SDIOIRQB SDIOIRQA ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY...
Page 861 AT32UC3A3 31.7.14 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x048 Reset Value: 0x00000000 UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE TXBUFF RXBUFF CSRCV SDIOWAIT SDIOIRQB SDIOIRQA ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY...
Page 862 AT32UC3A3 31.7.15 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x04C Reset Value: 0x00000000 UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE TXBUFF RXBUFF CSRCV SDIOWAIT SDIOIRQB SDIOIRQA ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY...
Page 863 AT32UC3A3 31.7.16 DMA Configuration Register Name: Access Type: Read/Write Offset: 0x050 Reset Value: 0x00000000 DAMEN CHKSIZE OFFSET • DMAEN: DMA Hardware Handshaking Enable 1: DMA Interface is enabled. 0: DMA interface is disabled. To avoid unpredictable behavior, DMA hardware handshaking must be disabled when CPU transfers are performed. To avoid data losses, the DMA register should be initialized before sending the data transfer command.
Page 864 AT32UC3A3 31.7.17 Configuration Register Name: Access Type: Read/Write Offset: 0x054 Reset Value: 0x00000000 LSYNC HSMODE FERRCTRL FIFOMODE • LSYNC: Synchronize on the last block 1: The pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall be different from zero) 0: The pending command is sent at the end of the current data block.
Page 865 AT32UC3A3 31.7.18 Write Protect Mode Register Name: WPMR Access Type: Read/Write Offset: 0x0E4 Reset Value: 0x00000000 WPKEY[23:16] WPKEY[15:8] WPKEY[7:0] WPEN • WPKEY[23:0]: Write Protection Key password This field should be written at value 0x4D4349 (ASCII code for “MCI”). Writing any other value in this field has no effect. •...
Page 866 AT32UC3A3 31.7.19 Write Protect Status Register Name: WPSR Access Type: Read-only Offset: 0x0E8 Reset Value: 0x00000000 WPVSRC[15:8] WPVSRC[7:0] WPVS • WPVSRC[15:0]: Write Protection Violation Source This field contains address where the violation access occurs. • WPVS: Write Protection Violation Status WPVS Definition No Write Protection Violation occurred since the last read of this...
Page 867 AT32UC3A3 31.7.20 Version Register Name: VERSION Access: Read-only Offset: 0x0FC Reset Value: VARIANT VERSION[11:8] VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associate 32072H–AVR32–10/2012...
Page 868 AT32UC3A3 31.7.21 FIFO Memory Aperture Name: Access: Read/Write Offset: 0x200 - 0x3FFC Reset Value: 0x000000000 DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] • DATA[31:0]:Data to read or Data to write 32072H–AVR32–10/2012...
Page 869 AT32UC3A3 31.8 Module Configuration The specific configuration for the MCI instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 31-8. Module Clock Name Module name Clock name...
Page 870 AT32UC3A3 32. Memory Stick Interface (MSI) Rev: 2.1.0.0 32.1 Features • Memory Stick ver. 1.x & Memory Stick PRO support • Memory Stick serial clock (serial mode: 20 MHz max., parallel mode: 40 MHz max.) • Data transmit/receive FIFO of 64 bits x 4 •...
Page 871 AT32UC3A3 Figure 32-2. Write packet Memory Stick Host Memory Stick SDIO / DATA[3:0] DATA RDY/BSY SCLK 32.3 Block Diagram Figure 32-3. MSI block diagram CLK_MSI Registers ÷ SDIO / DATA0 DATA1 FIFO 64 x 4 DATA2 MS I/F DATA3 SCLK Data buffer 32.4 Product Dependencies...
Page 872 AT32UC3A3 32.4.3 Interrupt Controller MSI interrupt line is connected to the Interrupt Controller. In order to handle interrupts, Interrupt Controller(INTC) must be programmed before configuring MSI. 32.4.4 DMA Controller (DMACA) Handshake signals are connected to DMACA. In order to accelerate transfer from/to flash card, DMACA must be programmed before using MSI.
Page 873 AT32UC3A3 32.6 Functional Description 32.6.1 Reset Operation An internal reset (initialization of the internal registers and operating sequence) is performed when PB reset is active or by setting SYS.RST=1. RST bit is cleared to 0 after the internal reset is completed. The protocol currently being executed stops, and the internal operating sequence is initialized.
Page 874 AT32UC3A3 sources can be cleared by setting corresponding bit in ISCR but DRQ which is cleared once FIFO has been read/written. Figure 32-5. Communication example PEND=1, MSINT=1 Interrupt enable MSIER register FDIR=1 FIFO direction setting MSSYS register Write to FIFO MSDAT register TPC = SET_CMD TPC setting...
Page 875 AT32UC3A3 Figure 32-6. Interface mode switching sequence Serial Interface Mode MSSYS.SRAC=1, MSSYS.REI=1) SET_R/W_REG_ADRS TPC WRITE_REG TPC system parameter Error (PAM bit) Set Parallel Interface Mode MSSYS.SRAC=0, MSSYS.REI=0) Change SCLK MSSYS.CLKDIV[7:0]=X) 32.6.4 Data transfer requests After the communication protocol with the Memory Stick starts, a data transfer request is asserted to the CPU (DRQ bit in ISR) and to DMACA (internal signals), until data transfer of the amount indicated by DSZ (CMD) is finished.
Page 876 AT32UC3A3 the interrupt source, even if the interrupt is masked, can be read in ISR. DRQ interrupt request is cleared by reading (reception) or writing (transmission) FIFO, other interrupt requests are cleared by writing 1 to the corresponding bit in Interrupt Status Clear Reg- ister (ISCR).
Page 877 AT32UC3A3 32.7.1 Command register Name : Access Type : Read/Write Offset : 0x00 Reset Value : 0x00000000 • TPC : Transfer Protocol Code. code (dec) Description READ_LONG_DATA Transfer data from Data Buffer (512 bytes) READ_SHORT_DATA Transfer data from Data Buffer (32~256 bytes) READ_REG Read from a register GET_INT...
Page 878 AT32UC3A3 1 : Reserved. • DSZ : Data size. Length can be set from 1 byte to 1024 bytes. However, 1024 bytes is set when DSZ=0. 32072H–AVR32–10/2012...
Page 879 AT32UC3A3 32.7.2 Data register Name : Access Type : Read/Write Offset : 0x04 Reset Value : 0x4C004C00 DATA DATA DATA DATA This register is used to acces internal FIFO. Even when the data is less than 8 bytes, always read and write 8 bytes of data. 32072H–AVR32–10/2012...
Page 880 AT32UC3A3 32.7.3 Status register Name : Access Type : Read Only Offset : 0x08 Reset Value : 0x00001020 ISTA • ISTA : Insertion Status. It reflects the Memory Stick card presence. This is the inverse of INS pin. 0 : No card. 1 : Card is inserted.
Page 881 AT32UC3A3 • BRQ : MS Data Buffer Request. In parallel mode, this bit reflects the BREQ bit in the status register of a Memory Stick (INT). It indicates that a host has requested to access a Memory Sticks page buffer.In serial mode, this bit is always 0. It is cleared to 0 by writing to the command register (CMD).
Page 882 AT32UC3A3 32.7.4 System register Name : Access Type : Read/Write Offset : 0x0C Reset Value : 0x00004015 CLKDIV SRAC NOCRC FCLR FDIR • CLKDIV : Clock Division. Write this field to change SCLK frequency = CLK_MSI / (2*(CLKDIV+1)). • RST : Reset. When RST is written, internal synchronous reset is performed. 0 : This bit is cleared to 0 after the internal reset is completed.
Page 883 AT32UC3A3 1 : Write 1 to sample data at the rising edge of SCLK. • REO : Rising Edge output. This bit is used when not fixed hold time by the side of the Memory Stick in parallel communication. This setting cannot be changed during protocol execution. 0 : Write 0 to synchronize outputs with the falling edge of SCLK.
Page 884 AT32UC3A3 32.7.5 Interrupt Status register Name : Access Type : Read Only Offset : 0x10 Reset Value : 0x00000000 MSINT PEND • CD : Card Detection. 0 : No card detected. This bit is cleared when the correponding bit in ISCR is set to 1. 1 : This bit is set to 1 when a Memory Stick card is inserted or removed.
Page 885 AT32UC3A3 32.7.6 Interrupt Status Clear register Name : ISCR Access Type : Write Only Offset : 0x14 Reset Value : 0x00000000 MSINT PEND • CD : Card Detection clear bit. 0 : Writing 0 has no effect. 1 : Writing 1 clears corresponding bit in ISR. •...
Page 886 AT32UC3A3 32.7.7 Interrupt Enable register Name : Access Type : Write Only Offset : 0x18 Reset Value : 0x00000000 MSINT PEND • CD : Card Detection interrupt enable. 0 : Writing 0 has no effect. 1 : Writing 1 set to 1 corresponding bit in IMR. •...
Page 887 AT32UC3A3 32.7.8 Interrupt Disable register Name : Access Type : Write Only Offset : 0x1C Reset Value : 0x00000000 MSINT PEND • CD : Card Detection interrupt disable. 0 : Writing 0 has no effect. 1 : Writing 1 clears to 0 corresponding bit in IMR. •...
Page 888 AT32UC3A3 32.7.9 Interrupt Mask register Name : Access Type : Read Only Offset : 0x20 Reset Value : 0x00000000 MSINT PEND • CD : Card Detection interrupt mask. 0 : Interrupt is disabled. 1 : Interrupt is enabled. • TOE : Time Out Error interrupt mask. 0 : Interrupt is disabled.
Page 889 AT32UC3A3 32.7.10 Version Register Name : VERSION Access Type : Read Only Offset : 0x24 Reset Value : 0x00000210 VARIANT VERSION[11:8] VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION : Version Number Version number of the module. No functionality associated. 32072H–AVR32–10/2012...
Page 890 AT32UC3A3 33. Advanced Encryption Standard (AES) Rev: 1.2.3.1 33.1 Features • Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) • 128-bit/192-bit/256-bit cryptographic key • 12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256-bit cryptographic key • Support of the five standard modes of operation specified in the NIST Special Publication 800- 38A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques: –...
Page 891 AT32UC3A3 33.3.2 Clocks The clock for the AES bus interface (CLK_AES) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the AES before disabling the clock, to avoid freezing the AES in an undefined state. 33.3.3 Interrupts The AES interrupt request line is connected to the interrupt controller.
Page 892 AT32UC3A3 These sizes are selected by writing the Cipher Feedback Data Size field in the MR register (MR.CFDS). 33.4.2 Start Modes The Start Mode field in the MR register (MR.SMOD) allows selection of the encryption (or decryption) start mode. 33.4.2.1 Manual mode The sequence is as follows: •...
Page 893 AT32UC3A3 33.4.2.3 DMA mode The DMA Controller can be used in association with the AES to perform an encryption/decryp- tion of a buffer without any action by the software during processing. In this starting mode, the type of the data transfer (byte, halfword or word) depends on the oper- ation mode.
Page 894 AT32UC3A3 33.4.3.1 Manual and automatic modes • When MR.LOD is zero The ISR.DATRDY bit is cleared when at least one of the ODATAnR registers is read. Figure 33-1. Manual and Automatic Modes when MR.LOD is zero Write CR.START (Manual mode) Write IDATAnR register(s) (Auto mode) Read ODATAnR register(s) ISR.DATRDY...
Page 895 AT32UC3A3 Figure 33-3. DMA Mode when MR.LOD is zero E n a b le D M A C o n tro lle r C h a n n e ls (R e c e iv e a n d T ra n s m it C h a n n e ls) M u ltip le e n c ry p tio n o r d e c ry p tio n p ro c e s s e s D M A C o n tro lle r In te rru p t •...
Page 896 AT32UC3A3 33.4.4 Security Features 33.4.4.1 Countermeasures The AES also features hardware countermeasures that can be useful to protect data against Dif- ferential Power Analysis (DPA) attacks. These countermeasures can be enabled through the Countermeasure Type field in the MR reg- ister (MR.CTYPE).
Page 897 AT32UC3A3 33.5 User Interface Table 33-4. AES Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register Write-only 0x00000000 0x04 Mode Register Read/Write 0x00000000 0x10 Interrupt Enable Register Write-only 0x00000000 0x14 Interrupt Disable Register Write-only 0x00000000 0x18 Interrupt Mask Register Read-only 0x00000000 0x1C...
Page 898 AT32UC3A3 33.5.1 Control Register Name: Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 LOADSEED SWRST START • LOADSEED: Random Number Generator Seed Loading Writing a one to this bit will load a new seed in the embedded random number generator used for the different countermeasures.
Page 899 AT32UC3A3 33.5.2 Mode Register Name: Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 CTYPE CKEY CFBS OPMOD KEYSIZE SMOD PROCDLY CIPHER • CTYPE: Countermeasure Type CTYPE Description Countermeasure type 1 is disabled Add random spurious power consumption during some configuration settings Countermeasure type 2 is disabled Add randomly 1 cycle to processing.
Page 900 AT32UC3A3 • CKEY: Countermeasure Key Writing the value 0xE to this field allows the CTYPE field to be modified. Writing another value to this field has no effect. This bit always reads as zero. • CFBS: Cipher Feedback Data Size CFBS Description 128-bit...
Page 901 AT32UC3A3 • SMOD: Start Mode SMOD Description Manual mode Automatic mode DMA mode • LOD = 0: The encrypted/decrypted data are available at the address specified in the configuration of DMA Controller. • LOD = 1: The encrypted/decrypted data are available in the ODATAnR registers. Reserved •...
Page 902 AT32UC3A3 33.5.3 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 URAD DATRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 903 AT32UC3A3 33.5.4 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 URAD DATRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 32072H–AVR32–10/2012...
Page 904 AT32UC3A3 33.5.5 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 URAD DATRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one.
Page 905 AT32UC3A3 33.5.6 Interrupt Status Register Name: Access Type: Read-only Offset: 0x1C Reset Value: 0x0000001E URAT URAD DATRDY • URAT: Unspecified Register Access Type: URAT Description The IDATAnR register during the data processing in DMA mode. The ODATAnR register read during the data processing. The MR register written during the data processing.
Page 906 AT32UC3A3 • DATRDY: Data Ready This bit is set/clear as described in the Table 33-3 on page 895. This bit is also cleared when SWRST bit in the Control Register is set to one. 32072H–AVR32–10/2012...
Page 907 AT32UC3A3 33.5.7 Key Word n Register Name: KEYWnR Access Type: Write-only Offset: 0x20 +(n-1)*0x04 Reset Value: 0x00000000 KEYWn[31:24] KEYWn[23:16] KEYWn[15:8] KEYWn[7:0] • KEYWn[31:0]: Key Word n Writing the 128-bit/192-bit/256-bit cryptographic key used for encryption/decryption in the four/six/eight 32-bit Key Word registers.
Page 908 AT32UC3A3 33.5.8 Input Data n Register Name: IDATAnR Access Type: Write-only Offset: 0x40 + (n-1)*0x04 Reset Value: 0x00000000 IDATAn[31:24] IDATAn[23:16] IDATAn[15:8] IDATAn[7:0] • IDATAn[31:0]: Input Data Word n Writing the 128-bit data block used for encryption/decryption in the four 32-bit Input Data registers. IDATA1 corresponds to the first word of the data to be encrypted/decrypted, and IDATA4 to the last one.
Page 909 AT32UC3A3 33.5.9 Output Data n Register Name: ODATAnR Access Type: Read-only Offset: 0x50 + (n-1)*0x04 Reset Value: 0x00000000 ODATAn[31:24] ODATAn[23:16] ODATAn[15:8] ODATAn[7:0] • ODATAn[31:0]: Output Data n Reading the four 32-bit ODATAnR give the 128-bit data block that has been encrypted/decrypted ODATA1 corresponds to the first word, ODATA4 to the last one.
Page 910 AT32UC3A3 33.5.10 Initialization Vector n Register Name: IVnR Access Type: Write-only Offset: 0x60 + (n-1)*0x04 Reset Value: 0x00000000 IVn[31:24] IVn[23:16] IVn[15:8] IVn[7:0] • IVn[31:0]: Initialization Vector n The four 32-bit Initialization Vector registers set the 128-bit Initialization Vector data block that is used by some modes of operation as an additional initial input: MODE(OPMODE.
Page 911 AT32UC3A3 33.5.11 Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: VARIANT VERSION[11:8] VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION[11:0] Version number of the module. No functionality associated. 32072H–AVR32–10/2012...
Page 912 AT32UC3A3 33.6 Module Configuration The specific configuration for each AES instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 33-5.
Page 913 AT32UC3A3 34. Audio Bitstream DAC (ABDAC) Rev: 1.0.1.1 34.1 Features • Digital Stereo DAC • Oversampled D/A conversion architecture – Oversampling ratio fixed 128x – FIR equalization filter – Digital interpolation filter: Comb4 – 3rd Order Sigma-Delta D/A converters • Digital bitstream outputs •...
Page 914 AT32UC3A3 34.3 Block Diagram Figure 34-1. ABDAC Block Diagram Audio Bitstream DAC GCLK_ABDAC bit_clk Clock Generator sample_clk COMB Sigma-Delta CHANNEL0[15:0] Equalization FIR DATA0 (INT=128) DA-MOD User Interface CHANNEL1[15:0] COMB Sigma-Delta Equalization FIR DATA1 (INT=128) DA-MOD 34.4 I/O Lines Description Table 34-1. I/O Lines Description Pin Name Pin Description...
Page 915 AT32UC3A3 34.5.2 Clocks The CLK_ABDAC to the Audio Bitstream DAC is generated by the Power Manager (PM). Before using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is enabled in the Power Manager. The ABDAC needs a separate clock for the D/A conversion operation. This clock, GCLK_ABDAC should be set up in the Generic Clock register in the Power Manager and its fre- quency must be as follow: ×...
Page 916 AT32UC3A3 If one want to get coherence between the sign of the input data and the output voltage one can use the DATAN signal or invert the sign of the input data by software. 34.6.3 Data Swapping When the SWAP bit in the ABDAC Control Register (CR.SWAP) is written to one, writing to the Sample Data Register (SDR) will cause the values written to the CHANNEL0 and CHANNEL1 fields to be swapped.
Page 917 AT32UC3A3 34.6.9 Frequency Response Figure 34-2. Frequency Response, EQ-FIR+COMB - 1 0 - 2 0 - 3 0 - 4 0 - 5 0 - 6 0 F r e q u e n c y [ F s ] 32072H–AVR32–10/2012...
Page 918 AT32UC3A3 34.7 User Interface Table 34-2. ABDAC Register Memory Map Offset Register Register Name Access Reset 0x00 Sample Data Register Read/Write 0x00000000 0x08 Control Register Read/Write 0x00000000 0x0C Interrupt Mask Register Read-only 0x00000000 0x10 Interrupt Enable Register Write-only 0x00000000 0x14 Interrupt Disable Register Write-only 0x00000000...
Page 919 AT32UC3A3 34.7.1 Sample Data Register Name: Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 CHANNEL1[15:8] CHANNEL1[7:0] CHANNEL0[15:8] CHANNEL0[7:0] • CHANNEL1: Sample Data for Channel 1 signed 16-bit Sample Data for channel 1. • CHANNEL0: Signed 16-bit Sample Data for Channel 0 signed 16-bit Sample Data for channel 0.
Page 920 AT32UC3A3 34.7.2 Control Register Name: Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 SWAP • EN: Enable Audio Bitstream DAC 1: The module is enabled. 0: The module is disabled. • SWAP: Swap Channels 1: The swap of CHANNEL0 and CHANNEL1 samples is enabled. 0: The swap of CHANNEL0 and CHANNEL1 samples is disabled.
Page 921 AT32UC3A3 34.7.3 Interrupt Mask Register Name: Access Type: Read-only Offset: 0x0C Reset Value: 0x00000000 TXREADY UNDERRUN 1: The corresponding interrupt is enabled. 0: The corresponding interrupt is disabled. A bit in this register is set when the corresponding bit in IER is written to one. A bit in this register is cleared when the corresponding bit in IDR is written to one.
Page 922 AT32UC3A3 34.7.4 Interrupt Enable Register Name: Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 TXREADY UNDERRUN Writing a one to a bit in this register will set the corresponding bit in IMR. Writing a zero to a bit in this register has no effect. 32072H–AVR32–10/2012...
Page 923 AT32UC3A3 34.7.5 Interrupt Disable Register Name: Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 TXREADY UNDERRUN Writing a one to a bit in this register will clear the corresponding bit in IMR. Writing a zero to a bit in this register has no effect. 32072H–AVR32–10/2012...
Page 924 AT32UC3A3 34.7.6 Interrupt Clear Register Name: Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 TXREADY UNDERRUN Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request. Writing a zero to a bit in this register has no effect. 32072H–AVR32–10/2012...
Page 925 AT32UC3A3 34.7.7 Interrupt Status Register Name: Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 TXREADY UNDERRUN • TXREADY: TX Ready Interrupt Status This bit is set when the Audio Bitstream DAC is ready to receive a new data in SDR. This bit is cleared when the Audio Bitstream DAC is not ready to receive a new data in SDR.
Page 926 AT32UC3A3 35. Programming and Debugging 35.1 Overview General description of programming and debug features, block diagram and introduction of main concepts. 35.2 Service Access Bus The AVR32 architecture offers a common interface for access to On-Chip Debug, programming, and test functions. These are mapped on a common bus called the Service Access Bus (SAB), which is linked to the JTAG port through a bus master module, which also handles synchroniza- tion between the debugger and SAB clocks.
Page 927 AT32UC3A3 35.2.2.1 Security measure and control location A security measure is a mechanism to either block or allow SAB access to a certain address or address range. A security measure is enabled or disabled by one or several control signals. This is called the control location for the security measure.
Page 928 AT32UC3A3 35.3 On-Chip Debug (OCD) Rev: 1.4.2.1 35.3.1 Features • Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+ • JTAG access to all on-chip debug functions • Advanced program, data, ownership, and watchpoint trace supported • NanoTrace JTAG-based trace access •...
Page 929 AT32UC3A3 35.3.3 Block Diagram Figure 35-1. On-Chip Debug Block Diagram JTAG JTAG On-Chip Debug Memory Transmit Queue Watchpoints Service Unit Debug PC Program Ownership Data Trace Debug Trace Trace Breakpoints Instruction Internal Memories and HSB Bus Matrix peripherals SRAM 35.3.4 JTAG-based Debug Features A debugger can control all OCD features by writing OCD registers over the JTAG interface.
Page 930 AT32UC3A3 Figure 35-2. JTAG-based Debugger JTAG-based debug tool 10-pin IDC JTAG AVR32 35.3.4.1 Debug Communication Channel The Debug Communication Channel (DCC) consists of a pair OCD registers with associated handshake logic, accessible to both CPU and JTAG. The registers can be used to exchange data between the CPU and the JTAG master, both runtime as well as in debug mode.
Page 931 AT32UC3A3 35.3.4.3 OCD mode When a breakpoint triggers, the CPU enters OCD mode, and instructions are fetched from the Debug Instruction OCD register. Each time this register is written by JTAG, the instruction is executed, allowing the JTAG to execute CPU instructions directly. The JTAG master can e.g. read out the register file by issuing mtdr instructions to the CPU, writing each register to the Debug Communication Channel OCD registers.
Page 932 AT32UC3A3 Debug tools utilizing the AUX port should connect to the device through a Nexus-compliant Mic- tor-38 connector, as described in the AVR32UC Technical Reference manual. This connector includes the JTAG signals and the RESET_N pin, giving full access to the programming and debug features in the device.
Page 933 AT32UC3A3 The trace features can be configured to be very selective, to reduce the bandwidth on the AUX port. In case the transmit queue overflows, error messages are produced to indicate loss of data. The transmit queue module can optionally be configured to halt the CPU when an overflow occurs, to prevent the loss of messages, at the expense of longer run-time for the program.
Page 934 AT32UC3A3 35.3.6.7 Software Quality Analysis (SQA) Software Quality Analysis (SQA) deals with two important issues regarding embedded software development. Code coverage involves identifying untested parts of the embedded code, to improve test procedures and thus the quality of the released software. Performance analysis allows the developer to precisely quantify the time spent in various parts of the code, allowing bottlenecks to be identified and optimized.
Page 935 AT32UC3A3 35.4 JTAG and Boundary-scan (JTAG) Rev: 2.0.0.4 35.4.1 Features • IEEE1149.1 compliant JTAG Interface • Boundary-scan Chain for board-level testing • Direct memory access and programming capabilities through JTAG Interface 35.4.2 Overview The JTAG Interface offers a four pin programming and debug solution, including boundary-scan support for board-level testing.
Page 936 AT32UC3A3 35.4.3 Block Diagram Figure 35-4. JTAG and Boundary-scan Access 32-bit AVR device JTAG JTAG master Boundary scan enable Controller TDO TDI Instruction register Data register scan enable scan enable Instruction Register JTAG data registers 2nd JTAG Device Identification Register device By-pass Register Reset Register...
Page 937 AT32UC3A3 35.4.5.1 Power Management When an instruction that accesses the SAB is loaded in the instruction register, before entering a sleep mode, the system clocks are not switched off to allow debugging in sleep modes. This can lead to a program behaving differently when debugging. 35.4.5.2 Clocks The JTAG Interface uses the external TCK pin as clock source.
Page 938 AT32UC3A3 Figure 35-5. TAP Controller State Diagram Test-Logic- Reset Run-Test/ Select-DR Select-IR Idle Scan Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR 32072H–AVR32–10/2012...
Page 939 AT32UC3A3 35.4.7 How to Initialize the Module Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS high for 5 TCK clock periods. This sequence should always be applied at the start of a JTAG session to bring the TAP Controller into a defined state before applying JTAG commands.
Page 940 Optionally a series resistor can be added between the line and the pin to reduce the current. Details about the boundary-scan chain can be found in the BSDL file for the device. This can be found on the Atmel website. 35.4.10 Service Access Bus The AVR32 architecture offers a common interface for access to On-Chip Debug, programming, and test functions.
Page 941 AT32UC3A3 For more information about the SAB and a list of SAB slaves see the Service Access Bus chapter. 35.4.10.1 SAB Address Mode The MEMORY_SIZED_ACCESS instruction allows a sized read or write to any 36-bit address on the bus. MEMORY_WORD_ACCESS is a shorthand instruction for 32-bit accesses to any 36-bit address, while the NEXUS_ACCESS instruction is a Nexus-compliant shorthand instruc- tion for accessing the 32-bit OCD registers in the 7-bit address space reserved for these.
Page 942 AT32UC3A3 • During Shift-DR of read data: The read data is invalid. The SAB stays in data mode. Repeat scanning until the busy bit clears. • During Shift-DR of write data: The write data is ignored. The SAB stays in data mode. Repeat scanning until the busy bit clears.
Page 943 AT32UC3A3 35.5 JTAG Instruction Summary The implemented JTAG instructions in the 32-bit AVR are shown in the table below. Table 35-7. JTAG Instruction Summary Instruction OPCODE Instruction Description 0x01 IDCODE Select the 32-bit Device Identification register as data register. 0x02 SAMPLE_PRELOAD Take a snapshot of external pin values without affecting system operation.
Page 944 AT32UC3A3 Other security mechanisms can also restrict these functions. If such mechanisms are present they are listed in the SAB address map section. 35.5.1.1 Notation Table 35-9 on page 944 shows bit patterns to be shifted in a format like " peb01 ". Each character corresponds to one bit, and eight bits are grouped together for readability.
Page 945 AT32UC3A3 Table 35-9. Instruction Description (Continued) Instruction Description Shows the number of bits in the data register chain when this instruction is active. DR Size Example: 34 bits Shows which bit pattern to shift into the data register in the Shift-DR state when this instruction is active.
Page 946 AT32UC3A3 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6.
Page 947 AT32UC3A3 35.5.2.4 INTEST This instruction selects the boundary-scan chain as Data Register for testing internal logic in the device. The logic inputs are determined by the boundary-scan chain, and the logic outputs are captured by the boundary-scan chain. The device output pins are driven from the boundary-scan chain.
Page 948 AT32UC3A3 9. Return to Run-Test/Idle. Table 35-14. CLAMP Details Instructions Details IR input value 00110 (0x06) IR output value p0001 DR Size DR input value DR output value 35.5.2.6 BYPASS This instruction selects the 1-bit Bypass Register as Data Register. Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way: 1.
Page 949 AT32UC3A3 Starting in Run-Test/Idle, OCD registers are accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4.
Page 950 AT32UC3A3 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a write operation, scan in the new contents of the register. 9. Return to Run-Test/Idle. For any operation, the full 7 bits of the address must be provided.
Page 951 AT32UC3A3 The size field is encoded as i Table 35-18. Table 35-18. Size Field Semantics Size field value Access size Data alignment Address modulo 4 : data alignment 0: dddddddd xxxxxxxx xxxxxxxx xxxxxxxx Byte (8 bits) 1: xxxxxxxx dddddddd xxxxxxxx xxxxxxxx 2: xxxxxxxx xxxxxxxx dddddddd xxxxxxxx 3: xxxxxxxx xxxxxxxx xxxxxxxx dddddddd Address modulo 4 : data alignment...
Page 952 AT32UC3A3 Table 35-19. MEMORY_SIZED_ACCESS Details (Continued) Instructions Details DR output value (Address phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb DR output value (Data read phase) xxxxxeb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb 35.5.3.4 MEMORY_WORD_ACCESS This instruction allows access to the entire Service Access Bus data area.
Page 953 AT32UC3A3 Table 35-20. MEMORY_WORD_ACCESS Details (Continued) Instructions Details DR output value (Address phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb DR output value (Data read phase) xeb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb 35.5.3.5 MEMORY_BLOCK_ACCESS This instruction allows access to the entire SAB data area.
Page 954 AT32UC3A3 Table 35-21. MEMORY_BLOCK_ACCESS Details (Continued) Instructions Details DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb The overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% trans- fer efficiency, or 2.1 MBytes per second with a 20 MHz TCK frequency.
Page 955 AT32UC3A3 6. Scan in an 16-bit counter value. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: Scan out the busy bit, and until the busy bit clears goto 7. 9. Calculate an approximation to the internal clock speed using the elapsed time and the counter value.
Page 956 AT32UC3A3 Table 35-24. AVR_RESET Details (Continued) Instructions Details DR Size Device specific. DR input value Device specific. DR output value Device specific. 35.5.3.9 CHIP_ERASE This instruction allows a programmer to completely erase all nonvolatile memories in a chip. This will also clear any security bits that are set, so the device can be accessed normally. In devices without non-volatile memories this instruction does nothing, and appears to complete immediately.
Page 957 AT32UC3A3 6. In Shift-DR: Scan in the value 1 to halt the CPU, 0 to start CPU execution. 7. Return to Run-Test/Idle. Table 35-26. HALT Details Instructions Details IR input value 11100 (0x1C) IR output value p0001 DR Size 1 bit DR input value DR output value 32072H–AVR32–10/2012...
Page 958 The part number is a 16 bit code identifying the component. Manufacturer ID The Manufacturer ID is a 11 bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is 0x01F. •Device specific ID codes The different device configurations have different JTAG ID codes, as shown in Table 35-27.
Page 959 I/O pins, as well as driving and observing the logic levels between the digital I/O pins and the internal logic. Typically, output value, output enable, and input data are all available in the boundary scan chain. The boundary scan chain is described in the BDSL (Boundary Scan Description Language) file available at the Atmel web site. 32072H–AVR32–10/2012...
Page 960 AT32UC3A3 36. Electrical Characteristics 36.1 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Operating Temperature........-40°C to +85°C Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ........-60°C to +150°C functional operation of the device at these or other conditions beyond those indicated in the Voltage on Input Pin...
Page 961 AT32UC3A3 36.2 DC Characteristics The following characteristics are applicable to the operating temperature range: T = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up toT = 100°C. Table 36-1. DC Characteristics Symbol Parameter Conditions Min.
Page 962 AT32UC3A3 36.2.1 I/O Pin Output Level Typical Characteristics Figure 36-1. I/O Pin drive x2 Output Low Level Voltage (VOL) vs. Source Current VddIo = 3.3V Load current [mA] Figure 36-2. I/O Pin drive x2 Output High Level Voltage (VOH) vs. Source Current VddIo = 3.3V Load current [mA] 36.3...
Page 963 AT32UC3A3 Table 36-2. Normal I/O Pin Characteristics Symbol Parameter Conditions drive x2 drive x2 drive x3 Unit 10pf Output frequency 30pf 18.2 35.7 61.6 60pf 18.5 36.3 10pf Rise time 30pf RISE 60pf 13.4 10pf Fall time 30pf 2.26 FALL 60pf 16.5 36.4...
Page 964 AT32UC3A3 36.5 Analog characteristics 36.5.1 Table 36-5. Electrical Characteristics Symbol Parameter Conditions Min. Typ. Max. Unit Analog Power Supply VDDANA Table 36-6. Decoupling Requirements Symbol Parameter Conditions Typ. Technology Unit Power Supply Capacitor VDDANA 36.5.2 Table 36-7. 1.8V BOD Level Values Symbol Parameter Value Conditions...
Page 965 AT32UC3A3 Table 36-9. BOD Timing Symbol Parameter Conditions Min. Typ. Max. Unit Minimum time with VDDCORE < Falling VDDCORE from 1.8V to 1.1V VBOD to detect power failure 36.5.3 Reset Sequence Table 36-10. Electrical Characteristics Symbol Parameter Conditions Min. Typ. Max.
Page 966 AT32UC3A3 Figure 36-3. MCU Cold Start-Up VDDIN BOD33LEVEL BOD33LEVEL VDDIO RESTART RESET_N Internal BOD33 Reset SSU1 Internal MCU Reset Figure 36-4. MCU Cold Start-Up RESET_N Externally Driven VDDIN BOD33LEVEL BOD33LEVEL VDDIO RESTART RESET_N Internal BOD33 Reset SSU1 Internal MCU Reset Figure 36-5.
Page 967 AT32UC3A3 36.5.4 RESET_N Characteristics Table 36-11. RESET_N Waveform Parameters Symbol Parameter Conditions Min. Typ. Max. Unit RESET_N minimum pulse width RESET 32072H–AVR32–10/2012...
Page 968 AT32UC3A3 36.6 Power Consumption The values in Table 36-12 Table 36-13 on page 970 are measured values of power con- sumption with operating conditions as follows: •V = 3.3V DDIO •T = 25°C •I/Os are configured in input, pull-up enabled. Figure 36-6.
Page 969 AT32UC3A3 Power Consumtion for Different Sleep Modes 36.6.1 Table 36-12. Power Consumption for Different Sleep Modes Mode Conditions Typ. Unit - CPU running a recursive Fibonacci Algorithm from flash and clocked from PLL0 at f MHz. - Flash High Speed mode disable (f < 66 MHz) - Voltage regulator is on.
Page 970 AT32UC3A3 Table 36-13. Typical Cuurent Consumption by Peripheral Peripheral Typ. Unit ABDAC DMACA GPIO INTC PDCA µA/MHz SDRAM TWIM TWIS USART USBB 32072H–AVR32–10/2012...
Page 971 AT32UC3A3 36.7 System Clock Characteristics These parameters are given in the following conditions: • V = 1.8V DDCORE 36.7.1 CPU/HSB Clock Characteristics Table 36-14. Core Clock Waveform Parameters Symbol Parameter Conditions Min. Typ. Max. Unit 1/(t CPU Clock Frequency -40°C < Ambient Temperature < 70°C CPCPU 1/(t CPU Clock Frequency...
Page 972 AT32UC3A3 36.8 Oscillator Characteristics The following characteristics are applicable to the operating temperature range: T = -40°C to 85°C and worst case of power supply, unless otherwise specified. 36.8.1 Slow Clock RC Oscillator Table 36-17. RC Oscillator Frequency Symbol Parameter Conditions Min.
Page 973 AT32UC3A3 36.8.3 Main Oscillators Table 36-19. Main Oscillators Characteristics Symbol Parameter Conditions Min. Typ. Max. Unit External clock on XIN 1/(t Oscillator Frequency CPMAIN Crystal Internal Load Capacitance (C Ω Crystal Equivalent Series Resistance Duty Cycle f = 400 KHz f = 8 MHz Startup Time f = 16 MHz...
Page 974 AT32UC3A3 36.9 ADC Characteristics Table 36-22. Channel Conversion Time and ADC Clock Parameter Conditions Min. Typ. Max. Unit 10-bit resolution mode ADC Clock Frequency 8-bit resolution mode Startup Time Return from Idle Mode µs Track and Hold Acquisition Time ADC Clock = 5 MHz µs Conversion Time ADC Clock = 8 MHz...
Page 975 AT32UC3A3 Table 36-26. Transfer Characteristics in 10-bit mode Parameter Conditions Min. Typ. Max. Unit Resolution Absolute Accuracy ADC Clock = 5 MHz Integral Non-linearity ADC Clock = 5 MHz ADC Clock = 5 MHz Differential Non-linearity ADC Clock = 2.5 MHz Offset Error ADC Clock = 5 MHz Gain Error...
Page 976 FS/HS Transceiver current FS transmission 5m cable consumption FS/HS Transceiver current FS reception consumption Including 1 mA due to Pull-up/Pull-down current consumption. 34.5.5 USB High Speed Design Guidelines In order to facilitate hardware design, Atmel provides an application note on www.atmel.com. 32072H–AVR32–10/2012...
Page 977 AT32UC3A3 36.11 EBI Timings 36.11.1 SMC Signals These timings are given for worst case process, T = 85⋅C, VDDIO = 3V and 40 pF load capacitance. Table 36-30. SMC Clock Signal Symbol Parameter Max. Unit 1/(t SMC Controller Clock Frequency 1/(t CPSMC cpcpu...
Page 978 AT32UC3A3 Table 36-32. SMC Read Signals with no Hold Settings Symbol Parameter Min. Unit NRD Controlled (READ_MODE = 1) Data Setup before NRD High 13.7 Data Hold after NRD High NRD Controlled (READ_MODE = 0) Data Setup before NCS High 13.3 Data Hold after NCS High Table 36-33.
Page 979 AT32UC3A3 Table 36-34. SMC Write Signals with No Hold Settings (NWE Controlled only) Symbol Parameter Min. Unit Data Out Valid before NWE Rising (nwe pulse length - 1) * t - 1.2 CPSMC Data Out Valid after NWE Rising NWE Pulse Width nwe pulse length * t - 0.9 CPSMC...
Page 980 AT32UC3A3 Figure 36-8. SMC Signals for NRD and NRW Controlled Accesses. SMC37 SMC7 SMC7 SMC31 A2-A25 SMC3 SMC38 SMC3 SMC25 SMC4 SMC39 SMC4 SMC26 SMC5 SMC40 SMC5 SMC29 SMC6 SMC41 SMC6 SMC30 A0/A1/NBS[3:0] SMC42 SMC8 SMC32 SMC8 SMC9 SMC9 SMC24 SMC19 SMC20 SMC23...
Page 981 AT32UC3A3 Table 36-36. SDRAM Clock Signal Symbol Parameter Conditions Min. Max. Unit SDRAMC Bank Change before SDCK Rising Edge SDRAMC Bank Change after SDCK Rising Edge SDRAMC CAS Low before SDCK Rising Edge SDRAMC CAS High after SDCK Rising Edge SDRAMC DQM Change before SDCK Rising Edge SDRAMC...
Page 982 AT32UC3A3 Figure 36-9. SDRAMC Signals relative to SDCK. SDCK SDRAMC SDRAMC SDRAMC SDRAMC SDCKE SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDCS SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDWE SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDA10 SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC...
Page 983 AT32UC3A3 36.12 JTAG Characteristics 36.12.1 JTAG Interface Signals Table 36-37. JTAG Interface Timing Specification Symbol Parameter Conditions Min. Max. Unit JTAG TCK Low Half-period JTAG TCK High Half-period JTAG TCK Period JTAG TDI, TMS Setup before TCK High JTAG TDI, TMS Hold after TCK High JTAG TDO Hold Time JTAG...
Page 984 AT32UC3A3 Figure 36-10. JTAG Interface Signals JTAG JTAG JTAG TMS/TDI JTAG JTAG JTAG JTAG Device Inputs JTAG JTAG Device Outputs JTAG JTAG 36.13 SPI Characteristics Figure 36-11. SPI Master mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1) SPCK MISO MOSI 32072H–AVR32–10/2012...
Page 985 AT32UC3A3 Figure 36-12. SPI Master mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK MISO MOSI Figure 36-13. SPI Slave mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK MISO MOSI Figure 36-14.
Page 986 AT32UC3A3 Table 36-38. SPI Timings Symbol Parameter Conditions Min. Max. Unit MISO Setup time before SPCK rises 22 + 3.3V domain (master) CPMCK MISO Hold time after SPCK rises 3.3V domain (master) SPCK rising to MOSI Delay 3.3V domain (master) MISO Setup time before SPCK falls 22 + 3.3V domain...
Page 987 AT32UC3A3 36.15 Flash Memory Characteristics The following table gives the device maximum operating frequency depending on the field FWS of the Flash FSR register. This field defines the number of wait states required to access the Flash Memory. Flash operating frequency equals the CPU/HSB frequency. Table 36-39.
Page 988 AT32UC3A3 37. Mechanical Characteristics 37.1 Thermal Considerations 37.1.1 Thermal Data Table 37-1 summarizes the thermal resistance data depending on the package. Table 37-1. Thermal Resistance Data Symbol Parameter Condition Package Unit θ Junction-to-ambient thermal resistance Still Air TQFP144 40.3 °C/W θ...
Page 989 AT32UC3A3 37.2 Package Drawings Figure 37-1. TFBGA 144 package drawing 32072H–AVR32–10/2012...
Page 990 AT32UC3A3 Figure 37-2. LQFP-144 package drawing Table 37-2. Device and Package Maximum Weight 1300 Table 37-3. Package Characteristics Moisture Sensitivity Level MSL3 Table 37-4. Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification 32072H–AVR32–10/2012...
Page 991 AT32UC3A3 Figure 37-3. VFBGA-100 package drawing 32072H–AVR32–10/2012...
Page 992 AT32UC3A3 37.3 Soldering Profile Table 37-5 gives the recommended soldering profile from J-STD-20. Table 37-5. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/Second max Preheat Temperature 175°C ±25°C 150-200°C Time Maintained Above 217°C 60-150 seconds Time within 5°C of Actual Peak Temperature 30 seconds Peak Temperature Range...
Page 993 AT32UC3A3 38. Ordering Information Temperature Operating Device Ordering Code Package Conditioning Range AT32UC3A3256S AT32UC3A3256S-ALUT 144-lead LQFP Tray Industrial (-40⋅C to 85⋅C) AT32UC3A3256S-ALUR 144-lead LQFP Reels Industrial (-40⋅C to 85⋅C) AT32UC3A3256S-CTUT 144-ball TFBGA Tray Industrial (-40⋅C to 85⋅C) AT32UC3A3256S-CTUR 144-ball TFBGA Reels Industrial (-40⋅C to 85⋅C)
Page 994 AT32UC3A3 39. Errata 39.1 Rev. H 39.1.1 General Devices with Date Code lower than 1233 cannot operate with CPU frequency higher than 66MHz in 1WS and 36MHz in 0WS in the whole temperature range Fix/Workaround None DMACA data transfer fails when CTLx.SRC_TR_WIDTH equal...
Page 995 AT32UC3A3 For higher polling time, the software must freeze the pipe for the desired period in order to prevent any "extra" token. 39.1.4 Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion.
Page 996 AT32UC3A3 SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled.
Page 997 AT32UC3A3 URAD (Unspecified Register Access Detection Status) does not detect read accesses to the write-only KEYW[5..8]R registers Fix/Workaround None. 39.1.6 HMATRIX In the PRAS and PRBS registers, the MxPR fields are only two bits In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits. The unused bits are undefined when reading the registers.
Page 998 AT32UC3A3 Fix/Workaround None. Frame Synchro and Frame Synchro Data are delayed by one clock cycle The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when: - Clock is CKDIV - The START is selected on either a frame synchro edge or a level - Frame synchro data is enabled - Transmit clock is gated on output (through CKO field) Fix/Workaround...
Page 999 AT32UC3A3 DMACA data transfer fails when CTLx.SRC_TR_WIDTH equal CTLx.DST_TR_WIDTH Fix/Workaround For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH. 3.3V supply monitor is not available FGPFRLO[30:29] are reserved and should not be used by the application. Fix/Workaround None. Service access bus (SAB) can not access DMACA registers Fix/Workaround None.
Page 1000 AT32UC3A3 39.2.3 Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 39.2.4 USART ISO7816 info register US_NER cannot be read...

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