NP Address Bus (NPA5-NPA0)
This TTL-level input bus is used to select an appropriate register in the chip. NPA0 is
the least significant bit in the address; NPA5 is the most significant bit.
NP Read/Write (NPRW)
This TTL-level input signal is used to determine whether the NP is reading a register
(NPRW high ≥ MAC drives the NPDx bus) or writing a register (NPRW low ≥ NP drives
the NPDx bus).
NP Data Bus (NPD15–NPD0)
This bidirectional three-state bus (TTL-level input, CMOS-level output) is used to read or
write 16 bits of data from or into a MAC register.
4.3 MAC-PHY INTERFACE
The MAC-PHY interface has a receive bus and a transmit bus that link the MAC chip to
the ELM chip. These buses are synchronous to BYTCLK.
Receive Data Bus (RCDAT9–RCDAT0)
This 10-bit TTL-level bus is used to receive a symbol pair from the PHY layer device
(ELM). This bus can be divided into two sub-buses:
1. RCDAT9–RCDAT5 corresponds to the first symbol of the pair received from the
2. RCDAT4–RCDAT0 corresponds to the last symbol of the pair received from the
The behavior of the MAC is undefined if presented with a symbol encoding that is not
listed in the data link code column of Table 6-1. The PHY layer should pass the coding
for a violation symbol when it detects an elasticity buffer overflow condition.
Transmit Data Bus (TXDAT9–TXDAT0)
This 10-bit CMOS-level bus is used to transmit a symbol pair from the MAC to the PHY
layer device (ELM). This bus can be divided into two sub-buses:
1. TXDAT9–TXDAT5 corresponds to the first symbol of the pair transmitted to the
2. TXDAT4–TXDAT0 corresponds to the last symbol of the pair transmitted to the
When they are not transmitting, these lines drive the FDDI idle data link code of 10111.
4.4 RECEIVE SYSTEM INTERFACE
The receive system interface provides the data path from the MAC to the FSI.
MC68838 USER'S MANUAL