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Mac-Phy Interface Operation - Motorola MC68838 User Manual

Media access controller
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SECTION 6

MAC-PHY INTERFACE OPERATION

The MAC-PHY interface links the MAC chip to the ELM. These buses are synchronous
with BYTCLK. There is no parity on the MAC-PHY interface since the data is protected by
the packet's FCS field (a 32-bit CRC).
The MAC will never generate a halt (H), quiet (Q), or violation (V) symbol nor signal a
PHY_INVALID to the PHY layer (ELM). The response of the MAC is undefined when it is
passed a code that is not listed in the data link code column of Table 6-1. The highest
order bit (bit 9) is the first bit of the symbol pair sent out on the PHY media on TXDATx
and the first bit received from the PHY media on RCDATx. The data symbol pair on
RCDATx and TXDATx is encoded in data link form as shown in Table 6-1
MOTOROLA
Table 6-1. RCDATx/TXDATx Encoding
Data Link
Symbol
Code
0
00000
1
00001
2
00010
3
00011
4
00100
5
00101
6
00110
7
00111
8
01000
9
01001
A
01010
B
01011
C
01100
D
01101
E
01110
F
01111
MC68838 USER'S MANUAL
Data Link
Symbol
Code
H
10100
H
10100
H
10100
H
10100
H
10100
I
10111
J
11100
K
10011
Q
10000
R
10001
S
11001
T
11101
V
11000
V
11000
V
11000
V
11000
6-1

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