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Cam Interface Timing - Motorola MC68838 User Manual

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11.8 CAM INTERFACE TIMING

Num
30
MATCH/TR_BR_FWD Setup Time
MATCH/TR_BR_FWD Hold Time
31
32
BYTCLK to LDADDR Valid
33
BYTCLK to LDADDR Invalid
BYTCLK to ADDR16 Negated, Low to High
34
BYTCLK to ADDR16 Asserted, High to Low
35
36
BYTCLK to DA Asserted
37
BYTCLK to DA Negated
NOTES:
1. All signals are shown relative to the rising edge of BYTCLK.
2. Only the timing of the DA match indication is given. The SA match indication would need to be provided to the MAC
six bytes later with the same relative timing for the proper SA actions to occur.
3. ADDR16 only changes, if necessary, with the BYTCLK cycle on the receipt of the second byte of the DA and
remains level until a different address size is detected on a following address cycle; thus, two timing values are
given, 34 and 35, for the possible transitions.
4. Figure 11-4 shows timing requirements for the CAM interface signal timing. This figure is drawn based on the
functional timing required when EXT_DA_MATCH = 0. For other functional timing, see Section 9.
BYTCLK
SYMCLK
RCDAT
MATCH
TR_BR_FWD
LDADDR
ADDR16
DA
11-6
(see Figure 11-4)
Characteristics
80 NS
FC
DA1
DA2
33
32
34
35
36
Figure 11-4. CAM Interface Timing
MC68838 USER'S MANUAL
DA5
DA6
SA1
30
37
Min
M a x
Unit
40
ns
5
ns
40
ns
4
ns
25
ns
2
ns
25
ns
2
ns
SA2
31
MOTOROLA

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