Counter Registers - Motorola MC68838 User Manual

event register. When a bit in this register is set and the corresponding bit in the interrupt
event register is also one, an interrupt is generated. This register is only read by the MAC
chip. lt can be read and written by the NP at any time. lt is cleared on power-up reset and
is unaffected by a MAC_RESET.

3.4 COUNTER REGISTERS

The three counter registers, the frame count register, lost count register field, token count
register, and error count register field are incremented as described in the FDDI standard.
The frame count register counts all frames where a frame is defined as one of the
following:
1. A JK followed by a nontoken FC (i.e., two data symbols)
2. Zero or more additional data symbols (including an odd number)
3. A T-symbol
The lost count register field is incremented for all format errors where a format error is
defined as a JK followed by zero or more data symbols and is not a frame, fragment, or a
token. A fragment is defined as a JK followed by zero, more data symbols followed by an
idle symbol, or a JK followed by a token FC followed by a T-symbol followed by an idle
symbol. A token is defined as a JK followed by a token FC followed by two T-symbols
followed by anything other than a PHY_INVALID.
The error count register field is incremented for all locatable errors where a locatable error
is defined according to the received E-indicator. The received E-indicator is defined as the
symbol after the T-symbol that ends a frame. There is no locatable error if there is no
frame. If the received E-indicator is an S-symbol, then the error count register field is never
incremented. If the received E-indicator is missing (i.e., not an R-symbol or S-symbol),
then the error count register field is always incremented. If the received E-indicator is an
R-symbol, then the error count register field is only incremented if the frame has an invalid
data length (i.e., odd number of symbols or too short for this FC type) or has an incorrect
FCS (where the FCS for implementor frames is defined as always correct). This MAC
limits void frames to the same length requirements as an LLC frame and requires a valid
CRC.
The lost count, error count and frame count registers are always cleared when read. Also,
if these registers are read and cleared in the same cycle that they are incremented, the
register will have a one value instead of a zero value at the end of the cycle. Hence these
registers can be read at any time by the NP without losing count.
These registers are not intended to hold the complete counts of frames, format errors, and
Iocatable errors for network management purposes. They are far too short (e.g., the full
frame count register should be at least 48 bits long). Instead, SMT software should keep
the full counters. These counters are used to eliminate the real time requirements of the
software. Instead of requiring the software to guarantee an interrupt latency of less than 5
µs, due to possible event frequency, these counters keep track of the number of events
that occur during a much larger interrupt latency time.
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