3.5.2 My Long Address Register (MLA_A, MLA_B, MLA_C)
My long address register is contained in three 16-bit registers. The least significant 16 bits
(MLA_A) have register address 11, the middle 16 bits (MLA_B) have register address 12,
and the most significant 16 bits, MLA_C, which contains the l/G and U/L, have register
address 13. Within each register, bit 0 is the least significant bit and bit 15, the most
significant bit. This bit ordering is unaffected by the value of REVERSE_ADDR in control
register A as that bit reversal occurs only across the FSI bus.
The NP requires three read/write operations to completely read/write the 48-bit my long
address register. The read/write operations do not have to be consecutive since these
registers can only be changed by the NP.
3.5.3 Target Request Time Register (T_REQ)
The target request time register is a 16-bit register that holds the twos complement of this
station's desired target token rotation time in 20.48-µs units (20.48 µs = 256 × 80 ns) to a
maximum of 1342.1568 ms.
The target request time register should normally indicate a time between 1 and 10 ms and
must indicate a time smaller than T_MAX (this is not checked by the chip and, if false, the
FDDI ring protocol may be violated). A typical value would be 4.014080 ms, obtained by
assigning 196 (FF3C in hex) to the target request time register. This would cause the MAC
to send claim frames with an INFO field of FF FF 3C 00.
3.5.4 TVX, TRT Initial Timer Parameter Register (TVX_VALUE, T_MAX)
The 8-bit TVX_Value and 8-bit T_Max register fields are contained in one 16-bit
addressable register. T_Max occupies bits 7–0 of this register, and TVX_Value occupies
bits 15–8; bits 8 and 0 are the least significant, and bits 15 and 7 are the most significant
bits of each register.
MLA (LEAST SIGNIFICANT)
MC68838 USER'S MANUAL
MLA (MOST SIGNIFICANT)