Overview; Chip Features - Motorola MC68838 User Manual

1.1 OVERVIEW

The MAC chip transmits information to and receives information from the physical layer
as a symbol pair every 80 ns, where a symbol is either a nibble (4 bits) of data or a
control symbol. lt does this using separate transmit and receive buses, each composed
of 10 data signal lines. Transfers on the FSI transmit and receive buses are synchronous
with the 80-ns clock (BYTCLK). The MAC chip also has an NPI enabling an external
processor to read and write registers, which allows the processor full control of
management facilities.

1.2 CHIP FEATURES

The following is a list of the MAC chip's features:
• Completely Implements the ANSI FDDI MAC Standard
• Independent Receive and Transmit Data Paths and State Machines Can
Simultaneously Generate and Check CRC
• Supports 16-Bit or 48-Bit Individual Station Addresses On Chip
• Contains an Interface to a CAM for Individual and Multicast Address Recognition
• Supports Several Bridging Facilities:
— Can Reverse Bit Ordering on DA and SA
— Contains Count and Void Frame Bridge Stripping Algorithm On Chip
— Allows Generating Frame CRC on per Frame Basis
— Supports A and C Bit Handling for Transparent Bridging Mode
— Supports Extended Address Recognition Timing for Address Recognition
• Supports Optional FDDI Standard Capabilities Such As:
— Receipt of Additional Frame Status Indicators
— Restricted Tokens
— Synchronous Frames
• On-Chip Counters Support Station and Network Management Functions
— Token Counter
— Frame Counter
— Last Frame and Error Counter
— Void Timer for Latency Calculations
• Contains an NPI
• Contains Extensive Self-Test Capabilities, Scan Path Logic, and Data Parity
Generation and Checking
• High-Speed CMOS Technology
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