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Functional Description; Node Processor Interface Logic; Receive Data Path - Motorola MC68838 User Manual

Media access controller
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SECTION 2

FUNCTIONAL DESCRIPTION

There are four functional logic domains in the MAC chip: the NPI, the receive data path,
the transmit data path, and the clock and test logic.

2.1 NODE PROCESSOR INTERFACE LOGIC

The function of the NPI is to provide a mechanism for an external processor to control the
MAC chip and receive status information and interrupt notifications. The NPI contains the
global command/status registers, an address decoder, the data latches, and the
controlling logic.
The NPI has an address bus with an associated read/write line and a bidirectional 16-bit
data bus. An interrupt line can notify an external processor of the occurrence of some
event.

2.2 RECEIVE DATA PATH

The receive data path is the internal data bus associated with receiving packets from the
ring. lt connects to the external RCDATx bus (data bus from the ELM chip) through a
pipeline latch in the receive latch logic and to the RPATHx (data bus to the FSI chip).
Only the receive data latch containing the current received symbol pair drives this
internal data bus. Usually several different logic blocks are concurrently reading and
processing this symbol pair. These logic blocks perform the following functions:
• Decode the input symbol pair, recognize the beginning of frames, and use this
information to run the receiver FSM.
• Compare the DA field of a received packet to this station's individual 16- or 48-bit
address.
• Compare the SA field of a received packet to this station's individual 16- or 48-bit
address.
• Run the external CAM address matching logic.
• Compare the INFO field of claim frames to this station's requested token rotation
time.
• Perform CRC checking on the received packet.
• Store the frame status indicators that have been received.
• Keep a count of the number of good and bad frames received.
MOTOROLA
MC68838 USER'S MANUAL
2-1

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