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Motorola MC68838 User Manual page 25

Media access controller
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SET_BIT5—Set Bit 5
Repeat fifth control indicator as an S-symbol.
0 = The fifth control indicator is repeated exactly as received.
1 = The repeating function always causes the fifth control indicator received to be
transmitted as an S-symbol. If the fifth received control indicator is already an
S-symbol, then the BIT5_I_SS interrupt is signaled. Nothing happens if there are
not five control indicators.
SET_BIT4—Set Bit 4
Repeat fourth control indicator as an S-symbol.
0 = The fourth control indicator is repeated exactly as received.
1 = The repeating function always causes the fourth control indicator received to be
transmitted as an S-symbol. If the fourth received control indicator is already an
S-symbol, then the BIT4_I_SS interrupt is signaled. Nothing happens if there are
not four control indicators.
REVERSE_ADDR—Reverse the DA and SA Fields of All Frames
This bit is used by both the receiver and transmitter portion of the MAC. This bit reversal
only occurs across the FSI bus; hence, it does not affect the CRC checking/generation
nor the interpretation of the my long address or my short address registers, etc. The
order of the octets is not affected by this bit. Octets are passed to and from the FSI in
the same order as they appear on the fiber.
0 = No bit reversal will occur.
1 = The MAC chip will reverse the bit order of data octets passed to and from the FSI
(i.e., across RPATHx and TPATHx for all octets that make up the DA and SA
fields of all frames to be sent or received from the FSI). Therefore, for DA and SA
octets, bit (7–x) is passed to the FSI on RPATHx, and bit (7–x) is obtained from
the FSI on TPATHx.
This feature is useful when implementing 802.3 and 802.4 protocol bridges to FDDI and
vice versa.
FLUSH_SA47—Flush Source Routing Frames
0 = The MAC will copy frames when the individual/group bit of the SA (bit 47 of
48-bit addresses or bit 15 of 16-bit addresses) is one.
1 = The MAC will not copy frames when the individual/group bit of the SA (bit 47 of
48-bit addresses or bit 15 of 16-bit addresses) is one.
This bit has no effect on the ring protocols. ln particular, it does not change the frame
stripping algorithms nor affect whether a claim frame is higher or lower. When
comparing the SA of a received frame to the my long address register, the I/G of the
received SA and the my long address register are ignored—i.e., the l/G bit of the
received SA is always considered a match, regardless of the value of FLUSH_SA47 or
the my long address register. On the other hand, bit 47 of the my long address register
is used for DA matches. FLUSH_SA47 has no effect when COPY_ALL is 10 or 11 or
when NSA frames are received (i.e., NSA source routing frames will still be received).
The current ANSI MAC standard requires the individual/group bit of the SA to be zero.
MOTOROLA
MC68838 USER'S MANUAL
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