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RABORT2— ADDR16 or RABORT2 Signal Selection
0 = ADDR16 pin operates as ADDA16 , an output, as defined in the signal
definitions.
1 = ADDR16 pin operates as RABORT2, an input, with the same functionality as the
RABORT input pin—that is, it signals the MAC that the incoming frame should be
aborted. RABORT2 is internally ORed with RABORT.
This bit is set on power up.
To use the ADDR16 signal, the user (initialization firmware) must clear this bit.
MAC_MODE_CTL—MAC A and C Frame Status Bit Handling Option
This bit defines how the MAC sets, resets, or repeats the C-indicator bit when RABORT
or RABORT2 occurs while the MAC is receiving a frame addressed to itself or
recognized as receivable by itself.
0 = Option 1. Set the A and C bits according to the MAC_MODE_CTL = 0 functions
as defined in Table 9-1.
1 = Option 2. Set the A and C bits according to the MAC_MODE_CTL = 1 function as
defined in Table 9-1.
3.2.3 Receive Status Register (RX_STATUS)
The receive status register holds the status flags, the comparison state (e.g., the H_Flag,
L_Flag, and M_Flag), the receiver FSM state, and the decoded FC. The NP can read the
receive status register at any time but can never write to this register. It is cleared on
power-up reset and by a MAC_Reset. The flags displayed in this register are internal flags
used as described in the ANSI FDDI MAC standard.
15
14
RX_FSM_STATE
7
6
N_FLAG
RX_FSM_STATE—Receiver Finite State Machine State
This state machine controls the overall operation of the MAC receiver.
000 = Await_Sd (R1)—Wait for JK of new frame
001 = Rc_FS (R4)—Receive and decode FS
010 = Rc_FC (R2)
011 = Rc_Info (R3)—Receive DA, SA, INFO, and CRC
100 = Chk_TK2 (R5')—State used to repeat TT
101 = Listen (R0)—Wait for first idle
110 = Chk_TK1 (R5)—Receive TT of token
111 = Rc_Off—MAC is turned off
MOTOROLA
13
12
R_FLAG
5
4
FR_PARS_STATE
Receive and decode FC byte
—
MC68838 USER'S MANUAL
11
10
E_FLAG
3
2
L_FLAG
H_FLAG
9
8
FSM_STATE
1
0
M_FLAG
A_FLAG
3- 13
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