Control And Status Registers - Motorola MC68838 User Manual

Whenever the NP attempts to write to a nonexistent register, a read-only register, a read-
only/clear register, or a read/control write register when the FSMs are on, then the MAC
completes the NP write cycle normally (though no registers are modified) and records the
event by setting the NP_ERR bit.
All unused bits (i.e., undefined bits) in the MAC registers are read as zero and are ignored
when written. However, software should always write these unused bits as zeros and
should assume that these bits have unpredictable values upon reading.
All timing values are stored as the unsigned twos complements of the target or as
remaining time in octets (i.e., 80-ns units). Hence, the numerically greater magnitude
represents the shortest time remaining. For example, if the TVX timer has 240 ns left until
expiration, the time remaining would be three octets, and the 16-bit TVX register would
contain 1111 1111 1111 1101.

3.2 CONTROL AND STATUS REGISTERS

There are two control registers and two status registers for receive and transmit functions.
3.2.1 Control Register A (MAC_CNTRL_A)
Control register A controls the receiver portion of the MAC and a few joint
receiver/transmitter aspects. The NP can read and write control register A at any time. The
MAC chip never modifies this register. It is cleared on power-up reset and unaffected by a
MAC_Reset.
2 14
MAC_ON SET_BIT_5
7 6
COPY_EXTRA_SMT
MAC_ON—MAC On
This bit turns the receiver/transmitter FSM on or off. When set to one, the receiver finite
state machine transitions to the listen state (state R0) and the transmitter finite state
machine transitions to the Tx_Idle state (state T0).
0 = Both the receiver and transmitter FSM are turned off. When in this state, the MAC
receiver/transmitter ignores all inputs and stays in this state until MAC_ON is set.
When they are operating, the receiver and transmitter can be turned off at any
time by clearing this bit. (No timers are running).
1 = The receiver and transmitter finite state machines are operating and can be in
any of the states R0–R5 or T0–T5, respectively, or in the FDX states (All timers
are running).
3- 4
13 12
SET_BIT_4 REVERSE_
ADDR
5 4
COPY_IND_ COPY_GRP_
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11 10
FLUSH_SA47 COPY_ALL
3 2
DSABL_ RUN_BIST
BRDCST
9 8
COPY_OWN
1 0
RX_PARITY NTE_AL_FRMS
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