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T_Max holds the twos complement of the TRT timeout to be used when the ring is not
operational (i.e., value of T_Opr when RING_OPERATIONAL is false) in 5.242880-ms
units (where 5.24288 ms = 2
bits wide, and represents time in octets (80 ns). When the chip is required to assign
T_Max to T_Opr, bits 0–7 of register 15 are assigned to bits 16–23 of T_Opr, and bits 0–
15 of T_Opr are cleared. The chip does not check that the absolute value of the target
request time register is less than the absolute value of T_Max. This is left for SMT
software and must be checked. These registers are cleared on power-up reset. A
suggested default value is 32 (E0 in hex), representing 167.77216 ms.
The TVX_Value register field is used to load the TVX timer when that timer is reset. The
TVX_Value register field holds the twos complement of the time remaining in 20.48-µs
units (where 20.48 µs = 256 × 80 ns) to a maximum of 5.2224 ms. Since the TVX timer is
16-bits wide and is incremented every 80 ns, the 8-bit TVX_Value equals the most
significant 8 bits of the TVX timer (the lower 8 bits are zero) when it is reset. The default of
TVX_Value is 128 (80 in hex), representing 2.62144 ms, but must be programmed.
15
7
3.6 PROTOCOL TIMING REGISTERS
The following registers are not normally of interest to the NP, although they can be read at
any time (subject to the fact that it can take more than one read operation to obtain their
value and that they can change values between these reads). These registers cannot be
directly written by the NP.
The protocol timing registers include the three FDDI-defined timers (TVX_Timer,
TRT_Timer, and THT_Timer), in addition to the target rotation time remaining register, the
information field register, and the SENT_COUNT register.
3.6.1 TVX Timer Register (TVX_TIMER)
The TVX timer register is a 16-bit counter. lt holds the twos complement of the time
remaining in 80-ns units. For example, if this register held the value FF3C (196 in
decimal), then the time remaining would be 15.68 µs.
3.6.2 TRT Timer Register (TRT_TIMER_A, TRT_TIMER_B)
The TRT timer register is a 24-bit counter that has the addresses 2C and 2D (hex). The
NP may need to read it in two consecutive register reads (only when T_OPR is ≥ 5.242880
ms). Because this register can (and usually will) change between the two read operations,
care must be taken to get a consistent value.
The least significant 16 bits of the TRT timer occupy register address 2C, and the most
significant 8 bits of the TRT timer occupy bits 7–0 of register 2D. Bits 15 and 7 are the
MOTOROLA
16
times 80 ns) to a maximum of 1336.9344 ms. T_Opr is 24-
TVX_VALUE
T_MAX
MC68838 USER'S MANUAL
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0
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