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Bus Operation; Npi Operation; Read Cycle - Motorola MC68838 User Manual

Media access controller
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The NPI serves to interface an external processor and the control and status registers
internal to the MAC. The interface is general purpose; it is not designed for a specific


The NPI operation is controlled by NPCLK. In normal operation, this clock is the same as
BYTCLK. The two clocks are separate only for diagnostics and testing. Chip operation
can be halted by stopping BYTCLK while allowing register reads via the NPCLK. There
is only a single input register to the MAC; therefore, only a single register to be updated
by a write cycle or altered (e.g., cleared) by a read cycle should be accessed when
BYTCLK is inactive. If multiple registers are accessed while BYTCLK is inactive, only the
last register accessed is properly written.
All signals in the NPI must be synchronous with NPCLK. They must be stable a setup
time before, and a hold time after, a rising edge of this clock.
The NPI supports two types of bus transactions—a read cycle and a write cycle. A read
or write transaction can occur as fast as every two NPCLK cycles (160 ns). It is possible
to extend or wait state the transaction. Read or write transactions to nonexistent registers,
writes to read-only registers, and reads of write-only registers are all considered
programming errors, and the MAC will ignore the transaction (not drive the data bus on a
read and not accept data on a write) and set the NP_ERR bit in the interrupt event
register. Some registers can only be written under certain conditions. If a write is
attempted to a register that cannot be written at that time, the NP_ERR bit is set.


The NP uses a read cycle to read data from a MAC register (see Figure 5-1). Some MAC
registers are cleared when read.
A read of a MAC register is initiated by the assertion of the MACSEL signal. The MACSEL
line is sampled by the rising edge of NPCLK. It must be asserted a setup time before and
must remain asserted for a hold time after this clock edge. The MACSEL signal may be
asserted by the host bus logic to introduce as many wait states as necessary. Once the
MACSEL line is sampled and determined to be asserted, the NPAx bus and NPRW line
are sampled (NPRW should be high for a read). These signals must also satisfy a setup
time and hold time relative to this same rising edge of NPCLK. At least 40 ns after this



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