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Motorola MC68838 User Manual

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MC68838
Media Access Controller
User's Manual
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design.
Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it
convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should
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reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
the µ are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
© MOTOROLA INC., 1992

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   Summary of Contents for Motorola MC68838

  • Page 1

    Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

  • Page 2

    68K FAX-IT FAX 512-891-8593 The Motorola High-End Technical Publication Department provides a FAX number for you to submit any questions and comments about this document. We welcome your suggestions for improving our documentation or any questions concerning our products. Please provide the part number and revision number (located in upper right-hand corner on the cover), and the title of the document when submitting.

  • Page 3: Table Of Contents

    Read/Write Registers.................. 3-3 3.1.2 Read/Control Write Registers ..............3-3 3.1.3 Read-Only/Clear Registers ............... 3-3 3.1.4 Read-Only Registers .................. 3-3 Control and Status Registers................ 3-4 3.2.1 Control Register A (MAC_CNTRL_A) ............. 3-4 3.2.2 Control Register B (MAC_CNTRL_B) ............. 3-8 MOTOROLA MC68838 USER’S MANUAL...

  • Page 4

    3.7.5 Transmit CRC Registers (TX_CRC)............3-32 Section 4 Signal Description Clock Signals ....................4-1 Node Processor Interface................4-2 MAC-PHY Interface ..................4-3 Receive System Interface................4-3 Transmit System Interface................4-4 CAM Interface....................4-5 Test Signals..................... 4-6 MC68838 USER’S MANUAL MOTOROLA...

  • Page 5

    Built-In Self-Test Operation................. 10-1 10.2 Scan Path Operation..................10-2 Section 11 Electrical Characteristics 11.1 Maximum Ratings ..................11-1 11.2 Recommended Operating Conditions ............11-1 11.3 Thermal Characteristics................11-1 11.4 Electrical Characteristics................11-2 11.5 Node Processor Interface Timing .............. 11-2 MOTOROLA MC68838 USER’S MANUAL...

  • Page 6

    Ordering Information and Mechanical Data 12.1 Ordering Information ..................12-1 12.2 Pin Assignments ................... 12-2 12.2.1 120-Lead Ceramic Pin Grid Array w/Ceramic Lid (KB) ..... 12-2 12.2.2 120-Lead Plastic Quad Gull Wing (FC) ..........12-3 12.3 Package Dimensions................... 12-4 MC68838 USER’S MANUAL MOTOROLA...

  • Page 7

    LIST OF ILLUSTRATIONS Figure P a g e Number Title Number Motorola FDDI Architecture..................1-1 MAC Block Diagram....................2-2 MAC Functional Pinout.................... 4-1 Node Processor Bus Read Cycles ................ 5-2 Node Processor Bus Write Cycles................. 5-3 Receive Data Flowchart................... 7-4 TXRDY and Packet Request Header Timing............

  • Page 8

    LIST OF TABLES Table P a g e Number Title Number MAC Registers......................3-2 RCDATx/TXDATx Encoding..................6-1 RCCTLx and RPATHx Relationship ..............7-3 MAC A and C Bit Control..................9-4 10-1 BIST Register Values..................... 10-2 viii MC68838 USER’S MANUAL MOTOROLA...

  • Page 9

    FDDI—Fiber Distributed Data Interface FDX—Full Duplex FS—Frame Status FSI—FDDI System Interface FSM—Finite State Machine INFO—Information Field LAN—Local Area Network LFSR—Linear Feedback Shift Register LLC—Logical Link Control MAC—Media Access Controller MUX—Multiplex NP—Node Processor NPA—Node Processor Address Bus MOTOROLA MC68838 USER’S MANUAL...

  • Page 10

    LIST OF ACRONYMS (Continued) NPD—Node Processor Data Bus NPI—Node Processor Interface NSA—Next Station Address PHY—Physical Layer of FDDI Standard SA—Source Address SMT—Station Management TRT—Token Rotation Time TTL—Transistor-Transistor Logic MC68838 USER’S MANUAL MOTOROLA...

  • Page 11: Introduction

    SECTION 1 INTRODUCTION The MC68838 media access controller (MAC) chip implements the MAC protocol for a station operating under the ANSI standard for FDDI LANs (see Figure 1-1). FDDI is a 125-Mbit/sec, fiber-optic-based token ring designed to accommodate rings up to 1000 stations, 2 km between stations, and 200-km total ring length.

  • Page 12: Overview

    — Frame Counter — Last Frame and Error Counter — Void Timer for Latency Calculations • Contains an NPI • Contains Extensive Self-Test Capabilities, Scan Path Logic, and Data Parity Generation and Checking • High-Speed CMOS Technology MC68838 USER’S MANUAL MOTOROLA...

  • Page 13: Functional Description

    • Compare the INFO field of claim frames to this station's requested token rotation time. • Perform CRC checking on the received packet. • Store the frame status indicators that have been received. • Keep a count of the number of good and bad frames received. MOTOROLA MC68838 USER’S MANUAL...

  • Page 14: Receive Latch

    ADDRESS COMPARE TRANSMIT SEND FRAME RECEIVE CAPTURE TOKEN COUNTERS TRANSMIT SENT COUNT TIMERS RECEIVE CHECKER TRANSMIT DATA LATCH TEST INTERFACE RECEIVE DATA LATCH MAC-PHY RECEIVE TEST SIGNALS MAC-PHY TRANSMIT SIGNALS SIGNALS Figure 2-1. MAC Block Diagram MC68838 USER’S MANUAL MOTOROLA...

  • Page 15: Receive Crc Checker

    FC field, decodes the current symbol pair on the receive data path, and parses and forwards the received frame status field. This block interprets all the status flags described in the MAC standard: E_FLAG, A_FLAG, C_FLAG, N_FLAG, and R_FLAG. MOTOROLA MC68838 USER’S MANUAL...

  • Page 16: Address Comparator

    The transmit latch logic contains the TXDATx pipeline latch that drives the TXDATx external bus. The TXDATx external bus passes a symbol pair to the ELM chip on the following BYTCLK cycle after the MAC chip has received it. MC68838 USER’S MANUAL MOTOROLA...

  • Page 17: Transmit Data Host Lnterface

    In addition to parsing this information, this block contains the logic to determine when a token can be captured and issued and when a frame can be transmitted. It feeds these signals into the transmit FSM that takes the appropriate action depending upon its current state. MOTOROLA MC68838 USER’S MANUAL...

  • Page 18: Transmit Crc Generator

    A station can then transmit asynchronous frames until this timer expires. This procedure ensures that the sum of this station's transmissions and that of the previous station's transmissions during this rotation of the token are (approximately) less than the mutually agreed upon token rotation time. MC68838 USER’S MANUAL MOTOROLA...

  • Page 19: Transmit Data Latch (and Repeat Function)

    The MAC also has a built-in self-test capability. MOTOROLA MC68838 USER’S MANUAL...

  • Page 20

    MC68838 USER’S MANUAL MOTOROLA...

  • Page 21: Register Description

    A part holds the least significant bits, and the B part holds the most significant bits. The first hex digit of the address refers to NPA5–NPA4, and the second hex digit refers to NPA3–NPA0. MOTOROLA MC68838 USER’S MANUAL...

  • Page 22

    THT Timer, Sent Count Registers SENT_COUNT &THT_TIMER_B Read-Only Packet Request Register PKT_REQUEST Read-Only Receive CRC Register A RC_CRC_A Read-Only Receive CRC Register B RC_CRC_B Read-Only Transmit CRC Register A TX_CRC_A Read-Only Transmit CRC Register B TX_CRC_B Read-Only 3- 2 MC68838 USER’S MANUAL MOTOROLA...

  • Page 23: Register Types

    Whenever the NP attempts to read a nonexistent register, the MAC chip completes the NP read cycle normally (returning a valid, though unpredictable value) and records the erroneous event by setting the NP_ERR bit in the interrupt event register B. MOTOROLA MC68838 USER’S MANUAL...

  • Page 24: Control And Status Registers

    (No timers are running). 1 = The receiver and transmitter finite state machines are operating and can be in any of the states R0–R5 or T0–T5, respectively, or in the FDX states (All timers are running). 3- 4 MC68838 USER’S MANUAL MOTOROLA...

  • Page 25

    DA matches. FLUSH_SA47 has no effect when COPY_ALL is 10 or 11 or when NSA frames are received (i.e., NSA source routing frames will still be received). The current ANSI MAC standard requires the individual/group bit of the SA to be zero. MOTOROLA MC68838 USER’S MANUAL...

  • Page 26

    10 = The MAC additionally copies all NSA frames or 48-bit group-addressed SMT frames whose SA is not matched (subject to COPY_OWN). 11 = The MAC additionally copies all NSA frames or 8-bit addressed SMT frames whose SA is not matched (subject to COPY_OWN). 3- 6 MC68838 USER’S MANUAL MOTOROLA...

  • Page 27

    MATCH and RABORT pins (usually negated during BIST). MTESTx should be 00. Also, the TXPARITY_ON bit should be 0; otherwise, the parity of the nine MOTOROLA MC68838 USER’S MANUAL...

  • Page 28: Control Register B (mac_cntrl_b)

    The MAC performs the following operations: Captures every token (unless RING_OPERATIONAL is zero), Sends any FSI frames for which the token is usable, Sends two special void frames (see the BRIDGE_STRIP bit description), and Releases the token. 3- 8 MC68838 USER’S MANUAL MOTOROLA...

  • Page 29

    SA is matched (M_FLAG = 1—i.e., SA = my long address register and SA<> null) and frame has a valid CRC, length, and E-indicator (E_FLAG = 0. A claim frame is received. A beacon frame is received. A token is received. MOTOROLA MC68838 USER’S MANUAL...

  • Page 30

    TOKEN_TYPE field in the packet request header allows the frame to be sent without a token. When REPEAT_ONLY = 1 and RING_PURGE = 1, the MAC will still capture the token, send two special void frames, and then release the same kind of token. 3- 10 MC68838 USER’S MANUAL MOTOROLA...

  • Page 31

    Whenever the MAC is in the beacon state (T5), a frame is available to transmit at the MAC/FSI interface, and the BCN_FRAME bit is set in its packet request header, the MAC will send this frame. MOTOROLA MC68838 USER’S MANUAL 3- 11...

  • Page 32

    TR_BR_FWD . This signal is the power-up condition, extended DA match, and TR_BR_FWD input.) This bit is set on power up. To use the LDADDR pin in normal mode, the user (initialization firmware) must clear this bit. 3- 12 MC68838 USER’S MANUAL MOTOROLA...

  • Page 33: Receive Status Register (rx_status)

    011 = Rc_Info (R3)—Receive DA, SA, INFO, and CRC 100 = Chk_TK2 (R5')—State used to repeat TT 101 = Listen (R0)—Wait for first idle 110 = Chk_TK1 (R5)—Receive TT of token 111 = Rc_Off—MAC is turned off MOTOROLA MC68838 USER’S MANUAL 3- 13...

  • Page 34

    101 = Parse_INFO—Receiving INFO field of MAC frame 110 = Parse_Value RCV—Rest of INFO field 111 = Reserved L_FLAG—Current Value of L-Flag H_FLAG—Current Value of H-Flag M_FLAG—Current value of M-Flag A_FLAG—Current Value of A-Flag 3- 14 MC68838 USER’S MANUAL MOTOROLA...

  • Page 35: Transmit Status Register (tx_status)

    RING_OPERATIONAL becomes zero, the transmitter enters the FDX states, or the MAC is turned off (MAC_ON = 0). This bit is not cleared (stripping continues) if a duplicate token is received (i.e., a token received while transmitting). FLD_SEQ_STATE—Field Sequence State MOTOROLA MC68838 USER’S MANUAL 3- 15...

  • Page 36

    (except for the second rotation of the token). This counter does not wrap around—i.e., if TRT expires when LATE_CT is seven (111), LATE_CT will continue to be seven until a clear LATE_CT (LATE_CT = 1) action is performed by the transmitter. 3- 16 MC68838 USER’S MANUAL MOTOROLA...

  • Page 37: Interrupt Registers

    This event is signaled when a restricted token is received (i.e., when the receiver FSM signals JK_Received and R_Flag is set), regardless of whether the token is repeated or captured by the transmitter. Also, RING_OPERATIONAL does not affect the setting of this bit. MOTOROLA MC68838 USER’S MANUAL 3- 17...

  • Page 38

    FRAME_RCVD bit is set, FRAME_CT wraps around to 0, and the rest of this register is cleared (e.g., DOUBLE_OVFL is read as zero and remains zero), which is the proper behavior. 3- 18 MC68838 USER’S MANUAL MOTOROLA...

  • Page 39

    Specifically, this bit is set when A_FLAG = true and E_FLAG = false, and the I/G bit of the DA = 0, and Ar = S-Symbol. The A_FLAG is only set upon matching the broadcast address (subject to DISBLE_BRDCST being applicable since no group addresses are considered) or MOTOROLA MC68838 USER’S MANUAL 3- 19...

  • Page 40: Interrupt Event Register B (intr_event_b)

    MAC receiver FSM text and state diagram. Although the receiver only asserts this signal for one clock cycle, as with all MAC interrupts, this interrupt remains set until it is read by the external processor. 3- 20 MC68838 USER’S MANUAL MOTOROLA...

  • Page 41

    This bit is set when the MAC detects an error in the MAC-FSI interface. For example, this bit is set when the TPRITY signal indicates a parity error and TXPARITY_ON is enabled or when the TXCTLx lines do not progress through their required cycle. MOTOROLA MC68838 USER’S MANUAL 3- 21...

  • Page 42

    This bit is set even for reserved-for- implementor frames. On the other hand, this bit is not set if the MAC aborts the transmission of the frame (i.e., sends a fragment). 3- 22 MC68838 USER’S MANUAL MOTOROLA...

  • Page 43: Interrupt Event Register C (intr_event_c)

    MAC_RESET. 3.3.6 Interrupt Mask Register C (INTR_MASK_C) This register implements part of the interrupt mask register corresponding to interrupt mask register C. Each interrupt mask register corresponds bit for bit with the interrupt MOTOROLA MC68838 USER’S MANUAL 3- 23...

  • Page 44: Counter Registers

    Instead of requiring the software to guarantee an interrupt latency of less than 5 µs, due to possible event frequency, these counters keep track of the number of events that occur during a much larger interrupt latency time. 3- 24 MC68838 USER’S MANUAL MOTOROLA...

  • Page 45: Token Count Register (token_ct)

    This bit ordering is unaffected by the value of REVERSE_ADDR in control register A as that bit reversal occurs only across the FSI bus. MSA (MOST SIGNIFICANT) MSA (LEAST SIGNIFICANT) MOTOROLA MC68838 USER’S MANUAL 3- 25...

  • Page 46: My Long Address Register (mla_a, Mla_b, Mla_c)

    T_Max occupies bits 7–0 of this register, and TVX_Value occupies bits 15–8; bits 8 and 0 are the least significant, and bits 15 and 7 are the most significant bits of each register. 3- 26 MC68838 USER’S MANUAL MOTOROLA...

  • Page 47: Protocol Timing Registers

    The least significant 16 bits of the TRT timer occupy register address 2C, and the most significant 8 bits of the TRT timer occupy bits 7–0 of register 2D. Bits 15 and 7 are the MOTOROLA MC68838 USER’S MANUAL 3- 27...

  • Page 48

    0 is the most significant in each register. The upper 8 bits of 3- 28 MC68838 USER’S MANUAL MOTOROLA...

  • Page 49: Tht Timer, Sent Count Registers

    LOWER_CLAIM, MY_CLAIM, HIGHER_CLAIM, OTHER_CLAIM, OTHER_BEACON, MY_BEACON, special void frame, or token. lt is also cleared when RING_OPERATIONAL is false or when the MAC is turned off (MAC_ON = MOTOROLA MC68838 USER’S MANUAL 3- 29...

  • Page 50: Trt Time Remaining Register (t_neg_a, T_neg_b)

    If a second void frame is transmitted before receiving the previously transmitted void frame (i.e., the timer is still counting) the second void frame will not be timed and will have no effect on 3- 30 MC68838 USER’S MANUAL MOTOROLA...

  • Page 51: Internal Registers

    EXTRA_FS BCN_FRAME—Beacon Frame This bit has the inverse value of the BCN_FRAME bit contained in the last packet request header control bytes. USE_R_FLAG—Use R-FLAG This bit contains the value of the internal USE_R_FLAG flip/flop. MOTOROLA MC68838 USER’S MANUAL 3- 31...

  • Page 52: Built-in Self-test Signature Register (bist_signature)

    This field is the inverse of the Extra_FS field contained in the last packet request header control bytes. 3.7.3 Built-In Self-Test Signature Register (BIST_SIGNATURE) The BIST signature register is a 16-bit read-only register that contains the resultant signature after execution of the chip's self-test. 3- 32 MC68838 USER’S MANUAL MOTOROLA...

  • Page 53: Receive Crc Register (rx_crc)

    BYTCLK. This register is only expected to be read in test mode, because test programs do not need consistent values. Reading this register provides the internal CRC register, not its inverse, although the inverse would be transmitted. MOTOROLA MC68838 USER’S MANUAL 3- 33...

  • Page 54: Signal Description

    The rising edge, 0 to 5 V, of BYTCLK defines the beginning of a new cycle and is used to sample some input lines and to allow the chip to start presenting new values on all output lines. MOTOROLA MC68838 USER’S MANUAL...

  • Page 55: Node Processor Interface

    This output will remain asserted (low) until the appropriate interrupt is read to clear the interrupting event(s) or the interrupt is masked by writing a zero into the appropriate interrupt mask register bit. 4- 2 MC68838 USER’S MANUAL MOTOROLA...

  • Page 56: Mac-phy Interface

    2. TXDAT4–TXDAT0 corresponds to the last symbol of the pair transmitted to the fiber. When they are not transmitting, these lines drive the FDDI idle data link code of 10111. 4.4 RECEIVE SYSTEM INTERFACE The receive system interface provides the data path from the MAC to the FSI. MOTOROLA MC68838 USER’S MANUAL...

  • Page 57: Transmit System Interface

    MAC. These lines are used at different times to carry either packet data (either data to be sent or part of the packet request header) or extra control information. These signals must be synchronous to BYTCLK. 4- 4 MC68838 USER’S MANUAL MOTOROLA...

  • Page 58: Cam Interface

    This CMOS-level output signal is used to indicate whether the address being presented to the CAM is the DA or SA field of the received packet. This signal is low when the MAC is receiving fields other than address fields. MOTOROLA MC68838 USER’S MANUAL...

  • Page 59: Test Signals

    This output signal, which is driven by a NAND tree of all inputs, allows for DC parametric testing and AC process performance verification. This signal is not intended for use by the user and should not be connected. 4- 6 MC68838 USER’S MANUAL MOTOROLA...

  • Page 60: Bus Operation

    MACSEL line is sampled and determined to be asserted, the NPAx bus and NPRW line are sampled (NPRW should be high for a read). These signals must also satisfy a setup time and hold time relative to this same rising edge of NPCLK. At least 40 ns after this MOTOROLA MC68838 USER’S MANUAL...

  • Page 61

    NPCLK, the MAC continues to drive the NPDx bus with valid data until after the fourth rising edge of NPCLK. The NP can extend the read cycle indefinitely by maintaining the assertion of MACSEL . BYTCLK (NPCLK) NPRW Figure 5-1. Node Processor Bus Read Cycles MC68838 USER’S MANUAL MOTOROLA...

  • Page 62: Write Cycle

    NP can extend the time it has to three-state the NPDx bus. The negation of MACSEL has no effect on the MAC in a write cycle. See 5.2 Read Cycle for more details. BYTCLK (NPCLK) NPRW Figure 5-2. Node Processor Bus Write Cycles MOTOROLA MC68838 USER’S MANUAL...

  • Page 63

    MC68838 USER’S MANUAL MOTOROLA...

  • Page 64: Mac-phy Interface Operation

    Symbol Code Symbol Code 00000 10100 00001 10100 00010 10100 00011 10100 00100 10100 00101 10111 00110 11100 00111 10011 01000 10000 01001 10001 01010 11001 01011 11101 01100 11000 01101 11000 01110 11000 01111 11000 MOTOROLA MC68838 USER’S MANUAL...

  • Page 65

    MC68838 USER’S MANUAL MOTOROLA...

  • Page 66: Receive Data Path Operation

    FSI packet transmission logic, and RCCTL2–RCCTL0 are for the FSI reception logic. Table 7-1 illustrates the relationship between RCCTLx and RPATHx. RCCTL4–RCCTL3 indicate the end of a token cycle and indicate that the data bus MOTOROLA MC68838 USER’S MANUAL...

  • Page 67

    FSI previously sent. The MC68838 USER’S MANUAL MOTOROLA...

  • Page 68

    END_DATA transfer. The only time they differ is when this frame is a secondary NSA frame and the MAC has been programmed to flush such frames. Therefore, the F-bit can only change from a zero on an END_DATA transfer to a one on a FRAME_STATUS of a secondary NSA frame. MOTOROLA MC68838 USER’S MANUAL...

  • Page 69

    FS indicator field: This field is filled from bit 4 to bit 0 as FS symbols are received (i.e., bit 4 contains the value of the first FS symbol received). 1 = S-symbol, 0 = R-symbol. xx 100 xxxx xxxx Reserved for future use. Must be treated as FILLER. MC68838 USER’S MANUAL MOTOROLA...

  • Page 70

    RABORT (high) for a single data transfer cycle for the MAC to recognize it. The FSI must negate RABORT immediately upon detection of an END_DATA transfer. This signal must be synchronous with BYTCLK. START_DATA DATA FILLER END_DATA FILLER FRAME_STATUS Figure 7-1. Receive Data Flowchart MOTOROLA MC68838 USER’S MANUAL...

  • Page 71: Transmit Data Path Operation

    TX_START can follow this until TXRDY is asserted. TX_DATA or TX_END can always follow this. The FSI requests the token by transferring the packet request header to the MAC. The packet request header, which consists of three bytes of information, is associated with MOTOROLA MC68838 USER’S MANUAL...

  • Page 72

    This configuration causes the second packet request header byte to be held until TXRDY is detected (on the falling edge of SYMCLK when BYTCLK is low). BYTCLK TXRDY TPATH PRH#2 PRH#2 PRH#2 PRH#3 Figure 8-1. TXRDY and Packet Request Header Timing MC68838 USER’S MANUAL MOTOROLA...

  • Page 73: Mac Packet Transmission

    FSI must also pass the packet to the MAC. The packet passed to the MAC contains the following fields: 1. FC field 2. DA field 3. SA field 4. INFO field 5. FCS field (unless the MAC has been requested to generate CRC). MOTOROLA MC68838 USER’S MANUAL...

  • Page 74: Packet Request Header

    0 = Send this frame according to the rules for asynchronous frame transmission. The corresponding bit in the FC field is ignored because the MAC does not examine the FC field. 1 = Send this frame according to the rules for synchronous frame transmission. MC68838 USER’S MANUAL MOTOROLA...

  • Page 75

    (i.e., the transmitter does not know whether or not this frame is a reserved-for- implementor frame). 1 = The MAC transmitter calculates the CRC and appends it to the end of the frame passed to it by the FSI in the FCS field. MOTOROLA MC68838 USER’S MANUAL...

  • Page 76

    001 = TR RR RR ll 101 = TR RR SR ll 010 = TR RR RS ll 110 = TR RR SS II 011 = TR RR RT ll 111 = TR RR ST ll MC68838 USER’S MANUAL MOTOROLA...

  • Page 77: Cam Interface Operation

    1. LDADDR is pulsed for one BYTCLK cycle just before the first byte of both the DA and SA fields is given to the MAC and the CAM from the ELM. The DA signal from the MAC differentiates whether the current address is the DA or SA. LDADDR is MOTOROLA MC68838 USER’S MANUAL...

  • Page 78: Extended Match Mode

    Figure 9-2 shows the sequence of events on the CAM interface when EXT_DA_MATCH is programmed to one (for delayed address matching), which also causes the LDADDR 9- 2 MC68838 USER’S MANUAL MOTOROLA...

  • Page 79

    A two BYTCLK assertion is shown. BYTCLK JK FC TT RCDAT FC TT LDADDR ADDR16 RESTRICTED TOKEN UNRESTRICTED TOKEN Figure 9-3. CAM Interface Timing (Receiving Token Frame for Normal and Extended Match Mode) MOTOROLA MC68838 USER’S MANUAL...

  • Page 80: Extensions To A And C Bit Handling

    Ax = A Transmitted RPT = Repeat Cr = C Received = Don't care Cx = C Transmitted 3. MAC_MODE_CTL = RC_TX_CONTROL control register B Bit 2 EXT_ DA_MATCH = RC_TX_CONTROL control register B Bit 4 9- 4 MC68838 USER’S MANUAL MOTOROLA...

  • Page 81

    5. RABORT or RABORT2 can be used with the MATCH or TR_BR_FWD pin, or in promiscuous mode, to stop the transfer of a frame from the MAC to the FSI and to properly set the C-bit for a rejected or incompletely received frame. MOTOROLA MC68838 USER’S MANUAL...

  • Page 82

    9- 6 MC68838 USER’S MANUAL MOTOROLA...

  • Page 83: Test Operation

    PWRUP for at least 10 BYTCLK cycles. The registers shown in Table 10-1 should be written with the indicated hexadecimal values. The MAC should be clocked with BYTCLK until MACINT is asserted and the BIST value can be compared against the value indicated in Table 10-1. MOTOROLA MC68838 USER’S MANUAL 10-1...

  • Page 84: Scan Path Operation

    (boundary scan serial test mode), then clocking the data in parallel (normal or boundary scan parallel test mode), and finally serially shifting the data out, the I/O latches and interconnections between the various chips can be tested on a PC board. 10-2 MC68838 USER’S MANUAL MOTOROLA...

  • Page 85

    RCDAT6 RCDAT7 RCDAT8 RCDAT9 MSCANO — — — NOTE: MSCANI and MSCANO are not latched pins but represent the input and output of the scan chain, respectively. PKTGEN15–PKTGEN0 are internal latches in the scan chain. MOTOROLA MC68838 USER’S MANUAL 10-3...

  • Page 86

    10-4 MC68838 USER’S MANUAL MOTOROLA...

  • Page 87: Maximum Ratings

    11.3 THERMAL CHARACTERISTICS Characteristic Symbol V a l u e Unit °C/W Thermal Resistance for PGA θ Junction to Ambient (Free Air) 41.6 °C/W Thermal Resistance for QFP θ Junction to Ambient (Free Air) 43.9 MOTOROLA MC68838 USER’S MANUAL 11-1...

  • Page 88: Node Processor Interface Timing

    Time to NPD Driven (Read) — Time to NPD Valid (Read) — Time to NPD Invalid (Read) — NPD Setup Time (Write) — NPD Hold Time (Write) — Time to MACINT Asserted — Time to MACINT Negated — 11-2 MC68838 USER’S MANUAL MOTOROLA...

  • Page 89

    80 NS NPCLK MACSEL READ = 1 NPRW WRITE = 0 VALID ADDRESS VALID DATA (READ) VALID DATA (WRITE) MACINT Figure 11-1. Node Processor Interface Timing MOTOROLA MC68838 USER’S MANUAL 11-3...

  • Page 90: Mac-fsi Timing

    BYTCLK High to TXRDY or TABORT Invalid NOTE: * Timing relative to the falling edge of SYMCLK when BYTCLK is low. 80 NS BYTCLK (NPCLK) SYMCLK RPATH, RCCTL RABORT/ RABORT2 RPRITY TPATH, TXCTL, TPRITY TXRDY, TABORT Figure 11-2. MAC-FSI Timing 11-4 MC68838 USER’S MANUAL MOTOROLA...

  • Page 91: Mac-elm Timing

    RCDAT Hold Time * — NOTE: * Timing relative to the falling edge of SYMCLK when BYTCLK is low. 80 NS BYTCLK 40 NS SYMCLK VALID DATA TXDAT VALID RCDAT DATA Figure 11-3. MAC-ELM Timing MOTOROLA MC68838 USER’S MANUAL 11-5...

  • Page 92: Cam Interface Timing

    4. Figure 11-4 shows timing requirements for the CAM interface signal timing. This figure is drawn based on the functional timing required when EXT_DA_MATCH = 0. For other functional timing, see Section 9. 80 NS BYTCLK SYMCLK RCDAT MATCH TR_BR_FWD LDADDR ADDR16 Figure 11-4. CAM Interface Timing 11-6 MC68838 USER’S MANUAL MOTOROLA...

  • Page 93: Ordering Information And Mechanical Data

    This section contains ordering information, pin assignments, and package dimensions for the MC68838. 12.1 ORDERING INFORMATION Frequency Package Type (MHz) Temperature Order Number Ceramic Pin Grid Array w/Ceramic Lid (KB) 0°C to 70°C MC68838KBC Plastic Quad Gull Wing (FC) 0°C to 70°C MC68838FCC MOTOROLA MC68838 USER’S MANUAL 12-1...

  • Page 94: Pin Assignments

    NPD15 MACSEL NPCLK BYTCLK SYMCLK MACINT NPA2 NPA0 MATCH LDADDR NPA3 TXDAT0 TXDAT3 TXDAT6 RCDAT7 RCDAT5 RCDAT1 NPA1 NPA4 TXDAT1 TXDAT2 TXDAT7 RCDAT8 RCDAT4 RCDAT0 ADDR16 NPA5 TXDAT4 TXDAT5 TXDAT9 TXDAT8 RCDAT9 RCDAT6 RCDAT3 RCDAT2 12-2 MC68838 USER’S MANUAL MOTOROLA...

  • Page 95: 120-lead Plastic Quad Gull Wing (fc)

    MTEST1 NPD5 RPRITY NPD6 RCCTL4 NPD7 MSCANO NPD8 RCCTL3 NPD9 RCCTL2 NPD10 RCCTL1 MC68838 (TOP VIEW) NPD11 RCCTL0 NPD12 NPD13 RABORT NPD14 BYTCLK NPD15 NPCLK MACSEL SYMCLK MACINT LDADDR NPA0 MATCH NPA1 NPA2 ADDR16 NPA3 MOTOROLA MC68838 USER’S MANUAL 12-3...

  • Page 96: Package Dimensions

    1.350 SQ 1.370 SQ 2.21 0.098 2.49 0.087 0.46 (120X) 0.018 (120X) 1.27 (4X) 0.050 (4X) 0.100 BSC 2.54 BSC 43.18 48.26 1.70 0.190 1.143 1.38 0.055 0.045 16.383 16.891 0.645 0.665 16.891 17.145 0.665 0.675 12-4 MC68838 USER’S MANUAL MOTOROLA...

  • Page 97

    0.030 0.036 3.45 3.85 0.136 0.152 0.13 0.18 0.005 0.007 0.25 0.35 0.010 0.014 23.20 REF. 0.913 REF. 23.20 REF. 0.913 REF. DIMENSIONS FOR MOTOROLA CHANDLER MANUFACTURING SITE (FOR ALL NEW DESIGNS) REV. 2.3 1/15/90 MOTOROLA MC68838 USER’S MANUAL 12-5...

  • Page 98

    12-6 MC68838 USER’S MANUAL MOTOROLA...

  • Page 99

    EXT_DA_MATCH 3-12, 4-5, 9-3 MAC_ON 3-4 EXTRA_FS 3-32 MLA_A 3-2, 3-26 MLA_B 3-2, 3-26 MLA_C 3-2, 3-26 — F — MSA 3-2, 3-25 MY_BEACON 3-20 FDX_CHANGE 3-22 MY_CLAIM 3-20 FDX_MODE 3-9 FLD_CNT_STATE 3-16 FLD_SEQ_STATE 3-16 MOTOROLA MC68838 USER’S MANUAL Index-1...

  • Page 100

    RX_FSM_STATE 3-13 VOID_TIMER_REG_RDY 3-23 RX_STATUS 3-2, 3-13 RXPARITY 3-8 — W — — S — WON_CLAIM 3-21 SEND_FIRST 3-32 SEND_LAST 3-32 SENT_COUNT &THT_TIMER_B 3-2 SENT_COUNT 3-28 SET_BIT4 3-5 SET_BIT5 3-5 SET_BIT_4 7-2 SET_BIT_5 7-2 SI_ERR 3-21 Index-2 MC68838 USER’S MANUAL MOTOROLA...

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