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Signal Description; Clock Signals - Motorola MC68838 User Manual

Media access controller
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SECTION 4

SIGNAL DESCRIPTION

This section describes the MAC signals. The MAC is intended to interface with the FSI
device and the ELM device as a physical media interface. Figure 4-1 illustrates the
functional group pinout of the MAC
MTEST1–MTEST0
RCDAT9–RCDAT0
TPATH7–TPATH0
TXCTL1–TXCTL0

4.1 CLOCK SIGNALS

These signals are used to clock and power up the chip.
Byte Clock (BYTCLK)
This TTL-level-compatible input signal has a cycle time of 12.5 MHz during normal
operation. The rising edge, 0 to 5 V, of BYTCLK defines the beginning of a new cycle
and is used to sample some input lines and to allow the chip to start presenting new
values on all output lines.
MOTOROLA
BYTCLK
CLOCKS AND
SYMCLK
MACSEL
NODE PROCESSOR
NPA5–NPA0
INTERFACE
NPRW
TEST INTERFACE
MSCANI
ELM INTERFACE
MATCH
INTERFACE
DA
RECEIVE DATA
RABORT
SYSTEM INTERFACE
TRANSMIT DATA
TPRITY
SYSTEM INTERFACE
Figure 4-1. MAC Functional Pinout
MC68838 USER'S MANUAL
PWRUP
CONTROL
NPCLK
MACINT
NPD15–NPD0
MSCANO
MPTSTO
TXDAT9–TXDAT0
LDADDR/TR_BR_FWD
CAM
ADDR16/RABORT2
RPATH7–RPATH0
RPRITY
RCCTL4–RCCTL0
TXRDY
TABORT
4-1

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