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Token Count Register (Token_Ct); Station Parameter Registers; My Short Address Register (Msa); Frame Count Register (Frame_Ct) - Motorola MC68838 User Manual

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3.4.1 Frame Count Register (FRAME_CT)

The frame count register is a 16-bit unsigned integer register. The frame count register
always wraps from 65535 to 0 even when a double overflow occurs (i.e., when the counter
overflows and the FRAME_RCVD bit is still one from a previous overflow in the interrupt
event register). This register is cleared when read and is not otherwise writable by the NP.
3.4.2 Lost Count, Error Count Register
(LOST_CT, ERROR_CT)
The 6-bit LOST_CT and 6-bit ERROR_CT count register field are stored in one register so
they can be read (and hence cleared) with one NP read operation. The ERROR_CT field
occupies bits 5–0 of this register and LOST_CT field occupies bits 13–8. Bits 0 and 8 are
the least significant, and bits 5 and 13 are the most significant bits of each count. Each
counter is in its own byte. Bits 6, 7, 14, and 15 are always read as zero and are not part of
the counters. This register is always cleared when read and is not otherwise writable by
the NP.
15
14
0
0
7
6
0
0

3.4.3 Token Count Register (TOKEN_CT)

The token count register is a 16-bit unsigned integer value representing the number of
tokens received by this station. This counter wraps from 65535 to 0 even if
TKN_CNT_OVF is set in interrupt event register C. This counter is cleared when read.

3.5 STATION PARAMETER REGISTERS

The station parameter registers are normally written when the MAC is first powered up.
Sometimes it may be necessary to change these values, in which case the MAC chip
operation must first be disabled via the MAC_ON bit in control register A. Then their values
can be changed and the MAC operation can be re-enabled. These registers can be read
during normal MAC operation, but they cannot be changed. The registers in this group are
described in the following paragraphs.

3.5.1 My Short Address Register (MSA)

My short address register is contained in one 16-bit register. The I/G bit is always bit 15 of
this register and is the first bit received. This bit ordering is unaffected by the value of
REVERSE_ADDR in control register A as that bit reversal occurs only across the FSI bus.
15
14
I/G
7
MOTOROLA
13
5
MSA (MOST SIGNIFICANT)
MSA (LEAST SIGNIFICANT)
MC68838 USER'S MANUAL
LOST_CT
ERROR_CT
8
0
8
0
3- 25

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