Eaton EDR-5000 Nstallation, Operation And Maintenance Manual page 1019

Name
Logic.LE46.Timer Out
Logic.LE46.Out
Logic.LE46.Out inverted
Logic.LE46.Gate In1-I
Logic.LE46.Gate In2-I
Logic.LE46.Gate In3-I
Logic.LE46.Gate In4-I
Logic.LE46.Reset Latch-I
Logic.LE47.Gate Out
Logic.LE47.Timer Out
Logic.LE47.Out
Logic.LE47.Out inverted
Logic.LE47.Gate In1-I
Logic.LE47.Gate In2-I
Logic.LE47.Gate In3-I
Logic.LE47.Gate In4-I
Logic.LE47.Reset Latch-I
Logic.LE48.Gate Out
Logic.LE48.Timer Out
Logic.LE48.Out
Logic.LE48.Out inverted
Logic.LE48.Gate In1-I
Logic.LE48.Gate In2-I
Logic.LE48.Gate In3-I
Logic.LE48.Gate In4-I
Logic.LE48.Reset Latch-I
Logic.LE49.Gate Out
Logic.LE49.Timer Out
Logic.LE49.Out
Logic.LE49.Out inverted
Logic.LE49.Gate In1-I
Logic.LE49.Gate In2-I
Logic.LE49.Gate In3-I
Logic.LE49.Gate In4-I
Logic.LE49.Reset Latch-I
Logic.LE50.Gate Out
Logic.LE50.Timer Out
Description
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
www.eaton.com
EDR-5000 IM02602007E
1019