Time - ST STM32F103x6 Manual

STM32F103xx
SPI interface characteristics
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
Refer to
alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 36.
Symbol
f
SCK
1/t
c(SCK)
t
r(SCK)
t
f(SCK)
(2)
t
su(NSS)
(2)
t
h(NSS)
t
w(SCKH)
(2)
t
w(SCKL)
(2)
t
su(MI)
(2)
t
su(SI)
(2)
t
h(MI)
(2)
t
h(SI)
(2)(4)
t
a(SO)
(2)(5)
t
dis(SO)
(2)(1)
t
v(SO)
(2)(1)
t
v(MO)
(2)
t
h(SO)
(2)
t
h(MO)
1. TBD = to be determined.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Depends on f
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Table 7.
Section 5.3.12: I/O port pin characteristics
SPI characteristics
Parameter
SPI clock frequency
SPI clock rise and fall

time

NSS setup time
NSS hold time
(2)
SCK high and low
time
Data input setup time
Data input hold time
Data output access
time
Data output disable
time
Data output valid time
Data output valid time
Data output hold time
. For example, if f
PCLK
Table 36
frequency and V
PCLKx
for more details on the input/output
(1)
Conditions
Master mode
Slave mode
Capacitive load: C=50 pF
Slave mode
Slave mode
Master mode, f
PCLK
presc = TBD
Master mode
Slave mode
Master mode
Slave mode
Master mode, f
PCLK
Slave mode, f
PCLK
Slave mode
Slave mode, f
PCLK
Slave mode
Slave mode (after enable edge)
f = TBD
PCLK
Master mode (after enable
edge)
f = TBD
PCLK
Slave mode (after enable edge)
Master mode (after enable
edge)
= 8MHz, then t = 1/f
PCLK PCLK
Electrical characteristics
are derived from tests
supply voltage conditions
DD
Min
TBD
0
0
0
= TBD,
TBD
TBD
TBD
TBD
TBD
(3)
= TBD TBD
(3)
= TBD TBD
TBD
= TBD TBD
TBD
TBD
TBD
TBD
=125 ns and t
PLCLK v(MO)
Max Unit
TBD
MHz
TBD
TBD
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
= 255 ns.
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