ST STM32F103x6 Manual page 10

STM32F103xx
Table 3. Pin definitions (continued)
Pins
D8 5 5 81
E8 6 6 82
B7 54 83
C7 - - 84
D7 - - 85
B6 - - 86
C6 - - 87
D6 - - 88
A7 39 55 89
A6 40 56 90
C5 41 57 91
B5 42 58 92 PB6/I2C1_SCL/ TIM4_CH1
A5 43 59 93 PB7/I2C1_SDA/ TIM4_CH2 I/O
D5 44 60 94
B4 45 61 95
A4 46 62 96
D4 - - 97
C4 - - 98
E5 47 63 99
F5 48 64 100
1. I = input, O = output, S = supply, HiZ = high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. Refer to
4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in ouptut mode is limited: they can be used
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.
5. Available only on devices with a Flash memory density equal or higher than 64 Kbytes.
6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
UM0306, available from the STMicroelectronics website: www.st.com.
7. For the LQFP48 and LQFP64 packages, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset,
however the functionality of PD0 and PD1 can be remapped by software on these pins.
Pin name
PD0
PD1
PD2/TIM3_ETR
PD3
PD4
PD5
PD6
PD7
PB3/JTDO/TRACESWO
PB4/JNTRST
PB5/I2C1_SMBAl
BOOT0
PB8/TIM4_CH3
PB9/TIM4_CH4
PE0/TIM4_ETR
PE1
V
SS_3
V
DD_3
Main function
(after reset)
I/O FT OSC_IN
I/O FT OSC_OUT
I/O FT PD2
I/O FT PD3
I/O FT PD4
I/O FT PD5
I/O FT PD6
I/O FT PD7
I/O FT JTDO
I/O FT JNTRST
I/O PB5
I/O FT PB6
FT PB7
I BOOT0
I/O FT PB8
I/O FT PB9
I/O FT PE0
I/O FT PE1
S V
SS_3
S V
DD_3
Table 2 on page 7.
Pin descriptions
(3)
Default alternate functions
(7)
(7)
TIM3_ETR
PB3/TRACESWO
PB4
I2C1_SMBAl
I2C1_SCL
TIM4_CH1
I2C1_SDA
TIM4_CH2
TIM4_CH3
TIM4_CH4
TIM4_ETR
(6)
/
(5)(6)
(6)
/
(5) (6)
(5) (6)
(5) (6)
(5)
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