ST STM32F103x6 Manual page 36

Electrical characteristics
Figure 17. Recommended NRST pin protection
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the V
Table 32. Otherwise the reset will not be taken into account by the device.
5.3.14 TIM timer characteristics
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
Refer to
function characteristics (output compare, input capture, external clock, PWM output).
Table 33.
Symbol
t
res(TIM)
f
EXT
Res
TIM
t
COUNTER
t
MAX_COUNT
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
48/67
External
reset circuit
NRST
0.1 µF
Table 7.
Section 5.3.12: I/O port pin characteristics
(1)
TIMx characteristics
Parameter
Timer resolution time
Timer external clock
frequency on CH1 to CH4
Timer resolution
16-bit counter clock period
when internal clock is
selected
Maximum possible count
V DD
R PU
FILTER
Table 33
frequency and V
PCLKx
for details on the input/output alternate
Conditions
f = 72 MHz
TIMxCLK
f = 72 MHz
TIMxCLK
f = 72 MHz 0.0139
TIMxCLK
f = 72 MHz
TIMxCLK
STM32F103xx
Internal Reset
STM32F101xx
ai14132b
max level specified in
IL(NRST)
are derived from tests
supply voltage conditions
DD
Min Max
1
13.9
f /2
0
TIMxCLK
0 36
16
1 65536
910
65536 × 65536
59.6
Unit
t
TIMxCLK
ns
MHz
MHz
bit
t
TIMxCLK
µs
t
TIMxCLK
s