ST STM32F103x6 Manual

ST STM32F103x6 Manual

Performance line, arm-based 32-bit mcu with flash, usb, can, seven 16-bit timers, two adcs and nine communication interfaces

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Performance line, ARM-based 32-bit MCU with Flash, USB, CAN,
seven 16-bit timers, two ADCs and nine communication interfaces
Features
Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz
– Single-cycle multiplication and hardware
division
– Nested interrupt controller with 43
maskable interrupt channels
– Interrupt processing (down to 6 CPU
cycles) with tail chaining
Memories
– 32-to-128 Kbytes of Flash memory
– 6-to-20 Kbytes of SRAM
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz quartz oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 32 kHz RC
– PLL for CPU clock
– Dedicated 32 kHz oscillator for RTC with
calibration
Low power
– Sleep, Stop and Standby modes
– V
supply for RTC and backup registers
BAT
2 x 12-bit, 1 µs A/D converters (16-channel)
– Conversion range: 0 to 3.6 V
– Dual-sample and hold capability
– Synchronizable with advanced control timer
– Temperature sensor
DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
2
I
Cs and USARTs
July 2007
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
STM32F103x8 STM32F103xB
LQFP48
7 x 7 mm
Debug mode
– Serial wire debug (SWD) & JTAG interfaces
Up to 80 fast I/O ports
– 32/49/80 5 V-tolerant I/Os
– All mappable on 16 external interrupt
vectors
– Atomic read/modify/write operations
Up to 7 timers
– Up to three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– 16-bit, 6-channel advanced control timer:
up to 6 channels for PWM output
Dead time generation and emergency
stop
– 2 x 16-bit watchdog timers (Independent
and Window)
– SysTick timer: a 24-bit downcounter
Up to 9 communication interfaces
– Up to 2 x I
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 SPIs (18 Mbit/s)
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
Table 1.
Reference
STM32F103x6 STM32F103C6, STM32F103R6
STM32F103x8
STM32F103xB STM32F103RB STM32F103VB
Rev 2
STM32F103x6
LQFP64
LQFP100
10 x 10 mm
14 x 14 mm
2
C interfaces (SMBus/PMBus)
Device summary
Root part number
STM32F103C8, STM32F103R8
STM32F103V8
Preliminary Data
BGA100
10 x 10 mm
1/67
www.st.com
1

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  • Page 1 – Synchronizable with advanced control timer – Temperature sensor Table 1. Device summary Reference Root part number – 7-channel DMA controller STM32F103x6 STM32F103C6, STM32F103R6 – Peripherals supported: timers, ADC, SPIs, STM32F103C8, STM32F103R8 Cs and USARTs STM32F103x8 STM32F103V8 STM32F103xB STM32F103RB STM32F103VB...
  • Page 2 STM32F103xx Description Device overview Table 2. Device features and peripheral counts (STM32F103xx performance line) Peripheral STM32F103Cx STM32F103Rx STM32F103Vx Flash - Kbytes SRAM - Kbytes General purpose Advanced Control USART GPIOs 12-bit synchronized ADC 10 channels 16 channels Number of channels CPU frequency 72 MHz Operating voltage...
  • Page 3 Description STM32F103xx Figure 1. STM32F103xx performance line block diagram Trace pbus JTAG & SWD POWER Controller = 2 to 3.6V VOLT. REG. JNTRST Ibus 3.3V TO 1.8V CORTEX M3 CPU JTDI FLASH 128 KB JTCK/SWCLK @VDD 64 bit JTMS/SWDIO : 72 MHz Dbus JTDO as AF...
  • Page 4 STM32F103xx Pin descriptions Pin descriptions Figure 2. STM32F103xx performance line LQFP100 pinout VDD_2 VSS_2 PA 13 PA 12 VBAT PA 11 PC13-ANTI_TAMP PA 10 PC14-OSC32_IN PA 9 PC15-OSC32_OUT PA 8 VSS_5 VDD_5 OSC_IN LQFP100 OSC_OUT NRST PD15 PD14 PD13 PD12 PD11 VSSA PD10...
  • Page 5: Table Of Contents

    Pin descriptions STM32F103xx Figure 3. STM32F103xx performance line LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDD_2 VBAT PC13-ANTI_TAMP VSS_2 PA13 PC14-OSC32_IN PA12 PC15-OSC32_OUT PD0 OSC_IN PA11 PD1 OSC_OUT PA10 NRST LQFP64 VSSA...
  • Page 6: Figure

    STM32F103xx Pin descriptions Figure 5. STM32F103xx performance line BGA100 ballout PC14- PC13- PA15 PA14 APA13 OSC32_IN ANTI_TAMP PC15- V BAT PC11 PC10 PA12 OSC32_OUT OSC_IN V SS_5 PC12 PA11 OSC_OUT V DD_5 BOOT0 PA10 NRST V SS_4 V SS_3 V SS_2 V SS_1 V DD_4 V DD_3...
  • Page 7: Pc13-Anti_Tamp

    Pin descriptions STM32F103xx Table 3. Pin definitions Pins Main function Pin name Default alternate functions (after reset) PE2/TRACECK TRACECK PE3/TRACED0 TRACED0 PE4/TRACED1 TRACED1 PE5/TRACED2 TRACED2 PE6/TRACED3 TRACED3 PC13-ANTI_TAMP PC13 ANTI_TAMP PC14-OSC32_IN PC14-OSC32_IN PC15-OSC32_OUT PC15-OSC32_OUT SS_5 SS_5 DD_5 DD_5 OSC_IN OSC_IN OSC_OUT OSC_OUT NRST...
  • Page 8 STM32F103xx Pin descriptions Table 3. Pin definitions (continued) Pins Main function Pin name Default alternate functions (after reset) PA4/SPI1_NSS/ SPI1_NSS USART2_CK/ADC_IN4 USART2_CK / ADC_IN4 PA5/SPI1_SCK/ ADC_IN5 SPI1_SCK / ADC_IN5 PA6/SPI1_MISO/ SPI1_MISO ADC_IN6/TIM3_CH1 ADC_IN6/TIM3_CH1 PA7/SPI1_MOSI/ SPI1_MOSI ADC_IN7/TIM3_CH2 ADC_IN7/TIM3_CH2 PC4/ADC_IN14 ADC_IN14 PC5/ADC_IN15 ADC_IN15 PB0/ADC_IN8/ TIM3_CH3 ADC_IN8/TIM3_CH3...
  • Page 9 Pin descriptions STM32F103xx Table 3. Pin definitions (continued) Pins Main function Pin name Default alternate functions (after reset) PB15/SPI2_MOSI SPI2_MOSI PB15 TIM1_CH3N TIM1_CH3N PD10 PD10 PD11 PD11 PD12 PD12 PD13 PD13 PD14 PD14 PD15 PD15 PA8/USART1_CK/ USART1_CK/ TIM1_CH1/MCO TIM1_CH1 /MCO PA9/USART1_TX/ USART1_TX TIM1_CH2...
  • Page 10 Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, UM0306, available from the STMicroelectronics website: www.st.com. 7. For the LQFP48 and LQFP64 packages, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins.
  • Page 11 Memory mapping STM32F103xx Memory mapping The memory map is shown in Figure Figure 6. Memory map APB memory space 0xFFFF FFFF reserved 0xE010 0000 reserved 0x6000 0000 reserved 4 Kbits 0x4002 3400 reserved 1 Kbit 0x4002 3000 0xFFFF FFFF reserved 3 Kbits 0x4002 2400 0xFFFF F000...
  • Page 12: Vbat

    Electrical characteristics STM32F103xx Figure 7. Pin loading conditions Figure 8. Pin input voltage STM32F103xx pin STM32F103xx pin C = 50 pF V IN ai14141 ai14142 5.1.6 Power supply scheme Figure 9. Power supply scheme V BAT 3.3 V Backup circuitry Po wer swi tch (OSC32K,RTC, 1.8-3.6 V...
  • Page 13: Figure

    STM32F103xx Electrical characteristics 5.1.7 Current consumption measurement Figure 10. Current consumption measurement scheme I DD _V BAT V BAT I DD V DD V DDA ai14126 25/67...
  • Page 14: Nrst

    Electrical characteristics STM32F103xx Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics, Table 5: Current characteristics, and Table 6: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied.
  • Page 15 STM32F103xx Electrical characteristics Table 6. Thermal characteristics Symbol Ratings Value Unit Storage temperature range –65 to +150 °C Maximum junction temperature (see Thermal characteristics) Operating conditions 5.3.1 General operating conditions Table 7. General operating conditions Symbol Parameter Conditions Unit Internal AHB clock frequency HCLK Internal APB1 clock frequency PCLK1...
  • Page 16 Electrical characteristics STM32F103xx 5.3.3 Embedded reset and power control block characteristics The parameters given in Table 9 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table Table 9. Embedded reset and power control block characteristics Symbol Parameter Conditions...
  • Page 17 STM32F103xx Electrical characteristics 5.3.5 Supply current characteristics The current consumption is measured as described in Figure 10: Current consumption measurement scheme. Maximum current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at V or V (no load) All peripherals are disabled except if it is explicitly mentioned...
  • Page 18 Electrical characteristics STM32F103xx Table 12. Maximum current consumption in Stop and Standby modes Symbol Parameter Conditions Unit = 2.4 V = 3.3 V 85 °C 105 °C Regulator in Run mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Supply current in Stop mode...
  • Page 19 STM32F103xx Electrical characteristics Typical current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at V or V (no load). All peripherals are disabled except if it is explicitly mentioned. access time is adjusted to f frequency (0 wait state from 0 to 24 MHz, 1 Flash...
  • Page 20: Symbol Parameter

    Electrical characteristics STM32F103xx Table 14. Typical current consumption in Stop and Standby modes Symbol Parameter Conditions Unit Regulator in Run mode, 3.3 V Low-speed and high-speed internal RC oscillators OFF 2.4 V High-speed oscillator OFF (no independent watchdog) Supply current in µA Stop mode Regulator in Low Power mode,...
  • Page 21: Typ

    STM32F103xx Electrical characteristics 5.3.6 External clock source characteristics High-speed external user clock The characteristics given in Table 15 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table Table 15. High-speed external (HSE) user clock characteristics Symbol Parameter...
  • Page 22 Electrical characteristics STM32F103xx Figure 11. High-speed external clock source AC timing diagram V HSEH V HSEL t W(HSE) t r(HSE) t f(HSE) t W(HSE) T HSE f HSE_ext EXTER NAL OSC _IN CLOCK SOURC E STM32F103xx ai14143 Figure 12. Low-speed external clock source AC timing diagram V LSEH V LSEL t W(LSE)
  • Page 23: Osc_Out

    STM32F103xx Electrical characteristics High-speed external clock The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 17.
  • Page 24 Electrical characteristics STM32F103xx Low-speed external clock The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 18.
  • Page 25 STM32F103xx Electrical characteristics 5.3.7 Internal clock source characteristics The parameters given in Table 19 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table High-speed internal (HSI) RC oscillator (1)(2) Table 19. HSI oscillator characteristics Symbol Parameter Conditions...
  • Page 26 Electrical characteristics STM32F103xx Wakeup time from low power mode The wakeup times given in Table 21 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode.
  • Page 27: Max

    STM32F103xx Electrical characteristics 5.3.9 Memory characteristics Flash memory = − 40 to 105 °C unless otherwise specified. The characteristics are given at T Table 23. Flash memory characteristics Symbol Parameter Conditions Unit = − 40 to +105 °C Word programming time µs prog = −...
  • Page 28: Tbd

    Electrical characteristics STM32F103xx 5.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs.
  • Page 29 STM32F103xx Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values.
  • Page 30: Tbd

    Electrical characteristics STM32F103xx 5.3.11 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
  • Page 31 STM32F103xx Electrical characteristics 5.3.12 I/O port pin characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 29 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table All unused pins must be held at a fixed voltage, by using the I/O output mode, an external pull-up or pull-down resistor (see Figure 15).
  • Page 32 Electrical characteristics STM32F103xx Figure 15. Unused I/O pin connection V DD STM32F103xx 1 0 kΩ UNU SED I/O PORT STM32F103xx UNU SED I/O PORT 1 0 kΩ ai14147b Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed V In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in...
  • Page 33 STM32F103xx Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 30 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table Table 30. Output voltage characteristics Symbol Parameter Conditions Unit Output low level voltage for an I/O pin TTL port when 8 pins are sunk at same time...
  • Page 34 Electrical characteristics STM32F103xx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 16 Table 31, respectively. Unless otherwise specified, the parameters given in Table 31 are derived from tests performed under ambient temperature and V supply voltage conditions summarized in Table Table 31.
  • Page 35: Table 32

    STM32F103xx Electrical characteristics Figure 16. I/O AC characteristics definition t r(I O)out EXT ERNAL t r(I O)out OUTPUT ON 50pF Maximum frequency is achieved if (t r + t f ) £ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.13...
  • Page 36 Electrical characteristics STM32F103xx Figure 17. Recommended NRST pin protection V DD External reset circuit R PU Internal Reset NRST FILTER 0.1 µF STM32F101xx ai14132b 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the V max level specified in IL(NRST) Table...
  • Page 37 STM32F103xx Electrical characteristics 5.3.15 Communications interfaces C interface characteristics Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under ambient temperature, f frequency and V supply voltage conditions PCLK1 summarized in Table The STM32F103xx performance line I C interface meets the requirements of the standard C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true”...
  • Page 38: Table 35

    Electrical characteristics STM32F103xx Figure 18. I C bus AC waveforms and measurement circuit V DD V DD STM32F103xx 4 .7 kΩ 4 .7 kΩ 100Ω C bus 100Ω S TART REPEATED S TART S TART t su(STA) t r(SDA) t f(SDA) t su(SDA) t su(STA:STO) S TOP...
  • Page 39: Time

    STM32F103xx Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under ambient temperature, f frequency and V supply voltage conditions PCLKx summarized in Table Refer to Section 5.3.12: I/O port pin characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
  • Page 40 Electrical characteristics STM32F103xx Figure 19. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) t c(SCK) t h(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA= 0 t w(SCKL) CPOL=1 t v(SO) t r(SCK) t h(SO) t dis(SO) t a(SO) t f(SCK) MISO...
  • Page 41 STM32F103xx Electrical characteristics Figure 21. SPI timing diagram - master mode High NSS input t c(SCK) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t r(SCK) t su(MI) t w(SCKL) t f(SCK) MISO MS BIN BI T6 IN LSB IN INP UT t h(MI)
  • Page 42: Rise Time

    Electrical characteristics STM32F103xx Figure 22. USB timings: definition of data signal rise and fall time Crossover points Differen tial Data L ines V CRS V S S ai14137 Table 38. USB: Full speed electrical characteristics Symbol Parameter Conditions Unit Driver characteristics Rise time = 50 pF Fall Time...
  • Page 43 STM32F103xx Electrical characteristics Table 39. ADC characteristics (continued) Symbol Parameter Conditions Unit External input impedance kΩ (2)(3) External capacitor on analog input < Negative input leakage current | < 400 µA µA on analog pins on adjacent analog pin Sampling switch resistance kΩ...
  • Page 44 Electrical characteristics STM32F103xx Figure 23. ADC accuracy characteristics (1) Example of an actual transfer curve 1023 (2) The ideal transfer curve – 1022 (3) End point correlation line 1LSB ---------------------------------------- - IDEAL 1021 1024 =Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. =Offset Error: deviation between the first actual transition and the first ideal one.
  • Page 45: Figure

    STM32F103xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 25 Figure depending on whether V is connected to V or not. The 10 nF capacitors should be REF+ ceramic (good quality). They should be placed them as close as possible to the chip. Figure 25.
  • Page 46: Table 41

    Electrical characteristics STM32F103xx 5.3.18 Temperature sensor characteristics Table 41. TS characteristics Symbol Parameter Conditions Unit ± linearity with temperature °C SENSE Avg_Slope Average slope 4.478 mV/°C Voltage at 25 °C Startup time µs START 58/67...
  • Page 47 STM32F103xx Package characteristics Package characteristics Figure 27. LFBGA100 - low profile fine pitch ball grid array package outline Seating plane ddd C A2 A4 A3 1 2 3 4 5 6 7 8 9 10 A1 corner index area ∅ (100 balls) (see note 5) ∅...
  • Page 48 Package characteristics STM32F103xx Figure 28. Recommended PCB design rules (0.80/0.75 mm pitch BGA) Dpad 0.37 mm 0.52 mm typ. (depends on solder mask registration tolerance Solder paste 0.37 mm aperture diameter – Non solder mask defined pads are recommended – 4 to 6 mils screen print Dpad 60/67...
  • Page 49 STM32F103xx Package characteristics Figure 29. LQFP100 – 100-pin low-profile quad flat package outline ai14397 Table 43. LQFP100 – 100-pin low-profile quad flat package mechanical data inches Dim. 1.60 0.063 0.05 0.15 0.002 0.006 1.35 1.40 1.45 0.053 0.055 0.057 0.17 0.22 0.27 0.007...
  • Page 50 Package characteristics STM32F103xx Figure 30. LQFP64 – 64 pin low-profile quad flat package outline ai14398 Table 44. LQFP64 – 64 pin low-profile quad flat package mechanical data inches Dim. 1.60 0.063 0.05 0.15 0.002 0.006 1.35 1.40 1.45 0.053 0.055 0.057 0.17 0.22...
  • Page 51 STM32F103xx Package characteristics Figure 31. LQFP48 – 48 pin low-profile quad flat package outline ai14399 Table 45. LQFP48 – 48 pin low-profile quad flat package mechanical data inches Dim. 1.60 0.063 0.05 0.15 0.002 0.006 1.35 1.40 1.45 0.053 0.055 0.057 0.17 0.22...
  • Page 52 Package characteristics STM32F103xx Thermal characteristics The average chip-junction temperature, T , in degrees Celsius, may be calculated using the following equation: x Θ + (P Where: is the Ambient Temperature in ° C, Θ is the Package Junction-to-Ambient Thermal Resistance, in ° C/W, is the sum of P and P is the product of I...
  • Page 53 STM32F103xx Order codes Order codes Table 47. Order codes Flash program SRAM memory memory Part number Package Kbytes Kbytes STM32F103C6T6 LQFP48 STM32F103C8T6 STM32F103R6T6 STM32F103R8T6 LQFP64 STM32F103RBT6 STM32F103V8T6 LQFP100 STM32F103VBT6 STM32F103V8H6 LFBGA100 STM32F103VBH6 Future family enhancements Further developments of the STM32F103xx performance line will see an expansion of the current options.

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