ST STM32F103x6 Manual page 37

STM32F103xx
5.3.15 Communications interfaces
2
I C interface characteristics
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
The STM32F103xx performance line I
2
I C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and V
diode between the I/O pin and V
connected to the I
master node remains powered on. Otherwise, the STM32F103xx would be powered by the
protection diode.
2
The I C characteristics are described in
characteristics
and SCL) .
Table 34.
Symbol
t
w(SCLL)
t
w(SCLH)
t
su(SDA)
t
h(SDA)
t
r(SDA)
t
r(SCL)
t
f(SDA)
t
f(SCL)
t
h(STA)
t
su(STA)
t
su(STO)
t
w(STO:STA)
C
b
1. Values based on standard I
2. f
PCLK1
higher than 4 MHz to achieve the maximum fast mode I
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
Table 7.
is disabled, but is still present. In addition, there is a protection
DD
2
C bus, it is not possible to power off the STM32F103xx while another I
for more details on the input/output alternate function characteristics (SDA
2
I C characteristics
Parameter
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus
line
2
C protocol requirement, not tested in production.
must be higher than 2 MHz to achieve the maximum standard mode I
Table 34
frequency and V
PCLK1
2
C interface meets the requirements of the standard
. As a consequence, when multiple master devices are
DD
Table 34. Refer also to
Standard mode I
Min Max
4.7
4.0
250
(3)
0
1000
300
4.0
4.7
4.0
4.7
400
2
C frequency.
Electrical characteristics
are derived from tests
supply voltage conditions
DD
Section 5.3.12: I/O port pin
2 (1) 2 (1)(2)
C Fast mode I C
Min Max
1.3
0.6
100
(4)
0 900
20 + 0.1C 300
b
20 + 0.1C 300
b
0.6
0.6
0.6
1.3
400
2
C frequency. It must be
2
C
Unit
µs
(3)
ns
µs
µs
µs
pF
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