ST STM32F103x6 Manual page 26

Electrical characteristics
Wakeup time from low power mode
The wakeup times given in
oscillator. The clock source used to wake up the device depends from the current operating
mode:
Stop or Standby mode: the clock source is the RC oscillator
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and V
voltage conditions summarized in
Table 21.
Symbol
t
WUSLEEP
t
WUSTOP
t
WUSTDBY
1. TBD stands for to be determined.
2. The wakeup time from Sleep and Stop mode are measured from the wakeup event to the point in which the
user application code reads the first instruction.
3. The wakeup time from Standby mode is measured from the wakeup event to the point in which the device
exits from reset.
5.3.8 PLL characteristics
The parameters given in
temperature and V
Table 22.
Symbol
f
PLL_IN
f
PLL_OUT
f
VCO
t
LOCK
t
JITTER
1. TBD stands for to be determined.
2. Data based on device characterization, not tested in production.
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Table 21
Low-power mode wakeup timings
Parameter
(2)
Wakeup from Sleep mode
Wakeup from Stop mode
(regulator in run mode)
(2)
Wakeup from Stop mode
(regulator in low power mode)
(3)
Wakeup from Standby mode
Table 22
supply voltage conditions summarized in
DD
PLL characteristics
Parameter
PLL input clock
PLL input clock duty cycle
PLL multiplier output clock
VCO frequency range
PLL lock time
Cycle to cycle jitter (+/-3Σ
peak to peak)
is measured on a wakeup phase with a 8-MHz HSI RC
Table 7.
(1)
Conditions
Wakeup on HSI RC clock
HSI RC wakeup time = 2 µs
HSI RC wakeup time = 2 µs,
Regulator wakeup from LP
mode time = 5 µs
HSI RC wakeup time = 2 µs,
Regulator wakeup from power
down time = 38 µs
are derived from tests performed under ambient
(1)
Test Conditions
When PLL operates
(locked)
V is stable
DD
STM32F103xx
DD
Typ Max
0.75 TBD
4 TBD
7 TBD
40 TBD
Table 7.
Value
(2)
Min Typ Max
8.0
40 60
16 72
32 144
200
TBD TBD
supply
Unit
µs
µs
µs
Unit
MHz
%
MHz
MHz
µs
%