Intel 80960KB Manual page 42

80960KB
T T
a w
CLK2
CLK
LAD31:0
ALE
ADS
BE3:2
BE1:0
W/R
DT/R
DEN
READY
Figure 30. Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad
36
T T T T
d d d
Word Boundary (1, 0, 0, 0 Wait States)
T T
d r a
T T T
w d r