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2.8.1
AC Specification Tables
Symbol
Parameter
T
Processor Clock Period (CLK2)
1
T
Processor Clock Low Time (CLK2)
2
T
Processor Clock High Time (CLK2)
3
T
Processor Clock Fall Time (CLK2)
4
T
Processor Clock Rise Time (CLK2)
5
T
Output Valid Delay
6
T
HLDA Output Valid Delay
6H
T
ALE Width
7
T
ALE Output Valid Delay
8
T
Output Float Delay
9
T
HLDA Output Float Delay
9H
T
Input Setup 1
10
T
Input Hold
11
T
HOLD Input Hold
11H
T
Input Setup 2
12
T
Setup to ALE Inactive
13
T
Hold after ALE Inactive
14
T
Reset Hold
15
T
Reset Setup
16
T
Reset Width
17
NOTES:
1. Clock rise and fall times are not tested.
2. A float condition occurs when the maximum output current becomes less than I
should not be longer than the valid delay.
3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT
chronous or asynchronous.
Table 7. 80960KB AC Characteristics (16 MHz)
Min
Input Clock
31.25
8
8
Synchronous Outputs
2
4
15
2
2
4
Synchronous Inputs
3
5
4
8
10
8
3
5
1281
Max
Units
125
ns
V
= 1.5V
IN
ns
V
= 10% Point = 1.2V
IL
ns
V
= 90% Point = 0.1V + 0.5 V
IH
10
ns
V
= 90% Point to 10% Point (1)
IN
10
ns
V
= 10% Point to 90% Point (1)
IN
25
ns
28
ns
ns
18
ns
20
ns
(2)
20
ns
(2)
ns
(3)
ns
(3)
ns
(3)
ns
(3)
ns
ns
ns
(3)
ns
(3)
ns
41 CLK2 Periods Minimum
. Float delay is not tested; however, it
LO
, INT
, INT
/INT
0
1
2
80960KB
Notes
CC
and INT
may be syn-
R
3
17
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