Intel P4304XXMFEN2 Service Manual page 182

Intel ® Server Chassis P4304XXMFEN2/P4304XXMUXX Product Family System Integration and Service Guide
LED #
Upper Nibble
Checkpoint
Lower Nibble
Lower Nibble
Upper Nibble
Edh
Lower Nibble
Upper Nibble
EFh
Lower Nibble
Upper Nibble
B0h
Lower Nibble
Upper Nibble
B1h
Lower Nibble
Upper Nibble
B2h
Lower Nibble
Upper Nibble
B3h
Lower Nibble
Upper Nibble
B4h
Lower Nibble
Upper Nibble
B5h
Lower Nibble
Upper Nibble
B6h
Lower Nibble
Upper Nibble
B7h
Lower Nibble
Upper Nibble
B8h
Lower Nibble
Upper Nibble
B9h
Lower Nibble
Upper Nibble
Bah
Lower Nibble
Upper Nibble
BBh
Lower Nibble
Upper Nibble
BCh
Lower Nibble
BFh Upper Nibble
164
Diagnostic LED Decoder
LED 3 LED 2 LED 1 LED 0
8h
4h 2h
(MSB) (LSB)
8h
4h 2h
(MSB) (LSB)
1 0 1
1 1 1
1 1 0
1 1 1
1 1 1
1 0 1
0 0 0
1 0 1
0 0 0
1 0 1
0 0 1
1 0 1
0 0 1
1 0 1
0 1 0
1 0 1
0 1 0
1 0 1
0 1 1
1 0 1
0 1 1
1 0 1
1 0 0
1 0 1
1 0 0
1 0 1
1 0 1
1 0 1
1 0 1
1 0 1
1 1 0
1 0 1
1h
1h
Memory Test Failure
1
0
DIMM Configuration/Population Error:
1
0
Indicates a CLTT Table Structure Error.
1
1
Detect DIMM Population
0
1
Set DDR4 Frequency
1
1
Gather Remaining SPD Data
0
1
Program registers on the memory controller level
1
1
Evaluate RAS modes and save rank information
0
1
Program registers on the channel level
1
1
Perform the JEDEC defined initialization sequence
0
1
1
1
Initialize CLTT/OLTT
0
1
Hardware Memory Test and Initialization
1
1
Execute Software Memory Initialization
0
1
Program Memory Map and Interleaving
1
1
Program RAS Configuration
0
1
Description
Train DDR4 ranks