Intel P4304XXMFEN2 Service Manual page 176

Intel ® Server Chassis P4304XXMFEN2/P4304XXMUXX Product Family System Integration and Service Guide
LED #
Upper Nibble
Checkpoint
Lower Nibble
Upper Nibble
01h
Lower Nibble
Upper Nibble
02h
Lower Nibble
Upper Nibble
03h
Lower Nibble
Upper Nibble
04h
Lower Nibble
Upper Nibble
05h
Lower Nibble
Upper Nibble
06h
Lower Nibble
Upper Nibble
A1h
Lower Nibble
Upper Nibble
A3h
Lower Nibble
Upper Nibble
A7h
Lower Nibble
Upper Nibble
A8h
Lower Nibble
Upper Nibble
A9h
Lower Nibble
Upper Nibble
AAh
Lower Nibble
Upper Nibble
ABh
Lower Nibble
Upper Nibble
Ach
Lower Nibble
Upper Nibble
ADh
Lower Nibble
AEh Upper Nibble
158
Diagnostic LED Decoder
LED 3 LED 2 LED 1 LED 0
8h
4h 2h
(MSB) (LSB)
8h
4h 2h
(MSB) (LSB)
0 0 0
0 0 0
0 0 0
0 0 1
0 0 0
0 0 1
0 0 0
0 1 0
0 0 0
0 1 0
0 0 0
0 1 1
UPI RC (Fully leverage without platform change)
1 0 1
0 0 0
1 0 1
0 0 1
1 0 1
0 1 1
1 0 1
1 0 0
1 0 1
1 0 0
1 0 1
1 0 1
1 0 1
1 0 1
1 0 1
1 1 0
1 0 1
1 1 0
1 0 1
1h
1h
0
First POST code after CPU reset
1
0
Microcode load begin
0
0
CRAM initialization begin
1
0
EI Cache When Disabled
0
0
SEC Core at Power on Begin
1
0
Early CPU Initialization during Sec Phase
0
0
Collect Info such as SBSP, Boot Mode, Reset Type Etc.
1
0
Set Up Minimum Path Between SBSP & Other Sockets
1
0
Topology Discovery and Route Calculation
1
0
Program Final Route
0
0
Program Final IO SAD Setting
1
0
Protocol Layer and Other Uncore Settings
0
0
Transition Links to Full Speed Operation
1
0
0
0
1
0
Description
PHY Layer Setting
Link Layer Settings