Eaton EMR-5000 Installation, Operation And Maintenance Manual page 1046

Name
Logic.LE42.Gate Out
Logic.LE42.Timer Out
Logic.LE42.Out
Logic.LE42.Out inverted
Logic.LE42.Gate In1-I
Logic.LE42.Gate In2-I
Logic.LE42.Gate In3-I
Logic.LE42.Gate In4-I
Logic.LE42.Reset Latch-I
Logic.LE43.Gate Out
Logic.LE43.Timer Out
Logic.LE43.Out
Logic.LE43.Out inverted
Logic.LE43.Gate In1-I
Logic.LE43.Gate In2-I
Logic.LE43.Gate In3-I
Logic.LE43.Gate In4-I
Logic.LE43.Reset Latch-I
Logic.LE44.Gate Out
Logic.LE44.Timer Out
Logic.LE44.Out
Logic.LE44.Out inverted
Logic.LE44.Gate In1-I
Logic.LE44.Gate In2-I
Logic.LE44.Gate In3-I
Logic.LE44.Gate In4-I
Logic.LE44.Reset Latch-I
Logic.LE45.Gate Out
Logic.LE45.Timer Out
Logic.LE45.Out
Logic.LE45.Out inverted
Logic.LE45.Gate In1-I
Logic.LE45.Gate In2-I
Logic.LE45.Gate In3-I
Logic.LE45.Gate In4-I
Logic.LE45.Reset Latch-I
Logic.LE46.Gate Out
Description
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
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EMR-5000 IM02602012E
1046