Eaton EMR-5000 Installation, Operation And Maintenance Manual page 1038

Name
Logic.LE9.Timer Out
Logic.LE9.Out
Logic.LE9.Out inverted
Logic.LE9.Gate In1-I
Logic.LE9.Gate In2-I
Logic.LE9.Gate In3-I
Logic.LE9.Gate In4-I
Logic.LE9.Reset Latch-I
Logic.LE10.Gate Out
Logic.LE10.Timer Out
Logic.LE10.Out
Logic.LE10.Out inverted
Logic.LE10.Gate In1-I
Logic.LE10.Gate In2-I
Logic.LE10.Gate In3-I
Logic.LE10.Gate In4-I
Logic.LE10.Reset Latch-I
Logic.LE11.Gate Out
Logic.LE11.Timer Out
Logic.LE11.Out
Logic.LE11.Out inverted
Logic.LE11.Gate In1-I
Logic.LE11.Gate In2-I
Logic.LE11.Gate In3-I
Logic.LE11.Gate In4-I
Logic.LE11.Reset Latch-I
Logic.LE12.Gate Out
Logic.LE12.Timer Out
Logic.LE12.Out
Logic.LE12.Out inverted
Logic.LE12.Gate In1-I
Logic.LE12.Gate In2-I
Logic.LE12.Gate In3-I
Logic.LE12.Gate In4-I
Logic.LE12.Reset Latch-I
Logic.LE13.Gate Out
Logic.LE13.Timer Out
Description
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
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EMR-5000 IM02602012E
1038