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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit)
SVDON: 00FF12H•D4
Controls the turning ON/OFF of the continuous
sampling mode.
When "1" is written: Continuous sampling ON
When "0" is written: Continuous sampling OFF
When "1" is read:
When "0" is read:
The continuous sampling mode goes ON when "1"
is written to SVDON and goes OFF, when "0" is
written.
In the ON status, sampling of the supply voltage is
done continuously in 7.8 msec cycles and the
detection result is latched to SVD0–SVD3.
SVDON can be read, and "1" indicates SVD circuit
operation (BUSY) and "0" indicates standby
(READY).
At initial reset and in the SLEEP status, SVDON is
set to "0" (continuous sampling OFF/READY).
SVDSP: 00FF12H•D5
Controls the turning ON/OFF of the 1/4 Hz auto-
sampling mode.
When "1" is written: Auto-sampling ON
When "0" is written: Auto-sampling OFF
Reading:
The 1/4 Hz auto-sampling mode goes ON when "1"
is written to SVDSP and goes OFF, when "0" is
written.
In the ON status, sampling is done in every 4
seconds and "1" is read from SVDON during the
actual sampling period (7.8 msec).
At initial reset and in the SLEEP status, SVDSP is
set to "0" (auto-sampling OFF).
112
BUSY
READY
Valid
SVD0–SVD3: 00FF12H•D0–D3
The detection result of the SVD is set.
The reading data correspond to the detection levels
as shown in Table 5.13.3.2 and the data is main-
tained until the next sampling.
Table 5.13.3.2 Supply voltage detection results
SVD3
SVD2
SVD1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
For the correspondence between the detection level
and the supply voltage, see "7 ELECTRICAL
CHARACTERISTICS".
The initial value at initial reset is set according to
the supply voltage detected at first sampling by
hardware. Data of this bit is undefined until this
sampling is completed.
5.13.4 Programming notes
(1) To reduce current consumption, turn the SVD
circuit OFF (SVDON = SVDSP = "0") when it is
not necessary.
(2) When executing an SLP instruction while the
SVD circuit is operating, the stop operation of
the OSC1 oscillation circuit is kept waiting until
the sampling is completed. The two bits of
SVDON and SVDSP are automatically reset to
"0" by hardware while waiting for completion of
sampling.
EPSON
SVD0
Detection level
1
1
Level 15
1
0
Level 14
0
1
Level 13
0
0
Level 12
1
1
Level 11
1
0
Level 10
0
1
Level 9
0
0
Level 8
1
1
Level 7
1
0
Level 6
0
1
Level 5
0
0
Level 4
1
1
Level 3
1
0
Level 2
0
1
Level 1
0
0
Level 0
E0C88832/88862 TECHNICAL MANUAL
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