Programming Notes - Epson 0C88832 Technical Manual

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
ESTRA, ESREC, ESERR: 00FF23H•D0, D1, D2
Enables or disables the generation of an interrupt
for the CPU.
When "1" is written: Interrupt enabled
When "0" is written: Interrupt disabled
Reading:
ESTRA, ESREC and ESERR are interrupt enable
registers that respectively correspond to the
interrupt factors for transmitting complete, receiv-
ing complete and receiving error. Interrupts set to
"1" are enabled and interrupts set to "0" are disa-
bled.
At initial reset, this register is set to "0" (interrupt
disabled).
FSTRA, FSREC, FSERR: 00FF25H•D0, D1, D2
Indicates the serial interface interrupt generation status.
When "1" is read:
When "0" is read:
When "1" is written: Resets factor flag
When "0" is written: Invalid
FSTRA, FSREC and FSERR are interrupt factor flags
that respectively correspond to the interrupts for
transmitting complete, receiving complete and
receiving error and are set to "1" by generation of
each factor.
Transmitting complete interrupt factor is generated
at the point where the data transmitting of the shift
register has been completed.
Receiving complete interrupt factor is generated at
the point where the received data has been trans-
ferred into the received data buffer.
Receive error interrupt factor is generated when a
parity error, framing error or overrun error has
been detected during data receiving.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
At initial reset, this flag is reset to "0".
66
Valid
Interrupt factor present
Interrupt factor not present

5.7.10 Programming notes

(1) Be sure to initialize the serial interface mode in
the transmitting/receiving disable status (TXEN
= RXEN = "0").
(2) Do not perform double trigger (writing "1") to
TXTRG (RXTRG) when the serial interface is in
the transmitting (receiving) operation. Further-
more, do not execute the SLP instruction. (When
executing the SLP instruction, set TXEN =
RXEN = "0".)
(3) In the clock synchronous mode, since one clock
line (SCLK) is shared for both transmitting and
receiving, transmitting and receiving cannot be
performed simultaneously. (Half duplex only is
possible in clock synchronous mode.)
Consequently, be sure not to write "1" to
RXTRG (TXTRG) when TXTRG (RXTRG) is "1".
(4) When a parity error or flaming error is gener-
ated during receiving in the asynchronous
mode, the receiving error interrupt factor flag
FSERR is set to "1" prior to the receiving
complete interrupt factor flag FSREC for the
time indicated in Table 5.7.10.1. Consequently,
when an error is generated, you should reset the
receiving complete interrupt factor flag FSREC
to "0" by providing a wait time in error process-
ing routines and similar routines.
When an overrun error is generated, the
receiving complete interrupt factor flag FSREC
is not set to "1" and a receiving complete
interrupt is not generated.
Table 5.7.10.1 Time difference between FSERR
Clock source
f / n
OSC3
Programmable timer
(5) When the demultiplied signal of the OSC3
oscillation circuit is made the clock source, it is
necessary to turn the OSC3 oscillation ON, prior
to using the serial interface.
A time interval of several 100 µsec to several 10
msec, from the turning ON of the OSC3 oscilla-
tion circuit to until the oscillation stabilizes, is
necessary, due to the oscillation element that is
used. Consequently, you should allow an
adequate waiting time after turning ON of the
OSC3 oscillation, before starting transmitting/
receiving of serial interface. (The oscillation
start time will vary somewhat depending on the
oscillator and on the externally attached parts.
Refer to the oscillation start time example
indicated in Chapter 7, "ELECTRICAL CHAR-
ACTERISTICS".)
At initial reset, the OSC3 oscillation circuit is set
to OFF status.
EPSON
and FSREC on error generation
Time difference
1/2 cycles of f
OSC3
1 cycle of timer 1 underflow
E0C88832/88862 TECHNICAL MANUAL
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