Control Of Oscillation Circuit And Operating Mode - Epson 0C88832 Technical Manual

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits and Operating Mode)

5.3.7 Control of oscillation circuit and operating mode

Table 5.3.7.1 shows the control bits for the oscillation circuits and operating modes.
Address Bit Name
00FF02 D7 EBR
General-purpose register
D6 WT2 General-purpose register
D5 WT1
General-purpose register
D4 WT0 General-purpose register
D3 CLKCHG
CPU operating clock switch
D2 OSCC OSC3 oscillation On/Off control
D1 VDC1
Operating mode selection
D0 VDC0
VDC1, VDC0: 00FF02H•D1, D0
Selects the operating mode according to supply
voltage and operating frequency.
Table 5.3.7.2 shows the correspondence between
register preset values and operating modes.
Table 5.3.7.2 Correspondence between register
preset values and operating modes
Operating
VDC1 VDC0
mode
Normal mode 0 0
Low power mode 0 1
×
High speed mode 1
* The V voltage is the value where V
D1
made the standard (GND).
At initial reset, this register is set to "0" (normal
mode).
OSCC: 00FF02H•D2
Controls the ON and OFF settings of the OSC3
oscillation circuit.
When "1" is written: OSC3 oscillation ON
When "0" is written: OSC3 oscillation OFF
Reading:
When the CPU and some peripheral circuits
(output port, serial interface and programmable
timer) are to be operated at high speed, OSCC is to
be set to "1". At all other times, it should be set to
"0" in order to reduce current consumption.
At initial reset, OSCC is set to "0" (OSC3 oscillation
OFF).
E0C88832/88862 TECHNICAL MANUAL
Table 5.3.7.1 Oscillation circuit and operating mode control bits
Function
VDC1 VDC0 Operating mode
×
1 High speed (V
0 1 Low power (V
0 0 Normal
Power Operating
V
D1
voltage frequency
2.2 V 2.4–5.5 V 4.2 MHz
(Max.)
1.3 V 1.8–3.5 V 80 kHz
(Max.)
3.3 V 3.5–5.5 V 8.2 MHz
(Max.)
has been
SS
Valid
1
1
OSC3
On
=3.3V)
D1
=1.3V)
D1
(V =2.2V)
D1
CLKCHG: 00FF02H•D3
Selects the operating clock for the CPU.
When "1" is written: OSC3 clock
When "0" is written: OSC1 clock
Reading:
When the operating clock for the CPU is switched
to OSC3, CLKCHG should be set to "1" and when
the clock is switched to OSC1, CLKCHG should be
set to "0".
At initial reset, CLKCHG is set to "0" (OSC1 clock).
EPSON
0 SR R/W Comment
0 R/W
0 R/W
0 Reserved register
0 R/W
0 R/W
0 R/W
OSC1
0 R/W
Off
0 R/W
0 R/W
Valid
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