Exception Processing Vectors - Epson 0C88832 Technical Manual

Cmos 8-bit single chip microcomputer
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
At initial reset, the interrupt priority registers are
all set to "0" and each interrupt is set to level 0.
Furthermore, the priority levels in each system
have been previously decided and they cannot be
changed.
The CPU can mask each interrupt by setting the
interrupt flags (I0 and I1). The relation between the
interrupt priority level of each system and interrupt
flags is shown in Table 5.14.4.3, and the CPU
accepts only interrupts above the level indicated by
the interrupt flags.
The NMI (watchdog timer) that has level 4 priority,
is always accepted regardless of the setting of the
interrupt flags.
Table 5.14.4.3 Interrupt mask setting of CPU
I1
I0
1
1
Level 4 (NMI)
1
0
Level 4, Level 3 (IRQ3)
0
1
Level 4, Level 3, Level 2 (IRQ2)
0
0
Level 4, Level 3, Level 2, Level 1 (IRQ1)
After an interrupt has been accepted, the interrupt
flags are written to the level of that interrupt.
However, interrupt flags after an NMI has been
accepted are written to level 3 (I0 = I1 = "1").
Table 5.14.4.4 Interrupt flags after acceptance of interrupt
Accepted interrupt priority level
Level 4
(NMI)
Level 3
(IRQ3)
Level 2
(IRQ2)
Level 1
(IRQ1)
The set interrupt flags are reset to their original
value on return from the interrupt processing
routine. Consequently, multiple interrupts up to 3
levels can be controlled by the initial settings of the
interrupt priority registers alone. Additional
multiplexing can be realized by rewriting the
interrupt flags and interrupt enable register in the
interrupt processing routine.
Note: Beware. If the interrupt flags have been
rewritten (set to lower priority) prior to
resetting an interrupt factor flag after an
interrupt has been generated, the same
interrupt will be generated again.
116
Acceptable interrupt
I1
I0
1
1
1
1
1
0
0
1

5.14.5 Exception processing vectors

When the CPU accepts an interrupt request, it starts
exception processing following completion of the
instruction being executed. In exception processing,
the following operations branch the program.
(1) In the minimum mode, the program counter
(PC) and system condition flag (SC) are moved
to stack and in the maximum mode, the code
bank register (CB), PC and SC are moved.
(2) The branch destination address is read from the
exception processing vector corresponding to
each exception processing (interrupt) factor and
is placed in the PC.
An exception vector is 2 bytes of data in which the
top address of each exception (interrupt) processing
routine has been stored and the vector addresses
correspond to the exception processing factors as
shown in Table 5.14.5.1.
Table 5.14.5.1 Vector address and exception
Vector
Exception processing factor
address
000000H
Reset
000002H
Zero division
000004H
Watchdog timer (NMI)
000006H
Programmable timer 1 interrupt
000008H
Programmable timer 0 interrupt
00000AH
K10 input interrupt
00000CH
K04–K07 input interrupt
00000EH
K00–K03 input interrupt
000010H
Serial I/F error interrupt
000012H
Serial I/F receiving complete interrupt
000014H
Serial I/F transmitting complete interrupt
000016H
Stopwatch timer 100 Hz interrupt
000018H
Stopwatch timer 10 Hz interrupt
00001AH
Stopwatch timer 1 Hz interrupt
00001CH
Clock timer 32 Hz interrupt
00001EH
Clock timer 8 Hz interrupt
000020H
Clock timer 2 Hz interrupt
000022H
Clock timer 1 Hz interrupt
000024H
System reserved (cannot be used)
000026H
:
Software interrupt
0000FEH
Note: An exception processing vector is fixed at 2
bytes, so it cannot specify a branch destination
bank address. Consequently, to branch from
multiple banks to a common exception process-
ing routine, the top portion of an exception
processing routine must be described within the
common area (000000H–007FFFH).
EPSON
processing correspondence
E0C88832/88862 TECHNICAL MANUAL
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